TWI707435B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

Info

Publication number
TWI707435B
TWI707435B TW107130333A TW107130333A TWI707435B TW I707435 B TWI707435 B TW I707435B TW 107130333 A TW107130333 A TW 107130333A TW 107130333 A TW107130333 A TW 107130333A TW I707435 B TWI707435 B TW I707435B
Authority
TW
Taiwan
Prior art keywords
ultra
thin
conductive
sealing body
semiconductor
Prior art date
Application number
TW107130333A
Other languages
English (en)
Other versions
TW201947713A (zh
Inventor
張簡上煜
徐宏欣
林南君
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Publication of TW201947713A publication Critical patent/TW201947713A/zh
Application granted granted Critical
Publication of TWI707435B publication Critical patent/TWI707435B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體封裝包括超薄重佈線路結構、半導體晶粒、第一絕緣密封體、半導體晶片堆疊體以及第二絕緣密封體。半導體晶粒配置於超薄重佈線路結構上，且與之電耦合。第一絕緣密封體配置於超薄重佈線路結構上，且密封半導體晶粒。半導體晶片堆疊體配置於第一絕緣密封體上，且電耦合至超薄重佈線路結構。第二絕緣密封體配置於超薄重佈線路結構上，且密封半導體晶片堆疊體與第一絕緣密封體。另提供一種半導體封裝的製造方法。

Description

半導體封裝及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種具有超薄重佈線路結構的半導體封裝及其製造方法。
近年來，半導體封裝技術隨著先進的技術而日益進展。目前對於智慧型手機、消費性產品與可穿戴式元件的市場需求始終是要符合輕、薄、短、小。因此，先進封裝的發展趨勢始終遵循市場需求，並努力不斷降低積體電路（integrated circuit；IC）封裝的尺寸規格（form factor）以及封裝高度。此外，為了滿足目前對多功能半導體封裝的需求，半導體封裝已採用堆疊晶片的技術，以提供具有較大容量的儲存或製程資料的半導體封裝。在多晶片封裝領域，隨著對多功能電子元件需求的快速增長，如何在維持多晶片封裝製程的簡單性的同時，還能夠將多晶片封裝小型化，已成為本領域研究人員的一大挑戰。
本發明提供一種半導體封裝及其製造方法，其可有效降低封裝高度。
本發明提供一種半導體封裝，其包括超薄重佈線路結構、半導體晶粒、第一絕緣密封體、半導體晶片堆疊體以及第二絕緣密封體。半導體晶粒配置於超薄重佈線路結構上，且電耦合至超薄重佈線路結構。第一絕緣密封體位於超薄重佈線路結構上，且密封半導體晶粒。半導體晶片堆疊體配置於第一絕緣密封體上，且電耦合至超薄重佈線路結構。第二絕緣密封體位於超薄重佈線路結構上，且密封半導體晶片堆疊體與第一絕緣密封體。
在本發明的一實施例中，半導體封裝更包括多個第一導線。多個第一導線電耦合至半導體晶粒及超薄重佈線路結構。
在本發明的一實施例中，半導體封裝更包括多個第二導線。多個第二導線電耦合至半導體晶片堆疊體與超薄重佈線路結構。
本發明提供一種半導體封裝的製造方法。本方法包括至少以下步驟。形成超薄重佈線路結構。對超薄重佈線路結構進行電路測試。在超薄重佈線路結構上配置半導體晶粒，以電耦合至超薄重佈線路結構。形成半導體晶片堆疊體與第一絕緣密封體於超薄重佈線路結構上，其中第一絕緣密封體形成於半導體晶片堆疊體的背面上，以密封半導體晶粒，且半導體晶片堆疊體電耦合至超薄重佈線路結構。形成第二絕緣密封體於超薄重佈線路結構上，以密封半導體晶片堆疊體與第一絕緣密封體。
在本發明的一實施例中，其中形成超薄重佈線路結構，且對超薄重佈線路結構進行電路測試包括以下步驟。形成導電層。形成超薄重佈線路結構於導電層上。透過導電層以對的超薄重佈線路結構進行開路測試。在進行開路測試之後，移除導電層。在移除導電層之後，對超薄重佈線路結構進行短路檢查或自動光學檢測。
在本發明的一實施例中，其中形成超薄重佈線路結構，且對超薄重佈線路結構進行電路測試包括以下步驟。形成導電層。形成超薄重佈線路結構於導電層上。透過導電層以對的超薄重佈線路結構進行開路測試。在進行開路測試之後，移除導電層。導電層形成於第一臨時載板上，且在進行開路測試之後及在移除導電層之前，移除第一臨時載板。在進行開路測試之後，將超薄重佈線路結構與導電層轉移至第二臨時載板，且將導電層從超薄重佈線路結構移除時，將超薄重佈線路結構配置於第二臨時載板上。在形成第二絕緣密封體之後，移除第二臨時載板。
在本發明的一實施例中，其中在超薄重佈線路結構上配置半導體晶粒之後，形成多個第一導線，以電耦合至半導體晶粒與超薄重佈線路結構。
在本發明的一實施例中，其中在第一絕緣密封體上配置半導體晶片堆疊體之後，形成多個第二導線，以電耦合至半導體晶片堆疊體與超薄重佈線路結構。
基於上述，本發明能夠實現半導體封裝的小型化。半導體封裝的超薄重佈線路結構有利於降低半導體封裝的整體高度。此外，在晶粒接合之前，對超薄重佈線路結構進行電路測試，可避免晶粒損失等問題產生，這對於高端元件與堆疊記憶體的應用來說十分重要。藉此，可以製造出具有較佳穩定性及良率的半導體封裝。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1K是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。請參照圖1A，形成導電層102於第一臨時載板50上。第一臨時載板50可以是晶片支撐系統（wafer support system，WSS）或是面板支撐系統（panel support system，PSS），但本發明不限於此。在一些實施例中，為了提高後續製程中導電層102從第一臨時載板50的離型性（releasability），可以在第一臨時載板50上形成離型層52。離型層可以為光熱轉換（light to heat conversion；LTHC）黏著層或是其他適宜的黏著層。第一臨時載板50可由玻璃纖維膠片（如：FR-4）、雙馬來酰亞胺三嗪（Bismaleimide Triazine，BT）、陶瓷、玻璃、矽或是其他適宜的材料所組成，其具有適宜的熱膨脹係數（coefficient thermal expansion，CTE）來控制翹曲。其他適宜的載板材料也可以作為第一臨時載板50，只要所述材料能夠承載在其之上所形成的半導體封裝且能夠承受後續的製程即可。在一些實施例中，導電層102的材料可以包括鈦、銅或其組合，但本發明不限於此。導電層102可以藉由物理氣相沉積（physical vapor deposition，PVD）製程、鍍析製程或是其他適宜的製程形成。在一些實施例中，導電層102可以被稱為晶種層（seed layer）。
請參照圖1B，在導電層102上形成超薄重佈線路結構200。舉例來說，超薄重佈線路結構200包括第一區域R1以及與第一區域R1連接的第二區域R2。在一些實施例中，第一區域R1及第二區域R2可以交錯排列。超薄重佈線路結構200可以是扇出型重佈線路層，其包括介電層210、形成於第一區域R1中的第一導電圖案222以及形成於第二區域R2中的第二導電圖案224。第一導電圖案222及第二導電圖案224可以配置於導電層102上，且嵌入介電層210中。舉例來說，藉由微影（photolithography）及蝕刻製程或是其他適宜的製程，而在導電層102上形成並圖案化導電材料（例如銅、鎳、金等），以形成位於第一區域R1中的第一導電圖案222及位於第二區域R2中的第二導電圖案224。接著，在導電層102上形成介電材料（例如氧化矽（silicon oxide）、氮化矽（silicon nitride）、聚醯亞胺（polyimide）、苯環丁烯（benzocyclobutene，BCB）等），以覆蓋第一導電圖案222與第二導電圖案224。接著，可以移除部分的介電材料，以形成用於暴露出至少一部分的第二導電圖案224及/或一部分的第一導電圖案222的開口（未繪示）。本發明對於介電層210及導電層102的形成順序並不加以限制。
上述步驟可以重覆執行多次，以形成電路設計所需的多層（multi-layered）重佈線路層，但本發明不限於此。在一些實施例中，第二導電圖案224可以包括形成於最頂層的介電層210上的多個導電接墊2241。在一些實施例中，可以在第二導電圖案224的導電接墊2241上形成第一金屬層226，以用於後續的打線接合製程。舉例來說，第一金屬層226可以包括銅、鎳、金、其組合或是其他適宜的材料。
在一些實施例中，超薄重佈線路結構200的厚度介於約20μm至約60μm之間。介電層210的楊氏模量可以介於約2.0 GPa至約4.0 GPa之間。在一些實施例中，超薄重佈線路結構200具有微細間距電路（fine line circuitry） ，其線寬/線距（line and space；L/S）為約2μm至約10μm。與傳統的有機基板相比，超薄重佈線路結構200以更薄的結構及更細的線寬/線距提供電性連接功能。
在一些實施例中，在形成超薄重佈線路結構200之後，導電層102電耦合至第一導電圖案222與第二導電圖案224，並進行電路測試（例如，開路測試），以藉由導電層102檢測超薄重佈線路結構200的電性不連續性（electrical discontinuity）。
請參照圖1C與圖1D，在進行開路測試之後，將超薄重佈線路結構200與導電層102轉移至第二臨時載板50a。第二臨時載板50a的材料與第一臨時載板50的材料相似，其具有適宜的熱膨脹係數來控制翹曲。在一些實施例中，可以在第二臨時載板50a上形成與離型層52相似的離型層52a。在將超薄重佈線路結構200轉移至第二臨時載板50a上之後，第二導電圖案224的導電接墊2241與形成於導電接墊2241上的第一金屬層226可以嵌入離型層52a中。
在一些實施例中，進行開路測試之後，可以移除第一臨時載板50。舉例來說，在將超薄重佈線路結構200轉移至第二臨時載板50a上之後，可以施加例如是紫外光雷射、可見光或熱的外部能量至離型層52，使得第一臨時載板50可以朝如圖1C所示的箭頭的方向被剝離。移除第一臨時載板50之後，在第二臨時載板50a上配置超薄重佈線路結構200以及堆疊於超薄重佈線路結構200上的導電層102。由於移除第一臨時載板50，所以暴露出導電層102。接著，可以藉由蝕刻製程或其他適宜的製程將導電層102從超薄重佈線路結構200移除。在另一些實施例中，可以在與移除第一臨時載板50的同一製程中移除導電層102。
在移除導電層102之後，第二臨時載板50a與貼附於其上的超薄重佈線路結構200可以如圖1D所示的上下翻轉（flipped upside down），使得超薄重佈線路結構200的表面200a朝上，以進行後續的製程。在一些實施例中，在藉由例如是蝕刻製程等移除導電層102之後，在表面200a上的第一導電圖案222與第二導電圖案224可以稍微低於（例如：約1μm至3μm）在表面200a上的介電層210。
請參照圖1E，在移除導電層102之後，可以在第一導電圖案222與第二導電圖案224上形成第二金屬層228。在一些實施例中，第二金屬層228被稱為表面處理（surface finish）。舉例來說，無電鍍鎳鈀浸金（electroless nickel electroless palladium immersion gold，ENEPIG）、電鍍鎳金（electroplated Ni/Au）或其類似物可以作為第二金屬層228，以提升第一導電圖案222與第二導電圖案224的接合性（bondability），並用於進一步的電性連接（例如：打線接合製程）。在形成第二金屬層228之後，第二金屬層228可以覆蓋第二導電圖案224的一端，且第一金屬層226覆蓋第二導電圖案224具有導電接墊2241的另一端。
在一些實施例中，移除導電層102之後，可以藉由短路檢查儀或自動光學檢測儀進行短路檢查或自動光學檢測（automated optical inspection；AOI），以檢測超薄重佈線路結構200。由於在後續的晶片安裝製程之前進行開路/短路檢查或自動光學檢測，而可及早發現超薄重佈線路結構200的缺陷，可以消除晶粒損失的問題，進而改善半導體封裝的良率。在一些實施例中，可以進行切割製程，以促進後續的製程。舉例來說，可以切割面板級的超薄重佈線路結構200以形成多個條狀級（strip-level）的超薄重佈線路結構（未繪示）。
請參照圖1F，在進行電路測試（例如，開路/短路檢查或自動光學檢測）之後，在超薄重佈線路結構200上配置半導體晶粒300。在一些實施例中，半導體晶粒300可以用於執行邏輯應用程序。然而，本發明不限於此。其他適宜的主動元件也可以作為半導體晶粒300。在一些實施例中，半導體晶粒300可以藉由打線接合製程電耦合至超薄重佈線路結構200的第一導電圖案222。舉例來說，形成多個第一導線310以用於連接半導體晶粒300與超薄重佈線路結構200。第一導線310的材料可以包括金、鋁或其他適宜的導電材料。在一些實施例中，可以在半導體晶粒300與超薄重佈線路結構200之間配置晶粒黏著膜3001，以防止半導體晶粒300在打線接合製程中脫落。
請參照圖1G，形成半導體晶片堆疊體500與第一絕緣密封體400於超薄重佈線路結構200上。第一絕緣密封體400可以形成在半導體晶片堆疊體500的背面上，以密封半導體晶粒300，且半導體晶片堆疊體500可以電耦合至超薄重佈線路結構200。舉例來說，第一絕緣密封體400包括晶粒黏著膜、晶粒上膜（film over die，FOD）、導線上膜（film over wire，FOW） 或其他適宜的絕緣材料。半導體晶片堆疊體500可以包括例如由NAND閘快取記憶體（NAND flash）所構構成的非揮發性記憶體的記憶體晶片。在一些實施例中，可以藉由打線接合製程以促進後續的製程電耦合至超薄重佈線路結構200的第二導電圖案224。舉例來說，在第一絕緣密封體400上配置半導體晶片堆疊體500之後，形成多個第二導線510，以連接半導體晶片堆疊體500與超薄重佈線路結構200。第二導線510的材料可以與第一導線310相似，但本發明不限於此。
請參照圖1H，在配置半導體晶片堆疊體500之後，形成第二絕緣密封體600於超薄重佈線路結構200上，以密封半導體晶片堆疊體500、第二導線510與第一絕緣密封體400，而提供提供物理支撐及電性隔離。在一些實施例中，第二絕緣密封體600的材料不同於第一絕緣密封體400的材料。舉例來說，第二絕緣密封體600的材料可以選用具有低濕氣吸收率的材料。在一些實施例中，第二絕緣密封體600的材料可以是環氧樹脂、模塑化合物或其他適宜的絕緣材料。可以藉由例如壓縮模塑（compression molding）、轉移模塑（transfer molding）或其他密封製程的製程形成第二絕緣密封體600。在一些實施例中，在形成第二絕緣密封體600之後，第二絕緣密封體600的厚度T1可以大於從超薄重佈線路結構200開始計算至半導體晶片堆疊體500的頂部的高度H1。第一絕緣密封體400可以覆蓋第一導電圖案222，且第二絕緣密封體600可以覆蓋第二導電圖案224。
請參考圖1I，在形成第二絕緣密封體600之後，將第二臨時載板50a從超薄重佈線路結構200移除。在一些實施例中，可以朝如圖1I所示的箭頭的方向移除第二臨時載板50a。第二臨時載板50a的移除製程可以與移除第一臨時載板50相似，為了簡潔起見，故於此不加以贅述。在一些實施例中，可以在移除第二臨時載板50a之後暴露出超薄重佈線路結構200的第二導電圖案224上的導電接墊2241，以用於進一步的電性連接。
請參照圖1J，形成多個導電端子700於與半導體晶粒300相對的超薄重佈線路結構200上，且電耦合至超薄重佈線路結構200。舉例來說，在移除第二臨時載板50a以暴露出導電接墊2241之後，形成導電端子700於第二導電圖案224的導電接墊2241上。導電端子700的材料可以包括銅、錫、金、鎳或其他適宜的導電材料。導電端子700可以是藉由植球（ball placement）、電鍍製程（plating process）或其他適宜的製程而形成的導電凸塊、導電柱或焊球。值得注意的是，導電端子700可以為其他可能的材質、形式和形狀。可以選擇性地進行回焊製程（reflow process），以提升導電端子700與超薄重佈線路結構200之間的附著力。在一些實施例中，導電端子700可以根據設計需求而形成陣列排列，以在超薄重佈線路結構200的導電接墊2241上具有細間距（fine pitch）。在一些實施例中，具有導電端子700形成於其上的導電接墊2241可以被稱為球墊。
請參照圖1K，在形成導電端子700之後，進行單體化製程，以形成獨立的封裝件，且已大致上完成半導體封裝10的製造過程。單體化製程可以包括藉由旋轉刀片、雷射光束或其他適宜的方式進行切割。在單體化之後，第一絕緣密封體400可以密封半導體晶粒300與第一導線310，且第二絕緣密封體600可以密封半導體晶片堆疊體500、第二導線510與第一絕緣密封體400。第二絕緣密封體600可以提供機械保護、電性及環境隔離，進而提升半導體封裝10的可靠度及產量。半導體封裝10的厚度（即，z方向的高度）可以對應於超薄重佈線路結構200的厚度的減少量而減少。舉例來說，半導體封裝10的厚度可以小於800微米，進而達到半導體封裝10的小型化。
圖2A至圖2G是依據本發明另一實施例的半導體封裝的製造方法的剖面示意圖。本實施例的製造方法與圖1A至圖1K所示的製造方法相似。圖式中相同或近似的元件標號表示相同或近似的元件，並且為了簡潔起見不再重複其細節。
請參照圖2A與圖2B，形成導電層104於臨時載板50上。在一些實施例中，導電層104可以是藉由層壓製程或其他適宜的製程而形成於臨時載板50上的雙層導電材料104。舉例來說，雙層導電材料104可以包括與臨時載板50接觸的第一部分1042以及配置於與臨時載板50相對的第一部分1042上的第二部分1044。在一些實施例中，第一部分1042及第二部分1044可以是銅箔，而可以在形成超薄重佈線路結構200’的過程中作為晶種層。在形成導電層104之後，如圖2B所示超薄重佈線路結構200’形成於雙層導電材料104的第二部分1044上。
本實施例中的超薄重佈線路結構200’的形成過程與圖1B所述的相似。兩者的差別在於第一導電圖案222’及第二導電圖案224可以分別包括配置於最頂層的介電層210上的多個導電接墊2221及2241。第一導電圖案222’的導電接墊2221可以在與第二導電圖案224的導電接墊2241相同的製程中形成。在一些實施例中，第一金屬層226可以形成於第二導電圖案224的導電接墊2241與第一導電圖案222’的導電接墊2221上，以用於後續的打線接合製程。
在形成超薄重佈線路結構200’之後，雙層導電材料104（即導電層）電耦合至第一導電圖案222’與第二導電圖案224，且可以進行電路測試（例如，開路測試），以藉由雙層導電材料104檢測超薄重佈線路結構200’的電性不連續性。在本實施例中，由於結構是在未具有額外的載板轉移接合製程的情況下形成於臨時載板50上，因此此階段的電性測試可以僅檢測開路問題，而在製程的後續階段，可以藉由自動光學檢測進行短路檢查（例如，線路橋接）。在一些實施例中，可以進行切割製程，以促進後續的製程。舉例來說，可以切割面板級的超薄重佈線路結構200’以形成多個條狀級的超薄重佈線路結構（未繪示）。
請參照圖2C，在進行開路測試後，將半導體晶粒300配置於超薄重佈線路結構200’上。接著，形成第一導線310於第一導電圖案222’的導電接墊2221上，以電耦合超薄重佈線路結構200’與半導體晶粒300。後續的製程可以與圖1F至圖1H所述的相似。可以形成半導體晶片堆疊體500與位於半導體晶片堆疊體500的背面上的第一絕緣密封體400於超薄重佈線路結構200’上。第一絕緣密封體400可以密封半導體晶粒300、第一導線310以及第一導電圖案222’的導電接墊2221。接著，可以形成第二導線510於第二導電圖案224的導電接墊2241上，以電耦合至超薄重佈線路結構200’與半導體晶片堆疊體500。之後，形成第二絕緣密封體600於超薄重佈線路結構200’上，以密封半導體晶片堆疊體500、第二導線510、第二導電圖案224的導電接墊2241以及第一絕緣密封體400。
請參照圖2D，在形成第二絕緣密封體600之後，將雙層導電材料104的第一部分1042與臨時載板50從雙層導電材料104的第二部分1044移除。在一些實施例中，可以藉由在第一部分1042與第二部分1044之間的介面進行例如雷射剝離製程的物理處理、例如化學蝕刻的化學處理或其他適宜的製程，以移除雙層導電材料104的第一部分1042與臨時載板50，但本發明不限於此。在移除第一部分1042之後，可以暴露出雙層導電材料104的第二部分1044。
請參照圖2E，在分離雙層導電材料104的第一部分1042與第二部分1044之後，藉由蝕刻製程或其他適宜的製程移除第二部分1044，以暴露出超薄重佈線路結構200’。在另一些實施例中，第二部分1044可以與第一部分1042及臨時載板50在相同的製程中被移除。在移除雙層導電材料104的第二部分1044之後，暴露出第一導電圖案222’與第二導電圖案224。
請參照圖2F，在移除雙層導電材料104的第二部分1044後，形成導電端子700於與半導體晶粒300相對的超薄重佈線路結構200’上。舉例來說，導電端子700可以形成於第二導電圖案224上，以透過超薄重佈線路結構200’電耦合至半導體晶粒300。導電端子700的形成製程可以與圖1J中所述的製程類似，且為了簡潔起見，故於此不加以贅述。
請參照圖2G，在形成導電端子700之後，進行單體化製程，以形成獨立的封裝件，且已大致上完成半導體封裝20的製造過程。單體化製程可以相似於圖1K中所述的製程，且為了簡潔起見，故於此不加以贅述。在單體化之後，第一絕緣密封體400可以密封半導體晶粒300、第一導線310與第一導電圖案222’的導電接墊2221，且第二絕緣密封體600可以密封半導體晶片堆疊體500、第二導線510、第二導電圖案224的導電接墊2241與第一絕緣密封體400。
綜上所述，本發明的半導體封裝的超薄重佈線路結構以更薄的結構及更細的線寬/線距尺寸提供扇出電性連接功能。此外，在導電層上形成超薄重佈線路結構，並進行電路測試（例如：開路測試），藉此檢測超薄重佈線路結構的電性不連續性。可以在處理半導體晶粒之前進行短路檢查或自動光學檢測，而可及早發現超薄重佈線路結構的缺陷，藉此避免晶粒損失及提升半導體封裝的良率。另外，第二絕緣密封體具有低濕氣吸收率的材料特性，而可以提供機械保護、電性及環境隔離，藉此提升半導體封裝的可靠度表現。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧半導體封裝50‧‧‧第一臨時載板、臨時載板50a‧‧‧第二臨時載板52、52a‧‧‧離型層102、104‧‧‧導電層104‧‧‧雙層導電材料1042‧‧‧第一部分1044‧‧‧第二部分200、200’‧‧‧超薄重佈線路結構200a‧‧‧表面210‧‧‧介電層222、222’‧‧‧第一導電圖案2221、2241‧‧‧導電接墊224‧‧‧第二導電圖案226‧‧‧第一金屬層228‧‧‧第二金屬層300‧‧‧半導體晶粒3001‧‧‧晶粒黏著膜310‧‧‧第一導線400‧‧‧第一絕緣密封體500‧‧‧半導體晶片堆疊體510‧‧‧第二導線600‧‧‧第二絕緣密封體700‧‧‧導電端子H1‧‧‧高度T1‧‧‧厚度R1‧‧‧第一區域R2‧‧‧第二區域
圖1A至圖1K是依據本發明一實施例的半導體封裝的製造方法的剖面示意圖。 圖2A至圖2G是依據本發明另一實施例的半導體封裝的製造方法的剖面示意圖。
10‧‧‧半導體封裝
200‧‧‧超薄重佈線路結構
300‧‧‧半導體晶粒
310‧‧‧第一導線
400‧‧‧第一絕緣密封體
500‧‧‧半導體晶片堆疊體
600‧‧‧第二絕緣密封體
700‧‧‧導電端子

Claims (9)

  1. 一種半導體封裝，包括：超薄重佈線路結構，所述超薄重佈線路結構包括交替堆疊的多個介電層與多個導電圖案；半導體晶粒，配置於所述超薄重佈線路結構上，且電耦合至所述超薄重佈線路結構；第一絕緣密封體，位於所述超薄重佈線路結構上，且密封所述半導體晶粒，其中所述第一絕緣密封體與所述超薄重佈線路結構直接接觸；半導體晶片堆疊體，配置於所述第一絕緣密封體上，且電耦合至所述超薄重佈線路結構；以及第二絕緣密封體，位於所述超薄重佈線路結構上，且密封所述半導體晶片堆疊體與所述第一絕緣密封體。
  2. 如申請專利範圍第1項所述的半導體封裝，其中：所述超薄重佈線路結構的厚度介於20μm至60μm之間；所述介電層的楊氏模量介於2.0GPa至4.0GPa之間；且所述第一絕緣密封體的材料與所述第二絕緣密封體的材料不同。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述多個導電圖案包括：第一導電圖案，電耦合至所述半導體晶粒；以及 第二導電圖案，電耦合至所述半導體晶片堆疊體，其中所述第一絕緣密封體密封所述第一導電圖案，且所述第二絕緣密封體密封所述第二導電圖案。
  4. 一種半導體封裝的製造方法，包括：形成超薄重佈線路結構；對所述超薄重佈線路結構進行電路測試；在所述超薄重佈線路結構上配置半導體晶粒，以電耦合至所述超薄重佈線路結構；形成半導體晶片堆疊體與第一絕緣密封體於所述超薄重佈線路結構上，其中所述第一絕緣密封體形成於所述半導體晶片堆疊體的背面上，以密封所述半導體晶粒，且所述半導體晶片堆疊體電耦合至所述超薄重佈線路結構；以及形成第二絕緣密封體於所述超薄重佈線路結構上，以密封所述半導體晶片堆疊體與所述第一絕緣密封體，其中形成所述超薄重佈線路結構包括：形成介電層，其中所述介電層的楊氏模量介於2.0GPa至4.0GPa之間；以及形成第一導電圖案與第二導電圖案，其中在配置所述半導體晶粒之後，所述半導體晶粒電耦合至所述超薄重佈線路結構的所述第一導電圖案，且在配置所述半導體晶片堆疊體之後，所述半導體晶片堆疊體電耦合至所述超薄重佈線路結構的所述第二導電圖 案。
  5. 如申請專利範圍第4項所述的半導體封裝的製造方法，其中形成所述超薄重佈線路結構，且對所述超薄重佈線路結構進行電路測試包括：形成導電層；形成所述超薄重佈線路結構於所述導電層上；透過所述導電層以對所述的超薄重佈線路結構進行開路測試；以及在進行所述開路測試之後，移除所述導電層。
  6. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中所述導電層形成於第一臨時載板上，且在進行所述開路測試之後及在移除所述導電層之前，移除所述第一臨時載板。
  7. 如申請專利範圍第6項所述的半導體封裝的製造方法，其中在進行所述開路測試之後，將所述超薄重佈線路結構與所述導電層轉移至第二臨時載板，且將所述導電層從所述超薄重佈線路結構移除時，將所述超薄重佈線路結構配置於所述第二臨時載板上。
  8. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中形成所述導電層包括：將雙層導電材料層壓於臨時載板上，其中所述雙層導電材料包括與所述臨時載板接觸的第一部分及位於所述第一部分上且與 相對於所述臨時載板的第二部分。
  9. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中：在形成所述第二絕緣密封體之後，移除所述雙層導電材料的所述第一部分及所述臨時載板；且在移除所述雙層導電材料的所述第一部分及所述臨時載板之後，移除所述雙層導電材料的所述第二部分，以暴露出所述超薄重佈線路結構。
TW107130333A 2018-05-02 2018-08-30 半導體封裝及其製造方法 TWI707435B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/968,769 US10522512B2 (en) 2018-05-02 2018-05-02 Semiconductor package and manufacturing method thereof
US15/968,769 2018-05-02

Publications (2)

Publication Number Publication Date
TW201947713A TW201947713A (zh) 2019-12-16
TWI707435B true TWI707435B (zh) 2020-10-11

Family

ID=68384030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107130333A TWI707435B (zh) 2018-05-02 2018-08-30 半導體封裝及其製造方法

Country Status (2)

Country Link
US (1) US10522512B2 (zh)
TW (1) TWI707435B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700798B (zh) * 2018-07-12 2020-08-01 南韓商三星電子股份有限公司 半導體封裝
JP2020035957A (ja) 2018-08-31 2020-03-05 キオクシア株式会社 半導体装置
US11024586B2 (en) * 2019-01-22 2021-06-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11948917B2 (en) * 2019-04-23 2024-04-02 Intel Corporation Die over mold stacked semiconductor package
US11424212B2 (en) * 2019-07-17 2022-08-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
CN114843250B (zh) * 2022-07-06 2022-10-21 之江实验室 一种晶圆级集成系统的测试结构及测试方法
CN117438330B (zh) * 2023-12-19 2024-04-02 武创芯研科技(武汉)有限公司 一种基于平面压痕的晶圆级封装rdl再布线层缺陷检测方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201705381A (zh) * 2015-07-17 2017-02-01 矽品精密工業股份有限公司 封裝基板及其製法
TW201714267A (zh) * 2015-10-08 2017-04-16 華亞科技股份有限公司 封裝上封裝構件及其製作方法
TW201810600A (zh) * 2016-06-15 2018-03-16 聯發科技股份有限公司 半導體封裝

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4871280B2 (ja) * 2005-08-30 2012-02-08 スパンション エルエルシー 半導体装置およびその製造方法
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
CN203277370U (zh) 2012-09-14 2013-11-06 新科金朋有限公司 半导体器件
US10192796B2 (en) 2012-09-14 2019-01-29 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
US9761562B2 (en) 2015-05-06 2017-09-12 Micron Technology, Inc. Semiconductor device packages including a controller element
US20160365334A1 (en) 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US20170213801A1 (en) 2016-01-22 2017-07-27 Micron Technology, Inc. Method for manufacturing a package-on-package assembly

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201705381A (zh) * 2015-07-17 2017-02-01 矽品精密工業股份有限公司 封裝基板及其製法
TW201714267A (zh) * 2015-10-08 2017-04-16 華亞科技股份有限公司 封裝上封裝構件及其製作方法
TW201810600A (zh) * 2016-06-15 2018-03-16 聯發科技股份有限公司 半導體封裝

Also Published As

Publication number Publication date
TW201947713A (zh) 2019-12-16
US20190341369A1 (en) 2019-11-07
US10522512B2 (en) 2019-12-31

Similar Documents

Publication Publication Date Title
TWI707435B (zh) 半導體封裝及其製造方法
US10867976B2 (en) Semiconductor packages having dummy connectors and methods of forming same
US10128211B2 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
US11508635B2 (en) Semiconductor package having routable encapsulated conductive substrate and method
JP3701542B2 (ja) 半導体装置およびその製造方法
US10395946B2 (en) Electronic package and manufacturing method thereof
US20180261563A1 (en) Fabrication method of semiconductor package with stacked semiconductor chips
WO2019040205A1 (en) SEMICONDUCTOR DEVICE HAVING SEMI-CONDUCTIVE CHIPS STACKED LATERALLY OFFSET
TW201824500A (zh) 晶片封裝結構及其製造方法
JP3651346B2 (ja) 半導体装置およびその製造方法
TWI585906B (zh) 超薄封裝上封裝ＰｏＰ之封裝
TWI622153B (zh) 系統級封裝及用於製造系統級封裝的方法
TWI777358B (zh) 半導體封裝
US11469173B2 (en) Method of manufacturing a semiconductor structure
US20140291844A1 (en) Semiconductor device and manufacturing method thereof
US20180254232A1 (en) Electronic package and method for manufacturing the same
TW201742167A (zh) 電子封裝件及其製法
US11362057B2 (en) Chip package structure and manufacturing method thereof
US20230260911A1 (en) Electronic device and manufacturing method thereof
US8796867B2 (en) Semiconductor package and fabrication method thereof
TWI834888B (zh) 封裝基板
US20230197520A1 (en) Dummy die placement within a dicing street of a wafer
US20240096721A1 (en) Electronic package and manufacturing method thereof
US20220392861A1 (en) Electronic package and carrier thereof and method for manufacturing the same
KR100922848B1 (ko) 웨이퍼 레벨 패키지 및 그 제조방법