TWI467668B - 封裝的半導體裝置、用於半導體裝置的封裝體及半導體裝置封裝方法 - Google Patents

封裝的半導體裝置、用於半導體裝置的封裝體及半導體裝置封裝方法 Download PDF

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TWI467668B
TWI467668B TW101103214A TW101103214A TWI467668B TW I467668 B TWI467668 B TW I467668B TW 101103214 A TW101103214 A TW 101103214A TW 101103214 A TW101103214 A TW 101103214A TW I467668 B TWI467668 B TW I467668B
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Taiwan
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redistribution layer
layer
integrated circuit
semiconductor device
molding material
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TW101103214A
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TW201312663A (zh
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Chih Wei Lin
Ming Da Cheng
Wen Hsiung Lu
Hsiu Jen Lin
Bor Ping Jang
Chung Shi Liu
Mirng Ji Lii
Chen Hua Yu
Meng Tse Chen
Chun Cheng Lin
Yu Peng Tsai
Kuei Wei Huang
Wei Hung Lin
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Taiwan Semiconductor Mfg Co Ltd
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Description

封裝的半導體裝置、用於半導體裝置的封裝體及半導體裝置封裝方法
本發明係有關於一種半導體技術，特別是有關於一種封裝的半導體裝置、用於半導體裝置的封裝體及半導體裝置封裝方法。
半導體裝置係用於各種不同的電子應用中，諸如個人電腦、手機、數位相機及其他電子設備。半導體業透過不斷縮小最小特徵尺寸(minimum feature size)而持續的改進各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)，其容許更多的部件整合至既有的晶片面積內。這些較小的電子部件也需要較小的封裝，在一些應用中，其使用的面積較過去的封裝來的少。
一些小型的半導體封裝包括：四方扁平封裝(quad flat package,QFP)、針柵陣列封裝(pin grid array,PGA)、球柵陣列封裝(ball grid array,BGA)、覆晶封裝(flip chip,FC)、三維積體電路(three-dimensional integrated circuit,3DIC)、晶圓級封裝(wafer level package,WLP)、走線上方接墊(bond-on-trace,BOT)封裝以及堆疊式封裝(package on package,PoP)結構。然而，這些封裝技術需要使用有機基底，其成本高且具有大的形狀因子(form factor)。
因此，有必要尋求一種用於半導體裝置的封裝結構及封裝方法。
在本發明一實施例中，一種封裝的半導體裝置，包括：一重佈線層，重佈線層包括一第一表面及與第一表面相對的一第二表面；至少一積體電路，耦接至重佈線層的第一表面；複數個金屬凸塊，耦接至重佈線層的第二表面；以及一成型材料，設置於積體電路及重佈線層的第一表面上。
在本發明另一實施例中，一種用於半導體裝置的封裝體，包括：一重佈線層，包括至少一內層介電層及至少一金屬化層，金屬化層形成於內層介電層內，重佈線層具有一第一表面及與第一表面相對的一第二表面，其中複數個走線設置於重佈線層的第一表面上，且其中複數個接合墊設置於重佈線層的第二表面上，接合墊透過位於金屬化層內的接線而分別電性耦接至走線。
在本發明又一實施例中，一種半導體裝置之封裝方法，包括：提供一承載晶圓；在承載晶圓上形成一重佈線層，重佈線層包括至少一內層介電層及至少一金屬化層，金屬化層形成於內層介電層內，重佈線層具有一第一表面及與第一表面相對的一第二表面；將至少一積體電路耦接至重佈線層的第一表面；在積體電路及重佈線層的第一表面上形成一成型材料；在重佈線層的第二表面上形成複數個金屬凸塊；以及去除承載晶圓。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
本文實施例係關於一種半導體裝置的封裝。以下揭露具有一或多個積體電路的單一或多重、橫向或垂直或其組合的封裝體及種種製造方法與配置的許多實施例。
第1至7圖係繪示出根據本發明一實施例之半導體裝置之封裝方法剖面示意圖。首先請參照第1圖，提供一承載晶圓100。承載晶圓100可包括玻璃、矽(例如，矽晶圓)、氧化矽、金屬板或陶瓷材料等。一黏著層102塗覆於承載晶圓100上。黏著層102可包括環氧樹脂、矽膠、聚亞醯胺(polyimide,PI)、聚對苯撐苯並二噁唑(phenylenebenzobisoxazole,PBO)、苯並環丁烯(Benzocyclobutene,BCB)、高分子或金屬等，另外也可使用其他材料。黏著層102可透過旋轉塗佈(spining coating)、印刷、化學氣相沉積(chemical vapor deposition,CVD)或物理氣相沉積(physical vapor deposition,PVD)而形成。
於承載晶圓100上，例如，位於黏著層102上，形成一重佈線層(redistribution layer,RDL)104。重佈線層104可包括內層介電(inter-level dielectric,ILD)層110a、110b、110c以及設置或形成於金屬化層內的接線112。接線112可包括一或多個接觸窗(via)及/或導線。一或多個接觸窗及/或導線可彼此耦接並位於內層介電(ILD)層110a、110b、110c內，如圖所示。在一範例中，接線112包括第一接線112a及第二接線112b。
重佈線層104可透過在黏著層102上形成或塗覆內層介電層110a而形成。內層介電層110a經過曝光、顯影及圖案化而具有開口，以在既定位置露出部份的黏著層102。第一接線112a的製做包括在圖案化的內層介電層110a上形成第一光阻層(未繪示)、圖案化第一光阻層以及在圖案化的內層介電層110a上進行電鍍而形成第一接線112a。接著去除第一光阻層。在本實施例中，內層介電層110b、110c包括一單層結構，其形成或塗覆於第一接線112a上且露出部份的內層介電層110a。內層介電層110b/110c經過曝光、顯影及圖案化而具有開口，以在既定位置露出下方的第一接線112a及內層介電層110a。第二接線112b的製做包括在圖案化的內層介電層110b/110c上形成第二光阻層(未繪示)、圖案化第二光阻層以及在圖案化的內層介電層110b/110c上進行電鍍而形成第二接線112b。接著去除第二光阻層。
另外，重佈線層104的接線112可透過一或多個單鑲嵌或雙鑲嵌技術來圖案化內層介電層110a、110b及110c並填入導電材料於圖案內而形成。或者，接線112可透過一或多道蝕刻製程而形成，並於每一道蝕刻製程之後，將介電層110a、110b及110c形成於接線112上。
重佈線層104包括一第一表面106，用以連接至一半導體裝置或積體電路(IC)116。重佈線層104也包括一第二表面108，其相對於第一表面106，用以作為封裝體的電性連接，例如在前後端應用(end application)中使用。一部份的接線112位於重佈線層104的第一表面106上，包括走線114，其能夠耦接至積體電路116的接點，且在一些實施例中，使用走線上方接墊(BOT)貼合技術而貼附於重佈線層104上。
如第2圖所示，一積體電路116貼附於重佈線層104上。積體電路116可包括一工作部件(workpiece)或基底(未繪示)，其上具有一或多個電路。積體電路116可包括邏輯電路、記憶裝置或其他類型的電路。積體電路116的表面上包括複數個接觸墊122。可形成金屬柱體(pillar)118，其耦接至接觸墊122，且可形成一焊料凸塊120，其形成於每一金屬柱體118上。金屬柱體118可包括銅或其他金屬，且為非必需的(在一些實施例中，可不具有金屬柱體118)。更確切地說，在一些實施例中，焊料凸塊120可直接形成於積體電路116的接觸墊122上。透過將焊料凸塊120接合至接線112的走線114，積體電路116可接合至重佈線層104的接線112。
如第3圖所示，一成型材料(molding compound)124形成於積體電路116及重佈線層104上。在一些實施例中，成型材料124可包括壓縮成型材料且可包括環氧化物、橡膠、或PI，然而成型材料124也可包括其他材料。成型材料124可局部填入積體電路116下方的空間，例如重佈線層104與積體電路116之間的空間，如圖所示。
接著，如第4圖所示，去除承載晶圓100及黏著層102，以露出重佈線層104的接線112的第二表面108的部分126。
露出部分126可包括用於金屬凸塊的接合墊(landing pad)。在一些實施例中，露出部分126可包括用於焊球或焊料凸塊的接合墊。
第5圖係繪示出第4圖的反向圖。金屬凸塊128形成於接線112的露出部分126。在本實施例中，金屬凸塊128包括焊球。如第6圖所示，一成型材料130包括相似於成型材料124所列出的材料，且可選擇性地形成於金屬凸塊128之間的重佈線層104上，然而兩成型材料並不需要使用相同的材料。在一些實施例中，成型材料130的厚度約為10微米(μm)，然而成型材料130也可具有其他的尺寸。成型材料130薄到足以使金屬凸塊128的頂部突出於成型材料130。在一些實施例中，成型材料130的厚度可為金屬凸塊高度的一半。成型材料130的優點在於可使用大型積體電路116，以改善其可靠度。
接著使用晶片切割刀具或其他裝置在複數個封裝的積體電路116(例如，複數個積體電路116同時形成於承載晶圓100的表面(未繪示))的切割線(singulation line)132進行單體化(singulation)，而分開複數個封裝的積體電路116。如第7圖所示，每一個封裝的積體電路116形成一封裝的半導體裝置140。在第1至7圖所示的實施例中，每一單一積體電路116使用重佈線層104進行封裝，非必需的成型材料130位於一側，而另一成型材料124位於另一側。新的封裝的半導體裝置140的優點在於不需要基底。重佈線層104的局部接線112可將重佈線層104上的金屬凸塊128耦接於積體電路116的接觸墊122。接著，封裝的半導體裝置140可利用其金屬凸塊128而耦接至一印刷電路板(printed circuit board,PCB)、另一封裝的積體電路、一電子或機械模組或其他裝置。
在其他實施例中，如第8及9圖的剖面示意圖所示，二或多個積體電路116a、116b及116c可橫向封裝於單一封裝體中。在重佈線層104形成於承載晶圓100上之後，複數個積體電路116a、116b及116c係接合至重佈線層104的第一表面106。在一些實施例中，積體電路116a可包括一邏輯晶片，且積體電路116b及116c可包括被動元件。另外，積體電路116a、116b及116c也可用於進行其他功能。在一些實施例中，積體電路116a、116b及116c可用於進行相同的功能、同的功能或其組合。第8及9圖係繪示出三個積體電路116a、116b及116c。另外，複數個積體電路116a、116b及116c也可橫向地封裝於單一封裝體中。
接著進行第3至7圖所述的封裝技術，其結果如第9圖所示的封裝的積體電路/半導體裝置140a。封裝的半導體裝置140a包括一多重的晶片封裝，其中積體電路116a、116b及116c彼此相鄰且橫向設置於封裝的半導體裝置140a內。積體電路116a、116b及116c可透過重佈線層104內的接線112而耦接在一起，如圖所示。封裝的半導體裝置140a的優點在於包括系統及封裝(system in package,SiP)。
第10至20圖係繪示出一實施例之剖面示意圖，其中形成具有打線墊(wire bond)的z軸連接器134，以將二或多個積體電路進行垂直式封裝，且其中具有接線136(請參照第14圖)的x-y連接器形成於一金屬化層內。其中第10至20圖中相同於第1至9圖的部件係使用相同的標號，為了避免贅述，在第10至20圖中這些部件將省略其說明。
在形成如第1圖所示的重佈線層104之後，具有打線墊的z軸連接器134形成於重佈線層104上，並耦接至接線112的露出部分，如第10圖所示。z軸連接器134使用於將重佈線層104垂直地耦接至位於封裝體內的一積體電路或另一層接線，以下將進一步說明。在第10至20圖中z軸連接器134大體上垂直於由重佈線層104橫向形成的x-y平面。如第11圖所示，將至少一積體電路116a的焊料凸塊120a耦接至重佈線層104的走線114。第11圖中僅繪示單一積體電路116a。然而，複數個積體電路116a可形成於重佈線層104上。如第12圖(如第2及3圖所述)所示，於積體電路116a、z軸連接器134及重佈線層104上形成一第一成型材料124a。在本實施例中，成型材料124a包括一第一成型材料。如第13圖所示，成型材料124a的頂部透過研磨製程來去除，例如化學機械研磨(chemical mechanical polishing,CMP)製程160，以露出具有打線墊的z軸連接器134的上表面。可透過回蝕刻製程來去除一部份的成型材料。在其他實施例中，可控制成型材料的沉積，使z軸連接器134的上表面在進行成型材料的沉積製程之後維持露出狀態，因而不需要去除部分的成型材料。
如第14圖所示，接著於成型材料124a及具有打線墊的z軸連接器134上形成接線136。接線136耦接至z軸連接器134並提供用於封裝的x-y連接器。接線136的局部包括走線138。如第15圖所示，將至少一積體電路116b及/或116c貼附至接線136。第15圖係繪示出二個積體電路116b及116c。然而，複數個積體電路116b及116c可形成於重佈線層104的表面。部分的積體電路116b及116c可位於下方積體電路116a上方。積體電路116b的焊料凸塊120b耦接至接線136的走線138。積體電路116c的焊料凸塊120c也耦接至接線136的走線138。
如第16圖所示，於上述結構上方(例如，形成於積體電路116a、116b及116c、接線136及第一成型材料124a上方)形成一第二成型材料124b，其包括相似於第一成型材料124a所述的材料。如第17圖所示，接著去除承載晶圓100及黏著層102。如第18圖所示，於重佈線層104上形成金屬凸塊128，且如第19圖所示，可於金屬凸塊128之間的重佈線層104上選擇性地形成一成型材料130。如第20圖所示，接著在切割線132處對重佈線層104進行切割，以形成封裝的半導體裝置140b。
封裝的半導體裝置140b包括多重晶片封裝，其中積體電路116a、116b及116c在封裝體中呈垂直式設置。積體電路116a、116b及116c可透過重佈線層104的接線112及透過由具有打線墊的z軸連接器所提供的垂值連接器而耦接在一起，如圖所示。封裝的半導體裝置140b的優點在於包括系統級封裝(SiP)。
第21至22圖係繪示出一實施例之剖面示意圖，其包括具有打線墊的z軸連接器，且其中一第二重佈線層104b係形成於z軸連接器上。在本實施例中，第10圖所示的重佈線層104第21及22圖中標示為104a。所進行的封裝製程步驟如第10至14圖所示。接著，於接線136上形成具有一絕緣材料層142的一第二重佈線層104b。接線136為第二重佈線層104b的一部分且在本實施例中提供用於封裝的x-y連接器。
如第21圖所示，利用微影製程來圖案化絕緣材料層142，以露出部分的接線136。如第22圖所示，進行如第17至20圖所述的製程，以形成封裝的半導體裝置140c。第二重佈線層104b的露出區域可用於將封裝的半導體裝置140c貼附於另一積體電路、PCB、或另一類型的裝置(未繪示)。
在另一實施例中，如第23圖所示，封裝的半導體裝置140d內可不具有任何的x-y連接器或第二重佈線層。進行第10至13圖的製程步驟，但不形成如第14圖所示的接線136。更確切的說，進行第17至20圖所示的製程步驟，以形成如第23圖所示的封裝的半導體裝置140d。具有打線墊的z軸連接器134的露出端146可用於另一封裝體或裝置，取決於前後端應用。
第24及25圖係繪示出一實施例之剖面示意圖，其中z軸連接器134包括焊球，且其中x-y連接器製做於金屬化層內，例如接線136。在本實施例中，在形成如第1圖所示的重佈線層104之後，包括焊球的z軸連接器134形成於重佈線層104上，而耦接至接線112的露出部，如第24圖所示。如第25圖所示，包括焊球的z軸連接器134係將重佈線層104耦接至後續所形成的積體電路116b及116c。進行如第11至20圖所述的製程步驟，以形成如第25圖所述的封裝的半導體裝置140e。封裝的半導體裝置140e包括多重晶片封裝，其中積體電路116a與積體電路116b及116c垂直放置於封裝體中。積體電路116a、116b及116c可透過重佈線層104內的接線112及/或透過由包括含焊球的z軸連接器134所提供的垂直連接而耦接在一起，如圖所示。封裝的半導體裝置140e的優點在於包括系統級封裝(SiP)。
第24及25圖所示的實施例可作相似於第10至20圖所示的實施例的更動。舉例來說，可形成一第二重佈線層104b，如第26圖所示，且如第21及22圖所述。如第26圖所示，包括焊球的z軸連接器134將封裝的半導體裝置140f的第一重佈線層104a耦接至第二重佈線層104b。在另一實施例中，如第27圖所示，封裝的半導體裝置140g不具有接線136也不具有第二重佈線層104b。本實施例的封裝的半導體裝置140g的優點在於具有金屬凸塊128位於一側，而包括焊球的z軸連接器134則位於另一側。
第28及29圖係繪示出一實施例之剖面示意圖，其中z軸連接器134包括金屬柱體(metal pillar)，且其中x-y連接器製做於金屬化層內，例如接線136。在本實施例中，如第28圖所示，在形成如第1圖所示的重佈線層104之後，包括金屬柱體的z軸連接器134形成於重佈線層104上，耦接至接線112的露出部。如第29圖所示，包括金屬柱體的z軸連接器134係將重佈線層104耦接至後續所形成的積體電路116b及116c。
金屬柱體的製做是透過先形成重佈線層104，接著再重佈線層104上形成一光阻層(未繪示)。將光阻層圖案化以形成金屬柱體所需的圖案。接著可使用電鍍技術而形成金屬柱體。接著去除光阻層。
進行如第11至20圖所述的製程步驟，以形成如第25圖所述的封裝的半導體裝置140h。封裝的半導體裝置140h包括多重晶片封裝，其中積體電路116a與積體電路116b及116c垂直放置於封裝體中。積體電路116a、116b及116c可透過重佈線層104內的接線112及/或透過由包括含金屬柱體的z軸連接器134所提供的垂直連接而耦接在一起，如圖所示。封裝的半導體裝置140h的優點在於包括系統級封裝(SiP)。
第28及29圖所示的實施例可作相似於第10至20圖所示的實施例以及第24及25圖所示的實施例的更動。舉例來說，可形成一第二重佈線層104b，如第30圖所示，且如第21及22圖所述。包括金屬柱體的z軸連接器134將封裝的半導體裝置140i的第一重佈線層104a耦接至第二重佈線層104b。在另一實施例中，如第31圖所示，封裝的半導體裝置140j不具有接線136，也不具有第二重佈線層104b。本實施例的封裝的半導體裝置140j的優點在於具有金屬凸塊128位於一側，而包括金屬柱體的z軸連接器1 34則位於另一側。
第32至38圖係繪示出一實施例之剖面示意圖，其中包括一基底通孔電極(through-substrate via,TSV)的積體電路116a係與至少一其他積體電路116b及116c(如第36圖所示)進行垂直式封裝。如第32圖所示，積體電路116a包括一基底148及形成於其表面上的一絕緣材料層149。於絕緣材料層149內以及一部分的基底148內形成複數個基底通孔電極(TSV)150。於基底通孔電極150及絕緣材料層149上形成複數個金屬化層152。金屬化層152包括形成於絕緣材料層158內的複數個導線及接觸窗154。
在進行第1圖所述的封裝步驟之後，積體電路116a係耦接至第一重佈線層104a，如先前實施例所述。例如，積體電路116a的接觸墊122a透過金屬柱體118a及焊料凸塊120a而耦接至接線112的走線114。如第33圖所示，於積體電路116a及第一重佈線層104a上形成一第一成型材料124a，且封裝體進行一或多道CMP製程160或是蝕刻製程，其去除第一成型材料124a的頂部且去除積體電路116a的局部基底148，而露出基底通孔電極150的上表面162，亦如第33圖所示。如第34圖所示，於積體電路116a及第一成型材料124a上形成一隔離層，其包括一絕緣材料層164，且使用微影製程來圖案化絕緣材料層164，以在絕緣材料層164內形成開口166，並露出基底通孔電極150的上表面162。如第35圖所示，於絕緣材料層164上形成一導電材料，且使用微影製程來圖案化，以形成接線136，其耦接至基底通孔電極150的上表面162。在本實施例中，接線136及絕緣材料層164係作為第二重佈線層140b。
如第36圖所示，將至少一積體電路116b或116c貼附於第二重佈線層140b的接線136。第36圖係繪示出二個積體電路116b及116c。另外，可於第二重佈線層104b的表面上形成複數個積體電路116b及116c，如其他實施例所述。至少局部的積體電路116b及116c可位於下方膜層內的積體電路116a上，而在其他實施例中積體電路116b及116c整體位於積體電路116a上，如圖所示。積體電路116b的焊料凸塊120b耦接至接線136的走線138，且積體電路116c的焊料凸塊120c耦接至接線136的走線138。
如第37圖所示，一第二成型材料層124b包括相似於第一成型材層124a的材料，且形成於上述結構上。例如，位於積體電路116b及116c、接線136及絕緣材料層164上。如第37圖所示，去除承載晶圓100及黏著層102。如第38圖所示，於第一重佈線層104a上形成金屬凸塊128，且於金屬凸塊128之間的第一重佈線層104a上可選擇性地形成一成型材料層130。接著切割此結構，以形成封裝的半導體裝置140k，如第38圖所示。
新的封裝的半導體裝置140k包括一三維積體電路(3DIC)，其包括具有基底通孔電極150的一積體電路116a。封裝的半導體裝置140k包括一多重晶片封裝，其中積體電路116a與積體電路116b及116c垂直放置於封裝體中。積體電路116a、116b及116c可透過第一重佈線層104a內的接線112、透過由積體電路116a的基底通孔電極150所提供的垂直連接及/或第二重佈線層104b內的接線136而耦接在一起，如圖所示。封裝的半導體裝置140k的優點在於包括系統級封裝(SiP)。
第39圖係繪示出關於第32至38圖所示的實施例的另一實施例，其中於具有基底通孔電極的積體電路116a上形成一第二重佈線層104b。封裝的半導體裝置140m包括單一積體電路116a，且電性連接器可製做於封裝體中第二重佈線層104b的露出部上，如先前第22、26及30圖的實施例所述。
在第1至39圖的實施例中，先提供一承載晶圓100，而重佈線層104或第一重佈線層104a形成於承載晶圓100上。當封裝製程不再需要承載晶圓100時，將其去除。
在第40至66圖的實施例中，係使用了承載晶圓，其包括一基底268，且基底268在形成重佈線層104及接合墊(landing pad)期間包括一犧牲裝置。第40至66圖係使用相同於第1至39圖中的標號。為了避免贅述，在第40至66圖中這些部件將省略其說明。當然，相似材料x00、x02、x04等等係用於說明使用於第1至39圖中各個材料層及部件，其中x在第40至66圖中為2。
第40至47圖係繪示出根據本發明另一實施例之封裝一積體電路216a的方法或橫向封裝二個以上積體電路216a及216b的方法剖面示意圖，其中封裝體的連接包括具有焊球的金屬凸塊。首先，如第40圖所示，提供一基底268。基底268可包括一半導體材料，例如矽。在一些實施例中，基底268包括一空白矽晶圓。本文中(例如，在申請專利範圍中)基底268也稱作承載晶圓。在本實施例中，基底268包括一第一承載晶圓。
如第40圖所示，在基底268上形成一絕緣材料層210，且使用微影製程進行圖案化。如第41圖所示，使用蝕刻製程(例如，乾蝕刻或濕蝕刻)去除基底268的上表面。絕緣材料層210可作為蝕刻製程的罩幕層。絕緣材料層210將作為重佈線層204的絕緣材料層。
接著，如第42圖所示，在絕緣材料層210上形成接線212。可透過在絕緣材料層210以及基底268的露出部上沉積一導電材料，並圖案化導電材料而形成接線212。接線212的製做可透過濺鍍由Ti/Cu所構成的一第一層及在Ti/Cu層上電鍍一Ni/Cu層而形成。另外，可使用其他方法來形成接線212。接線212包括走線214，用以將積體電路216a或216b的焊料凸塊220a或220b連接至重佈線層204。在本實施例中，接線212及絕緣材料層210係構成重佈線層204。
如其他實施例所述及第43圖所示，利用走線上方接墊(BOT)技術，將積體電路216a及216b耦接至接線212的走線214。在積體電路216a及216b上及重佈線層204上形成一成型材料224。基底268包括積體電路216a獨自封裝的一第一區272a以及積體電路216a及216b一同封裝的一第二區272b(可選擇性一同封裝其他積體電路(未繪示))。
如第44圖所示，利用一黏著層202將一第二承載晶圓200接合或貼附至成型材料224上。如第44圖所示，對上述結構進行研磨或CMP製程260，以去除一部分的基底268或第一承載晶圓，並露出接線212的上表面274。
如第45圖所示，利用一蝕刻製程276去除基底268的剩餘部份，以露出重佈線層204的絕緣材料層210。蝕刻製程276可包括乾蝕刻或濕蝕刻矽製程。部分的接線212突出於絕緣材料層210的上表面。因此，在本封裝製程中具有第一承載晶圓的基底268自該結構中移除。
如第46圖所示，金屬凸塊228形成於接線212的露出部分。金屬凸塊128包括焊球且可透過焊球熔滴(solder ball drop)製程而形成。如第47圖所示，移開或去除承載晶圓200及黏著層202，且在切割線232處進行切割，以在單體化製程之後形成封裝的半導體裝置280a，其包括位於第一區272a的單一積體電路216a，且形成封裝的半導體裝置280b，其包括位於第二區272b的多重的積體電路216a及216b。也可在金屬凸塊228之間的絕緣材料層210上形成一非必要的成型材料層(未繪示)，如先前的實施例所述。此非必要的成型材料層(例如，先前實施例所示的成型材料層130)可形成於以下的實施例，但未繪示於圖式中。
因此，根據第40至47圖的實施例，包括重佈線層204及成型材料層224的封裝的半導體裝置280a及280b係使用二個承載晶圓268及200來製做。在本實施例中，封裝的半導體裝置280a及280b的金屬凸塊228包括焊球。
第48至52圖係繪示出關於第40至47圖的實施例的另一實施例的剖面示意圖，其中使用錫膏(solder paste)來形成封裝體的金屬凸塊228。如第48圖所示，在形成如第42圖所示的重佈線層204的接線212之後，於接線212及絕緣材料層210的露出部上形成一錫膏282。錫膏282黏附於接線212，而未黏附於絕緣材料層210。如第49圖所示，對焊膏282進行一回流(reflow)製程284，以在回流製程284之後，於接線212圖案內的錫膏282上形成凹面區286。
如第50圖所示，積體電路216a及216b耦接至接線212的走線214，且如第51圖所示，在積體電路216a及216b上及重佈線層204上形成一成型材料層224。亦如第51圖所示，利用一黏著層202，將第二承載晶圓200接合或貼附於成型材料層224。接著進行第44及45圖所述及所示的封裝製程，接著對上述結構進行一蝕刻製程，以從絕緣材料層210上的錫膏282的表面288上去除接線212，如第52圖所示。如第52圖所示，去除第二承載晶圓200，並切割上述結構，以留下一封裝的半導體裝置(未繪示)，其包括位於第一區272a的單一積體電路216a，且留下一封裝的半導體裝置280c，其包括從第二區272b切割出來的多重的積體電路216a及216b。
在本實施例中，不同於先前實施例中形成焊球來製做金屬凸塊228，而是金屬凸塊228包括錫膏282，其形成於重佈線層204的接線214內。本實施例的優點在於不需要形成焊球的製程步驟。包括錫膏282的金屬凸塊228具有接合墊，用於將封裝的半導體裝置280c耦接至一印刷電路板(PCB)、另一積體電路、另一封裝體或其他裝置。也可在金屬凸塊228之間的絕緣材料層210上形成一非必要的成型材料層(未繪示)，如先前的實施例所述。
第53至57圖係繪示出一實施例之剖面示意圖，其中多重的積體電路以垂直式或垂直及橫向式封裝在一起。封裝製程的初始步驟相同於第40至43圖所述的步驟。接著，在本實施例中，如第53圖所示，蝕刻成型材料層(其包括第一成型材料層224a)，以在第一成型材料層224a內形成接觸窗的圖案290。如第54圖所示，於接觸窗的圖案290內填入一導電材料，以在第一成型材料層224a內形成接觸窗292。在本實施例中，接觸窗292係作為z軸連接器234。如第55圖所示，在第一成型材料層224a及接觸窗292上形成包括x-y連接器的接線236，且將積體電路216a及216b耦接至接線236。如第56圖所示，於積體電路216a及216b、接線236及第一成型材料層224a上形成一第二成型材料層224b，且利用黏著層202，將第二承載晶圓200耦接至第二成型材料層224b。如第57圖所示，進行第44至47圖所述的封裝製程，且在切割線232處進行切割，以在第一區272a形成封裝的半導體裝置280d，且在第二區272b形成封裝的半導體裝置280e。
第58圖係繪示出關於第53至57圖的實施例的另一實施例之剖面示意圖，其中封裝體的金屬凸塊由錫膏282所構成，如第52圖的實施例所述。進行第48至52圖與第53至57圖的封裝製程，以達成第58圖所示的封裝的半導體裝置280g及208f。
第59至65圖係繪示出一實施例之剖面示意圖，其中包括基底通孔電極(TSV)的一積體電路216a與至少一其他積體電路進行垂直式封裝。第59及60圖係繪示出包括基底通孔電極的積體電路216a的部分製程。提供一基底248，且圖案化基底248而具有用於基底通孔電極250的圖案。上述圖案上可先形成一絕緣襯層，再填入一導電材料，以形成基底通孔電極250。基底通孔電極局部延伸通過基底248。在後段(back-end-od-line,REOL)製程中，於絕緣材料層249及基底通孔電極250上形成金屬化層252，且於積體電路216a的接觸墊222a上形成金屬柱體218a及焊料凸塊220a，如圖所示。於切割線296處切割積體電路216a。
接著進行如第40至42圖所述之封裝製程，且將包括基底通孔電極的積體電路216a貼附於接線212，如第61圖所示。第61圖所示，於積體電路216a上形成一第一成型材料層224a，且利用CMP製程260去除積體電路216a的局部基底248，以露出積體電路216a的基底通孔電極的表面262。進行相似於第34至36圖中所述的製程步驟：如第62圖所示，形成極圖案化一絕緣材料層264；如第63圖所示，形成接線236(接線236及絕緣材料層264構成一第二重佈線層204b)；以及如第64圖所示，將積體電路216b及216c貼附至接線236。接著進行如第56至57圖中所述的製程步驟，以達成如第65圖所示的封裝的半導體裝置280h及280i。
第66圖係繪示出關於第59至65圖的實施例的另一實施例的剖面示意圖，其中封裝體的金屬凸塊282由錫膏所構成，如第58圖所述，而形成如圖所示的封裝的半導體裝置280j及280k。
此處所述的z軸連接器134可包括金屬間柱(stud)凸塊堆疊，如第67圖所繪示的剖面示意圖。具有z軸連接器134的本文實施例中，z軸連接器134可包括金屬間柱凸塊堆疊，而非先前所述的其他z軸連接器類型。每一金屬間柱凸塊堆疊包括一金屬間柱198，金屬間柱198具有複數個焊料凸塊199形成於其上且沿著金屬間柱198的高度垂直設置。二個或二個以上焊料凸塊199可形成於美一金屬間柱198上。金屬間柱198可包括Au、Cu、其他金屬或其組合，且凸塊199可包括焊料、其他材料或其組合。
本文實施例的優點在於提供半導體裝置新的封裝方法及結構。在一些實施例中，積體電路116、116a、116b、216a或216b為分開封裝。在其他實施例中，多重的積體電路116、116a、116b、116c、216a、216b或216c封裝於單一封裝體內，且可於單一材料層內垂直堆疊或橫向排列。積體電路可具有基底通孔電極，以提供垂直連接器，或者垂直連接器(z軸連接器)可使用打線墊、焊球、金屬柱體或金屬間柱凸塊堆疊來製做。重佈線層104、104a、104b、204a及204b可使用承載晶圓或基底來製做。一承載晶圓或二個承載晶圓可用於形成所述新的封裝體。新的封裝方法及結構易實施於封裝及製程步驟中。
實施例中新的封裝方法及結構的優點在於不需要一基底，其省下時間、支出、空間及重量。由於沒有熱膨脹係數(CTE)不匹配的考量(由於不具有基底)，封裝體的可靠度高，且其製造成本低而良率高。積體電路利用BOT技術進行貼附或接合，因而大幅縮減成本。
此處所述的實施例係利用晶片重佈及成型技術，以有效重新安裝一使用承載晶圓100、200及268的新晶圓，放大了晶片區域以供重佈線層佈局之用。透過實施基底通孔電極的晶片重佈及在成型材料層內形成接觸窗，可完成三維系統級封裝(3D SiP)。上述實施例結合了三維基底通孔電極(3D TSV)及扇出式(fan-out)晶圓級製程(wafer level processing,WLP)，以獲得高輸出/輸入扇出。晶片重佈方法得以簡化，且可達成高度的晶粒偏移控制。在一些實施例中，裸矽晶圓係用以作為承載晶圓，且也作為犧牲工具，以形成重佈線層及三維結構的球接墊。在一些實施例中(例如，第46、47、57及65圖所示的實施例)，三維結構的球接墊改善了接點可靠度且容易進行大型封裝體的封裝。此處所述的新封裝結構優點在於在一些實施例中，使用了晶圓級製程。
依據此處所述的實施例，可達成具有較小形狀因素的系統級封裝(SiP)結構。更多成熟的封裝體類型可貼附於封裝體，例如覆晶球柵陣列(flip chip ball grid array,FCBGA)、打線球柵陣列(wire bond BGA,FCBGA)、晶圓級晶片尺寸封裝(wafer level chip scale package,WLCSP)或被動(passive)裝置。透過本文所述的實施例可達成三維晶圓級接合(wafer level bonding,WLB)封裝，例如3D eWLB及3D-TSV eWLB封裝、SiP、3D-SiP、PoP結構及扇出式WLP。
本文實施例包括半導體裝置或此處所述積體電路116、116a、116b、116c、116d的封裝方法，也包括封裝的半導體裝置140、140a、140b、140c、140d、140e、140f、140g、140h、140i、140j、140k、140m、280、280a、280b、280c、280d、280e、280f、280g、280h、280i、280j及280k，其使用此處所述的方法及材料進行封裝。上述實施例也包括用於此處所述的半導體裝置的封裝體。
在一實施例中，一種封裝的半導體裝置包括一重佈線層，其具有一第一表面及與第一表面相對的一第二表面。至少一積體電路耦接至重佈線層的第一表面，且複數個金屬凸塊耦接至重佈線層的第二表面。一成型材料設置於積體電路及重佈線層的第一表面上。
在另一實施例中，一種用於半導體裝置的封裝體包括一重佈線層，其包括至少一內層介電層及至少一金屬化層。金屬化層形成於內層介電層內。複數個走線設置於重佈線層的一第一表面上，且複數個接合墊設置於重佈線層的一第二表面上，其中第二表面相對於第一表面。接合墊透過位於金屬化層內的接線而分別電性耦接至走線。
又一實施例中，一種半導體裝置之封裝方法包括提供一承載晶圓及在承載晶圓上形成一重佈線層。重佈線層包括至少一內層介電層及至少一金屬化層。金屬化層形成於內層介電層內，且重佈線層具有一第一表面及與第一表面相對的一第二表面。此方法包括將至少一積體電路耦接至重佈線層的第一表面，且在積體電路及重佈線層的第一表面上形成一成型材料。在重佈線層的第二表面上形成複數個金屬凸塊，且去除承載晶圓。
雖然本發明實施例及其優點已詳細揭露如上，然而可以理解的是其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
100．．．承載晶圓
102、202．．．黏著層
104、204．．．重佈線層
104a、204a．．．第一重佈線層
104b、204b．．．第二重佈線層
106．．．第一表面
108．．．第二表面
110a、110b、110c．．．內層介電層
112、136、212、236．．．接線
112a．．．第一接線
112b．．．第二接線
114、138、214．．．走線
116、116a、116b、116c、216a、216b、216c．．．半導體裝置/積體電路
118、118a、218a、218b．．．金屬柱體
120、120a、120b、120c、220a、220b、199．．．焊料凸塊
122、122a、222a．．．接觸墊
124、130．．．成型材料
124a、224a．．．第一成型材料
124b、224b．．．第二成型材料
126．．．露出部分
128、228．．．金屬凸塊
132、232、296．．．切割線
134、234．．．z軸連接器
140、140a、140b、140c、140d、140e、140f、140g、140h、140i、140j、140k、140m、280a、280b、280c、280d、280e、280f、280g、280h、280i、280j、280k．．．封裝的半導體裝置/封裝的積體電路
142、149、158、164、210、249、264．．．絕緣材料層
146．．．露出端
148、248、268．．．基底
150、250．．．基底通孔電極
152、252．．．金屬化層
154．．．導線及接觸窗
160、260．．．化學機械研磨製程
162、274．．．上表面
166．．．開口
198．．．金屬間柱
200．．．第二承載晶圓
272a．．．第一區
272b‧‧‧第二區
276‧‧‧蝕刻製程
282‧‧‧錫膏/金屬凸塊
284‧‧‧回流製程
286‧‧‧凹面區
262、288‧‧‧表面
290‧‧‧圖案
292‧‧‧接觸窗
第1至7圖係繪示出根據本發明實施例之半導體裝置之封裝方法剖面示意圖，其中一單積體電路使用重佈線層及成型材料來進行封裝；
第8至9圖係繪示出根據本發明另一實施例之二或多個積體電路之橫向封裝方法剖面示意圖；
第10至20圖係繪示出一實施例之剖面示意圖，其中形成具有打線墊的z軸連接器，以將二或多個積體電路進行垂直式封裝，且其中具有接線的x-y連接器形成於一金屬化層內；
第21至22圖係繪示出一實施例之剖面示意圖，其包括具有打線墊的z軸連接器，且其中一第二重佈線層係形成於z軸連接器上；
第23圖係繪示出一實施例之剖面示意圖，其包括具有打線墊的z軸連接器，且其中未形成x-y連接器或第二重佈線層；
第24及25圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括焊球，且其中x-y連接器製做於金屬化層內；
第26圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括焊球，且一第二重佈線層形成於z軸連接器上；
第27圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括焊球，且其中未形成x-y連接器或第二重佈線層；
第28及29圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括金屬柱體，且其中x-y連接器製做於金屬化層內；
第30圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括金屬柱體，且一第二重佈線層形成於z軸連接器上；
第31圖係繪示出一實施例之剖面示意圖，其中z軸連接器包括金屬柱體，且其中未形成x-y連接器或第二重佈線層；
第32至38圖係繪示出一實施例之剖面示意圖，其中包括一基底通孔電極的積體電路係與至少一其他積體電路進行垂直式封裝；
第39圖係繪示出一實施例之剖面示意圖，其中一第二重佈線層形成於包括基底通孔電極的積體電路上；
第40至47圖係繪示出根據本發明另一實施例之封裝一積體電路的方法或橫向封裝二個以上積體電路的方法剖面示意圖，其中封裝體的連接包括具有焊球的金屬凸塊；
第48至52圖係繪示出關於第40至47圖的實施例的另一實施例的剖面示意圖，其中使用錫膏來形成封裝體的金屬凸塊；
第53至57圖係繪示出一實施例之剖面示意圖，其中多重的積體電路以垂直式或垂直及橫向式封裝在一起；
第58圖係繪示出關於第53至57圖的實施例的另一實施例之剖面示意圖，其中封裝體的金屬凸塊由錫膏所構成；
第59至65圖係繪示出一實施例之剖面示意圖，其中包括基底通孔電極的一積體電路與至少一其他積體電路進行垂直式封裝；
第66圖係繪示出關於第59至65圖的實施例的另一實施例的剖面示意圖，其中封裝體的金屬凸塊由錫膏所構成；
第67圖係繪示出一實施例之剖面示意圖，其中z軸連接器可包括金屬間柱凸塊堆疊，其可實施於此處所述的實施例中。
104．．．重佈線層
106．．．第一表面
108．．．第二表面
110a、110b、110c．．．內層介電層
112．．．接線
114．．．走線
116．．．半導體裝置/積體電路
118．．．金屬柱體
120．．．焊料凸塊
122．．．接觸墊
124、130．．．成型材料
128．．．金屬凸塊
140．．．封裝的半導體裝置/封裝的積體電路

Claims (10)

  1. 一種封裝的半導體裝置，包括：一重佈線層，該重佈線層包括一第一表面及與該第一表面相對的一第二表面，其中該重佈線層更包括設置於複數個內層介電層中的複數個金屬化層；至少一積體電路，耦接至該重佈線層的該第一表面；複數個金屬凸塊，耦接至該重佈線層的該第二表面之一第一區域，且該重佈線層的該第二表面具有該等內層介電層之最上層之頂部表面所形成之暴露的一第二區域；以及一成型材料，設置於該積體電路及該重佈線層的該第一表面上。
  2. 如申請專利範圍第1項所述之封裝的半導體裝置，其中該積體電路包括一基底，其內具有複數個基底通孔電極，其中該積體電路包括至少一第一積體電路及至少一第二積體電路設置於該第一積體電路的至少一部分上，且部分的該第二積體電路電性耦接至部份的該第一積體電路或該重佈線層，或電性耦接至該第一積體電路與該重佈線層兩者。
  3. 如申請專利範圍第1項所述之封裝的半導體裝置，其中該積體電路包括至少一第一積體電路及至少一第二積體電路，設置於該重佈線層上，該第二積體電路透過複數個連接器而電性耦接至該重佈線層，該等連接器設置於該重佈線層與該第二積體電路之間的該成型材料內。
  4. 一種用於半導體裝置的封裝體，包括：一重佈線層，包括至少一內層介電層及至少一金屬化層，該金屬化層形成於該內層介電層內，該重佈線層具有一第一表面及與該第一表面相對的一第二表面，其中複數個走線設置於該重佈線層的該第一表面上，且其中複數個接合墊設置於該重佈線層中，且該等接合墊的每一者皆具有一暴露的表面在該重佈線層的該第二表面上，並且為該重佈線層的該第二表面之水平面的一部分，該等接合墊透過位於該金屬化層內的接線而分別電性耦接至該等走線。
  5. 如申請專利範圍第4項所述之用於半導體裝置的封裝體，更包括：複數個焊料凸塊，分別耦接至該等接合墊；以及一成型材料，設置於該等焊料凸塊之間的該重佈線層的該第二表面上。
  6. 如申請專利範圍第4項所述之用於半導體裝置的封裝體，其中該等走線沿著一x-y軸設置，該重佈線層更包括複數個z軸連接器，其沿著一z軸設置，該z軸大體上垂直於該x-y軸，且其中該等z軸連接器包括耦接至該封裝體的一積體電路的打線墊、金屬柱體、焊球、金屬間柱凸塊堆疊或基底通孔電極。
  7. 一種半導體裝置之封裝方法，包括：提供一承載晶圓；在該承載晶圓上形成一重佈線層，該重佈線層包括至少一內層介電層及至少一金屬化層，該金屬化層形成 於該內層介電層內，該重佈線層具有一第一表面及與該第一表面相對的一第二表面；將至少一積體電路耦接至該重佈線層的該第一表面；在該積體電路及該重佈線層的該第一表面上形成一成型材料；在該重佈線層的該第二表面上之一第一區域形成複數個金屬凸塊，其中該重佈線層的該第二表面具有該內層介電層之頂部表面所形成之暴露的一第二區域；以及去除該承載晶圓。
  8. 如申請專利範圍第7項所述之半導體裝置之封裝方法，其中耦接該積體電路的步驟包括耦接至少一第一積體電路，且形成該成型材料的步驟包括形成一第一成型材料，該封裝方法更包括：在該重佈線層上形成複數個z軸連接器，該等z軸連接器在形成該成型材料之前，耦接至該金屬化層內的接線；在該成型材料及該等z軸連接器上形成接線，該接線包括複數個x-y連接器；將至少一第二積體電路耦接至該接線；以及在該第二積體電路、該接線及該第一成型材料上形成一第二成型材料。
  9. 如申請專利範圍第7項所述之半導體裝置之封裝方法，其中形成該重佈線層的步驟包括形成一第一重佈線層，該封裝方法更包括：在該第一重佈線層上形成複數個z軸連接器，該等z 軸連接器在形成該成型材料之前，耦接至第一重佈線層的該金屬化層內的接線；以及在該等z軸連接器上形成一第二重佈線層，其中部份的該二重佈線層提供該半導體裝置電性接觸之用。
  10. 如申請專利範圍第7項所述之半導體裝置之封裝方法，更包括：在該重佈線層上形成複數個z軸連接器，該等z軸連接器在形成該成型材料之前，耦接至該重佈線層的該金屬化層內的接線，其中該等z軸連接器提供該半導體裝置電性接觸之用。
TW101103214A 2011-09-09 2012-02-01 封裝的半導體裝置、用於半導體裝置的封裝體及半導體裝置封裝方法 TWI467668B (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10304716B1 (en) 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
TWI670777B (zh) * 2015-11-10 2019-09-01 台灣積體電路製造股份有限公司 多堆疊疊層封裝結構及其製造方法

Families Citing this family (364)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058726B1 (en) 2008-05-07 2011-11-15 Amkor Technology, Inc. Semiconductor device having redistribution layer
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8832283B1 (en) 2010-09-16 2014-09-09 Google Inc. Content provided DNS resolution validation and use
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US20130075894A1 (en) * 2011-09-23 2013-03-28 Texas Instruments Incorporated Integrated circuit and method of making
US8552557B1 (en) * 2011-12-15 2013-10-08 Amkor Technology, Inc. Electronic component package fabrication method and structure
US9219029B2 (en) 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8664090B1 (en) 2012-04-16 2014-03-04 Amkor Technology, Inc. Electronic component package fabrication method
KR20130140321A (ko) * 2012-06-14 2013-12-24 에스케이하이닉스 주식회사 임베디드 패키지 및 제조 방법
US8872326B2 (en) 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9245862B1 (en) 2013-02-12 2016-01-26 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8890284B2 (en) * 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9362236B2 (en) 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
CN104051383B (zh) * 2013-03-15 2018-02-27 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9142530B2 (en) * 2013-03-21 2015-09-22 Stats Chippac Ltd. Coreless integrated circuit packaging system and method of manufacture thereof
KR101473093B1 (ko) * 2013-03-22 2014-12-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101494814B1 (ko) * 2013-04-15 2015-02-23 앰코 테크놀로지 코리아 주식회사 팬 아웃 반도체 패키지 및 그 제조 방법
US20150001732A1 (en) * 2013-06-27 2015-01-01 Debendra Mallik Silicon space transformer for ic packaging
KR101488608B1 (ko) 2013-07-19 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
TWI527173B (zh) 2013-10-01 2016-03-21 旭德科技股份有限公司 封裝載板
US9466581B2 (en) 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9412719B2 (en) 2013-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10056353B2 (en) 2013-12-19 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US9553059B2 (en) 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
KR101601388B1 (ko) * 2014-01-13 2016-03-08 하나 마이크론(주) 반도체 패키지 및 그 제조 방법
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9406642B1 (en) * 2014-03-11 2016-08-02 Stats Chippac Ltd. Integrated circuit packaging system with insulated trace and method of manufacture thereof
US9418877B2 (en) * 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US9466560B2 (en) 2014-05-28 2016-10-11 United Microelectronics Corp. Interposer fabricating process and wafer packaging structure
US9455158B2 (en) 2014-05-30 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
TWI655727B (zh) 2014-06-17 2019-04-01 恆勁科技股份有限公司 封裝基板及包含該封裝基板的覆晶封裝電路
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9425178B2 (en) * 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9449914B2 (en) * 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9613910B2 (en) 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9892952B2 (en) 2014-07-25 2018-02-13 Semiconductor Components Industries, Llc Wafer level flat no-lead semiconductor packages and methods of manufacture
CN105489580B (zh) 2014-09-17 2018-10-26 日月光半导体制造股份有限公司 半导体衬底及半导体封装结构
US10468381B2 (en) * 2014-09-29 2019-11-05 Apple Inc. Wafer level integration of passive devices
US9502322B2 (en) * 2014-10-24 2016-11-22 Dyi-chung Hu Molding compound supported RDL for IC package
US9679862B2 (en) * 2014-11-28 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having conductive bumps of varying heights
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US9972602B2 (en) * 2015-02-23 2018-05-15 Marvell World Trade Ltd. Method and apparatus for interconnecting stacked dies using metal posts
US10497660B2 (en) * 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
CN104851816A (zh) * 2015-04-13 2015-08-19 华进半导体封装先导技术研发中心有限公司 一种多芯片高密度封装方法
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9659805B2 (en) 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US9484227B1 (en) 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US10276541B2 (en) * 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US10170444B2 (en) * 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US9793231B2 (en) 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
KR102398663B1 (ko) * 2015-07-09 2022-05-16 삼성전자주식회사 칩 패드, 재배선 테스트 패드 및 재배선 접속 패드를 포함하는 반도체 칩
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9373605B1 (en) 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9564345B1 (en) 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US10784206B2 (en) 2015-09-21 2020-09-22 Mediatek Inc. Semiconductor package
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US9761534B2 (en) * 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9929112B2 (en) 2015-09-25 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9704825B2 (en) * 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US10068844B2 (en) 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US10720788B2 (en) 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
DE102016115788A1 (de) 2015-10-20 2017-04-20 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleitervorrichtung und Verfahren
US10304700B2 (en) 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
CN105225965B (zh) * 2015-11-03 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型封装结构及其制作方法
US9953892B2 (en) 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9953963B2 (en) 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9786614B2 (en) 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9793245B2 (en) 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9735118B2 (en) 2015-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas and waveguides in InFO structures
KR102109569B1 (ko) * 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10074472B2 (en) 2015-12-15 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. InFO coil on metal plate with slot
CN108352379B (zh) * 2015-12-21 2022-05-17 英特尔公司 系统级封装装置以及用于形成系统级封装装置的方法
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US10050013B2 (en) 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US9984998B2 (en) 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US20170213801A1 (en) * 2016-01-22 2017-07-27 Micron Technology, Inc. Method for manufacturing a package-on-package assembly
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9768303B2 (en) 2016-01-27 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for FinFET device
WO2017131683A1 (en) 2016-01-28 2017-08-03 Intel IP Corporation Integrated circuit packages
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9761522B2 (en) 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
DE102016118802B4 (de) 2016-01-29 2022-12-08 Taiwan Semiconductor Manufacturing Co. Ltd. Drahtloses Ladepaket mit in Spulenmitte integriertem Chip und Herstellungsverfahren dafür
US9904776B2 (en) 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10797038B2 (en) 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US9754805B1 (en) 2016-02-25 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging method and structure
US9842815B2 (en) 2016-02-26 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9847320B2 (en) 2016-03-09 2017-12-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the same
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
WO2017160231A1 (en) * 2016-03-14 2017-09-21 Agency For Science, Technology And Research Semiconductor package and method of forming the same
US9935009B2 (en) * 2016-03-30 2018-04-03 International Business Machines Corporation IR assisted fan-out wafer level packaging using silicon handler
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US9859229B2 (en) 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9935024B2 (en) 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US9947552B2 (en) 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US9997464B2 (en) 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9922895B2 (en) 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US9754914B1 (en) * 2016-05-10 2017-09-05 Rosemount Aerospace Inc. Method to provide die attach stress relief using gold stud bumps
US9806059B1 (en) 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10797025B2 (en) 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US9870997B2 (en) 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US9852957B2 (en) 2016-05-27 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Testing, manufacturing, and packaging methods for semiconductor devices
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
US9941216B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9941248B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures, pop devices and methods of forming the same
US9985006B2 (en) * 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9812381B1 (en) 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US11056436B2 (en) 2016-06-07 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out structure with rugged interconnect
US10354114B2 (en) 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US9812426B1 (en) 2016-06-29 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, semiconductor device, and method of fabricating the same
US9653391B1 (en) 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9793230B1 (en) 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10163800B2 (en) 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9824902B1 (en) 2016-07-12 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9661794B1 (en) 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9799615B1 (en) 2016-07-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures having height-adjusted molding members and methods of forming the same
US9691708B1 (en) 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10062654B2 (en) 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10276506B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US9984960B2 (en) 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10276542B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10541226B2 (en) 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10163860B2 (en) 2016-07-29 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10134708B2 (en) 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10297551B2 (en) 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10658334B2 (en) 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
KR101982044B1 (ko) 2016-08-31 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10128182B2 (en) 2016-09-14 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9922896B1 (en) 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9911672B1 (en) 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US9837359B1 (en) 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10515899B2 (en) 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US20180102298A1 (en) * 2016-10-06 2018-04-12 Mediatek Inc. Semiconductor device
US10157846B2 (en) 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US10163801B2 (en) 2016-10-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10692813B2 (en) 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US9837366B1 (en) 2016-11-28 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10128193B2 (en) 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10037963B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10304793B2 (en) 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163824B2 (en) 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
CN106783649A (zh) * 2017-01-11 2017-05-31 中芯长电半导体（江阴）有限公司 一种集成供电系统封装件的封装方法
CN106531710A (zh) * 2017-01-11 2017-03-22 中芯长电半导体（江阴）有限公司 一种集成供电系统的封装件及封装方法
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US9972581B1 (en) 2017-02-07 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Routing design of dummy metal cap and redistribution line
CN106684056A (zh) * 2017-03-22 2017-05-17 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装结构及其制备方法
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
DE102017124104A1 (de) 2017-04-07 2018-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Packages mit si-substrat-freiem interposer und verfahren zum bilden derselben
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
TWI618214B (zh) * 2017-04-13 2018-03-11 力成科技股份有限公司 具有重佈線路層的晶片結構
CN107180766A (zh) * 2017-05-11 2017-09-19 王家恒 扇出型封装结构及其制作方法、终端设备
CN106981468A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
CN106981467A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
TWI653728B (zh) * 2017-05-26 2019-03-11 南茂科技股份有限公司 指紋辨識晶片的封裝結構及其製造方法
DE102017012352B4 (de) 2017-06-30 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren mit einem Trennfilm als Isolierfilm im Gehäuse und Gehäuse
CN107146778A (zh) * 2017-06-30 2017-09-08 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
US10269589B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
CN107195551A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 扇出型叠层封装结构及其制备方法
CN107195625A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 双面塑封扇出型系统级叠层封装结构及其制备方法
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10475747B2 (en) * 2017-08-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10629540B2 (en) 2017-09-27 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
CN107785339A (zh) * 2017-10-13 2018-03-09 中芯长电半导体（江阴）有限公司 3d芯片封装结构及其制备方法
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US10283377B1 (en) * 2017-11-07 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US10553533B2 (en) * 2017-11-08 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US20190148325A1 (en) * 2017-11-10 2019-05-16 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing the same
US11177201B2 (en) 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US10784203B2 (en) 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
DE102018102086A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-packages und verfahren zu deren herstellung
US10529650B2 (en) 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10867954B2 (en) * 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10665522B2 (en) * 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
CN108109928A (zh) * 2017-12-29 2018-06-01 中芯长电半导体（江阴）有限公司 半导体芯片的封装结构及封装方法
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11488881B2 (en) 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11062915B2 (en) 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10665559B2 (en) * 2018-04-11 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Device, semiconductor package and method of manufacturing semiconductor package
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10631392B2 (en) 2018-04-30 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. EUV collector contamination prevention
US10790254B2 (en) * 2018-05-09 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure
CN110504172A (zh) * 2018-05-16 2019-11-26 中芯长电半导体（江阴）有限公司 垂直打线结构、堆叠芯片封装结构及方法
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
CN208638447U (zh) * 2018-06-29 2019-03-22 宁波舜宇光电信息有限公司 线路板组件、感光组件及摄像模组
US11004803B2 (en) 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US10573572B2 (en) * 2018-07-19 2020-02-25 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing a semiconductor package structure
US20200036081A1 (en) * 2018-07-30 2020-01-30 Innolux Corporation Package structure and antenna device using the same
US11289373B2 (en) * 2018-07-31 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11056459B2 (en) * 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10658348B2 (en) 2018-09-27 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having a plurality of first and second conductive strips
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
DE102019101999B4 (de) 2018-09-28 2021-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung mit mehreren polaritätsgruppen
US10861841B2 (en) 2018-09-28 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple polarity groups
US10665520B2 (en) 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11011451B2 (en) 2018-12-05 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11538735B2 (en) 2018-12-26 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit packages with mechanical braces
US10978382B2 (en) 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11107791B2 (en) * 2019-03-14 2021-08-31 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11145560B2 (en) * 2019-04-30 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacturing
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11380620B2 (en) 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11004758B2 (en) 2019-06-17 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11133258B2 (en) 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11387191B2 (en) 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10879114B1 (en) 2019-08-23 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive fill
SG10201908828WA (en) * 2019-09-23 2021-04-29 Apple Inc Embedded Packaging Concepts for Integration of ASICs and Optical Components
US11587905B2 (en) 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
TWI759844B (zh) * 2019-10-09 2022-04-01 財團法人工業技術研究院 多晶片封裝件及其製造方法
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11410968B2 (en) * 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
KR20210047607A (ko) 2019-10-22 2021-04-30 삼성전자주식회사 반도체 패키지
CN112786540A (zh) * 2019-11-06 2021-05-11 富泰华工业（深圳）有限公司 扇出型封装结构及其制作方法
TWI713165B (zh) * 2019-11-25 2020-12-11 南茂科技股份有限公司 晶片封裝結構及其製造方法
US11227837B2 (en) 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11227795B2 (en) 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11594571B2 (en) * 2020-02-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked image sensor device and method of forming same
DE102020116340A1 (de) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Gestapelter bildsensorvorrichtung und deren herstellungsverfahren
TWI720847B (zh) * 2020-03-17 2021-03-01 欣興電子股份有限公司 晶片封裝結構及其製作方法
US11393746B2 (en) 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11948930B2 (en) 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11552053B2 (en) 2020-06-25 2023-01-10 Apple Inc. Miniaturization of optical sensor modules through wirebonded ball stacks
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US12094828B2 (en) 2020-07-17 2024-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Eccentric via structures for stress reduction
US11532524B2 (en) 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11652037B2 (en) 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
KR20220026809A (ko) 2020-08-26 2022-03-07 삼성전자주식회사 반도체 패키지
KR20220034596A (ko) 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지
US11454888B2 (en) 2020-09-15 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11756871B2 (en) * 2020-09-15 2023-09-12 Sj Semiconductor (Jiangyin) Corporation Fan-out packaging structure and method
US11868047B2 (en) 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US12119235B2 (en) 2020-11-04 2024-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of manufacture of semiconductor devices having redistribution layer using dielectric material having photoactive component
KR20220067630A (ko) 2020-11-17 2022-05-25 삼성전자주식회사 반도체 패키지
US20220199535A1 (en) * 2020-12-18 2022-06-23 Intel Corporation Microelectronic structures including bridges
CN112928028A (zh) * 2021-01-22 2021-06-08 广东佛智芯微电子技术研究有限公司 一种具有嵌入式线路的板级芯片封装方法及其封装结构
US11646255B2 (en) * 2021-03-18 2023-05-09 Taiwan Semiconductor Manufacturing Company Limited Chip package structure including a silicon substrate interposer and methods for forming the same
CN113629016B (zh) * 2021-08-06 2024-07-02 深圳真茂佳半导体有限公司 一种氮化镓hemt芯片整合封装结构及其制造方法
US12015003B2 (en) * 2021-09-29 2024-06-18 International Business Machines Corporation High density interconnection and wiring layers, package structures, and integration methods
US20230106976A1 (en) * 2021-09-29 2023-04-06 Texas Instruments Incorporated Semiconductor die with solder restraining wall
CN115332088A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 一种基于中介层的封装及制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080142976A1 (en) * 2006-07-24 2008-06-19 Ibiden Co., Ltd. Interposer and electronic device using the same
US20110062592A1 (en) * 2009-09-11 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination Resistance of Stacked Dies in Die Saw
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3882539B2 (ja) 2000-07-18 2007-02-21 ソニー株式会社 半導体発光素子およびその製造方法、並びに画像表示装置
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US7164197B2 (en) * 2003-06-19 2007-01-16 3M Innovative Properties Company Dielectric composite material
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
TWI221336B (en) 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US20050205981A1 (en) 2004-03-18 2005-09-22 Kabushiki Kaisha Toshiba Stacked electronic part
TWI236721B (en) 2004-06-29 2005-07-21 Advanced Semiconductor Eng Leadframe for leadless flip-chip package and method for manufacturing the same
GB2418532A (en) 2004-09-28 2006-03-29 Arima Optoelectronic Textured light emitting diode structure with enhanced fill factor
JPWO2006035528A1 (ja) * 2004-09-29 2008-05-15 株式会社村田製作所 スタックモジュール及びその製造方法
JP2009054970A (ja) 2007-08-29 2009-03-12 Shinko Electric Ind Co Ltd 半導体装置
US7659609B2 (en) * 2007-08-31 2010-02-09 Stats Chippac Ltd. Integrated circuit package-in-package system with carrier interposer
US7863100B2 (en) * 2009-03-20 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with layered packaging and method of manufacture thereof
US9922955B2 (en) 2010-03-04 2018-03-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US8357563B2 (en) 2010-08-10 2013-01-22 Spansion Llc Stitch bump stacking design for overall package size reduction for multiple stack
US8508045B2 (en) * 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8587120B2 (en) 2011-06-23 2013-11-19 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080142976A1 (en) * 2006-07-24 2008-06-19 Ibiden Co., Ltd. Interposer and electronic device using the same
US20110062592A1 (en) * 2009-09-11 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination Resistance of Stacked Dies in Die Saw
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI670777B (zh) * 2015-11-10 2019-09-01 台灣積體電路製造股份有限公司 多堆疊疊層封裝結構及其製造方法
US10490540B2 (en) 2015-11-10 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10784248B2 (en) 2015-11-10 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US11462531B2 (en) 2015-11-10 2022-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US11462530B2 (en) 2015-11-10 2022-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10304716B1 (en) 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof

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