CN103000593A - 用于半导体器件的封装方法和结构 - Google Patents

用于半导体器件的封装方法和结构 Download PDF

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Publication number
CN103000593A
CN103000593A CN2012101900041A CN201210190004A CN103000593A CN 103000593 A CN103000593 A CN 103000593A CN 2012101900041 A CN2012101900041 A CN 2012101900041A CN 201210190004 A CN201210190004 A CN 201210190004A CN 103000593 A CN103000593 A CN 103000593A
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rdl
integrated circuit
distribution
semiconductor device
moulding compound
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CN103000593B (zh
Inventor
林志伟
郑明达
吕文雄
林修任
张博平
刘重希
李明机
余振华
陈孟泽
林俊成
蔡钰芃
黄贵伟
林威宏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了用于半导体器件的封装方法和结构。在一个实施例中，封装的半导体器件包括再分布层(RDL)，其具有第一表面和与第一表面相对的第二表面。至少一个集成电路连接至RDL的第一表面，以及多个金属凸块连接至RDL的第二表面。模塑料被设置在至少一个集成电路和RDL的第一表面的上方。

Description

用于半导体器件的封装方法和结构
相关申请的交叉参考
本申请涉及以下未决且属于同一受让人的专利申请：于2011年7月7日提交的标题为“Connecting Function Chips to a Package to formPackage-on-Package”的第13/178,161号，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体领域，更具体地，涉及用于半导体器件的封装方法和结构。
背景技术
作为实例，在诸如个人计算机、蜂窝电话、数码相机和其他电子设备的各种电子应用中使用半导体器件。半导体工业通过连续减小最小部件的尺寸来连续改进各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这使得更多的部件被集成到给定面积中。在一些应用中，这些更小的电子部件还要求更小的封装，其与过去的封装相比利用更小的面积。
用于半导体的一些较小类型的封装包括方扁形封装(QFP)、插针网格阵列(PGA)、球栅阵列(BGA)、倒装芯片(FC)、三维集成电路(3DIC)、晶片级封装(WLP)、迹线上接合(BOT，bond-on-trace)封装以及封装层叠(PoP)结构。然而，这些封装技术要求具有高成本和大形状因数的有机衬底。
本领域需要的是用于半导体器件的改进封装结构和方法。
发明内容
为解决上述问题，本发明提供了一种封装半导体器件，包括：再分布层(RDL)，RDL包括第一表面和与第一表面相对的第二表面；至少一个集成电路，连接至RDL的第一表面；多个金属凸块，连接至RDL的第二表面；以及模塑料，设置在至少一个集成电路和RDL的第一表面的上方。
其中，至少一个集成电路包括具有形成在其中的多个衬底通孔(TSV)的衬底，其中，至少一个集成电路包括至少一个第一集成电路，还包括设置在至少一个第一集成电路的至少一部分的上方的至少一个第二集成电路，至少一个第二集成电路的多个部分电连接至至少一个第一集成电路的多个部分，电连接至RDL，或者既电连接至至少一个第一集成电路又电连接至RDL。
其中，至少一个集成电路包括至少一个第一集成电路，还包括至少设置在RDL上方的至少一个第二集成电路，至少一个第二集成电路通过设置在RDL与至少一个第二集成电路之间的模塑料中的多个连接电连接至RDL。
其中，至少一个第二集成电路被设置在至少一个第一集成电路的至少一部分的上方。
此外，还提供了一种用于半导体器件的封装件，包括：再分布层(RDL)，RDL包括至少一个层间电介质(ILD)和至少一个金属化层，至少一个金属化层形成在至少一个ILD中，RDL具有第一表面和与第一表面相对的第二表面，其中，在RDL的第一表面上设置多个迹线，以及其中，多个接合焊盘被设置在RDL的第二表面上，多个接合焊盘通过至少一个金属化层中的配线分别电连接至多个迹线。
该封装件还包括：多个焊料块，分别连接至多个接合焊盘；以及模塑料，设置在多个焊料块之间的RDL的第二表面的上方。
其中，沿着x-y轴设置多个迹线，RDL还包括沿着z轴设置的多个z轴连接件件，z轴基本上垂直于x-y轴。
其中，多个z轴连接件件包括连接至封装件的集成电路的引线接合件、金属柱、焊球、金属立柱凸块堆叠件、或衬底通孔。
其中，RDL的至少一个金属化层包括至少一个第一金属化层，其中，封装件还包括设置在多个z轴连接件和RDL上方的至少一个第二金属化层。
其中，至少一个第二金属化层包括连接至多个z轴连接件的多个接触焊盘。
此外，还提供了一种封装半导体器件的方法，方法包括：提供载体晶片；在载体晶片的上方形成再分布层(RDL)，RDL包括至少一个层间电介质(ILD)和至少一个金属化层，至少一个金属化层形成在至少一个ILD中，RDL具有第一表面和与第一表面相对的第二表面；将至少一个集成电路连接至RDL的第一表面；在至少一个集成电路和RDL的第一表面的上方形成模塑料；在RDL的第二表面上形成多个金属凸块；以及去除载体晶片。
其中，将至少一个集成电路连接至RDL的第一表面包括使用迹线上接合(BOT)附接技术。
其中，连接至少一个集成电路包括连接至少一个第一集成电路，其中，形成模塑料包括形成第一模塑料，还包括：在形成模塑料之前，在RDL的上方形成多个z轴连接件，多个z轴连接件连接至金属化层中的配线；在模塑料和z轴连接件的上方形成配线，配线包括多个x-y连接件；将至少一个第二集成电路连接至配线；以及在至少一个第二集成电路、配线、和第一模塑料的上方形成第二模塑料。
其中，形成RDL包括形成第一RDL，还包括：在形成模塑料之前，在第一RDL的上方形成多个z轴连接件，多个z轴连接件连接至第一RDL的金属化层中的配线；以及在多个z轴连接件的上方形成第二RDL，其中，第二RDL的多个部分提供与封装半导体器件的电接触。
该方法还包括：在形成模塑料之前，在第一RDL的上方形成多个z轴连接件，多个z轴连接件连接至第一RDL的金属化层中的配线，其中，多个z轴连接件提供与封装半导体器件的电接触。
其中，形成RDL包括形成第一RDL，其中，连接至少一个集成电路包括连接至少一个第一集成电路，至少一个第一集成电路包括多个衬底通孔(TSV)，以及其中，形成模塑料包括形成第一模塑料，还包括：去除至少一个第一集成电路的一部分，露出多个TSV；在至少一个第一集成电路、多个TSV、和第一模塑料的上方形成绝缘材料；去除绝缘材料的多个部分，从而露出多个TSV；在绝缘材料的上方形成配线，配线包括多个x-y连接件；将至少一个第二集成电路连接至配线；以及在至少一个第二集成电路、配线、和第一模塑料的上方形成第二模塑料，其中，形成绝缘材料和形成配线包括形成第二RDL。
其中，提供载体晶片包括提供第一载体晶片，第一载体晶片包括由半导体材料组成的衬底，还包括：在衬底的上方形成绝缘材料；对绝缘材料进行图案化；通过图案化的绝缘材料去除衬底的一部分；在图案化的绝缘材料的上方形成配线，其中，形成绝缘材料、对绝缘材料进行图案化、和形成配线包括形成RDL；在连接至少一个集成电路和形成模塑料之后，将第二载体晶片连接至模塑料；去除衬底的一部分，露出配线的一部分；以及去除衬底的剩余部分，使配线的多个部分从绝缘材料突出。
其中，形成多个金属凸块包括：在去除衬底的剩余部分之后，在配线的从绝缘材料突出的部分的上方形成多个焊球，还包括：去除第二载体晶片。
其中，提供载体晶片包括提供第一载体晶片，第一载体晶片包括由半导体材料组成的衬底，还包括：在衬底的上方形成绝缘材料；对绝缘材料进行图案化；通过图案化的绝缘材料去除衬底的一部分；在图案化的绝缘材料的上方形成配线，其中，形成绝缘材料、对绝缘材料进行图案化、和形成配线包括形成RDL；用焊膏填充配线中的图案；回流焊膏；在连接至少一个集成电路和形成模塑料之后，将第二载体晶片连接至模塑料；去除衬底的一部分，露出配线的一部分；去除衬底的剩余部分；去除配线在绝缘材料的表面之外的部分，使焊膏的多个部分从绝缘材料突出；以及去除第二载体晶片，其中，形成多个金属凸块包括：在去除配线的多个部分之后，由从绝缘材料突出的焊膏形成多个金属凸块。
其中，连接至少一个集成电路包括连接至少一个第一集成电路，其中，形成RDL包括形成第一RDL，以及其中，形成模塑料包括形成第一模塑料，还包括：利用用于多个通孔的图案对第一模塑料进行图案化；用导电材料填充用于多个通孔的图案，在第一模塑料中形成多个z轴连接件；在多个z轴连接件的上方形成配线，配线形成多个x-y连接件，其中，配线和z轴连接件包括第二RDL；将至少一个第二集成电路连接至第二RDL的配线；以及在至少一个第二集成电路、配线、和第一模塑料的上方形成第二模塑料。
附图说明
对于更加完整地理解本公开及其优点，现在结合附图进行以下描述，其中：
图1至图7示出了根据本公开实施例的半导体器件的封装方法的截面图，其中，使用再分布层(RDL)和模塑料封装单个集成电路(IC)；
图8和图9示出了根据另一实施例的横向封装两个或以上IC的方法的截面图；
图10至图20示出了实施例的截面图，其中，形成包括丝焊(wire bond)的z轴连接件以允许两个或以上IC垂直的封装，以及其中，在金属化层中进行x-y连接。
图21和图22示出了包括具有丝焊的z轴连接件的实施例的截面图，其中，在z轴连接件的上方形成第二RDL层；
图23示出了具有丝焊z轴连接件的实施例的截面图，其中，没有形成x-y连接或第二RDL层；
图24和图25示出了实施例的截面图，其中，z轴连接件包括焊球，以及其中，在金属化层中进行x-y连接；
图26示出了实施例的截面图，其中，z轴连接件包括焊球，并且在z轴连接件的上方形成第二RDL层；
图27示出了实施例的截面图，其中，z轴连接件包括焊球，并且其中，没有形成x-y连接或第二RDL层；
图28和图29示出了实施例的截面图，其中，z轴连接件包括金属柱，以及其中，在金属化层中进行x-y连接；
图30示出了实施例的截面图，其中，z轴连接件包括金属柱，并且在z轴连接件的上方形成第二RDL层；
图31示出了实施例的截面图，其中，z轴连接件包括金属柱，并且没有形成x-y连接或第二RDL层；
图32至图38示出了实施例的截面图，其中，利用至少一个其他IC垂直地封装衬底通孔(TSV)IC；
图39示出了第二RDL形成在TSV IC之上的实施例；
图40至图47示出了根据另一实施例的封装一个IC或者横向封装两个或以上IC的方法的截面图，其中，封装的连接包括具有焊球的金属凸块；
图48至图52示出了图40至图47所示实施例的可选实施例，其中，焊膏被用于形成封装的金属凸块；
图53至图57示出了实施例的截面图，其中，垂直地将多个IC封装在一起，或者垂直且横向地将多个IC封装在一起；
图58示出了图53至图57所示实施例的可选实施例，其中，封装的金属凸块由焊膏形成；
图59至图65示出了利用至少一个其他IC垂直封装TSV IC的实施例的截面图；
图66示出了图59至图65所示实施例的可选实施例，其中，封装的金属凸块由焊膏形成；以及
图67示出了可以在本文所描述实施例中实施的包括金属立柱凸块堆叠件的z轴连接件的截面图。
除非另有指定，否则不同附图中对应标号和符合通常是指对应的部件。清楚地绘制附图以示出实施例的相关方面，并且不需要按比例绘制。
具体实施方式
以下详细讨论本公开实施例的制造和使用。然而，应该理解，本公开提供了可以以具体环境下的各种方式实施的许多可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用本公开的特定方式，而不用于限制公开的范围。
本公开的实施例涉及半导体器件的封装。将在本文描述利用各种制造方法和配置来单独或多重地封装一个以上IC、横向或垂直地封装一个以上IC或者它们的组合的多个实施例。
图1至图7示出了根据本公开实施例的封装半导体器件的方法的截面图。首先，参照图1，提供载体晶片100。例如，载体晶片100可包括玻璃、硅(例如，硅晶片)、氧化硅、金属板或陶瓷材料。在载体晶片100的上方涂覆粘合剂102。例如，粘合剂102可包括环氧树脂、硅橡胶、聚酰亚胺(PI)、聚对苯撑苯并双恶唑(PBO)、苯并环丁烯(BCB)、聚合物、或金属，尽管还可以使用其他材料。例如，可通过旋涂、印刷、化学汽相沉积(CVD)或物理汽相沉积(PVD)来涂覆粘合剂102。
在载体晶片100的上方(例如，在粘合剂102的上方)形成RDL 104。RDL 104可包括一个或多个绝缘层和配线层。RDL 104可包括层间电介质(ILD)110a、110b、110c，其中设置或形成有金属化层中的配线112。例如，配线112可包括一个或多个通孔和/或导线。如图所示，通孔和/或导线中的一个或多个可以在ILD 110a、110b、110c内连接在一起。在所示实例中，配线112包括第一配线112a和第二配线112b。
可通过在粘合剂102的上方形成或涂覆第一ILD 110a来形成RDL 104。ILD 110a被曝光和显影，利用开口对ILD 110a进行图案化以在预定位置露出粘合剂102的多个部分。第一配线112a通过以下处理形成：在图案化的ILD 110a的上方沉积第一光刻胶层(未示出)，对第一光刻胶层进行图案化，以及在图案化的ILD 110a的上方镀上第一配线112a。去除第一光刻胶层。在该实施例中包括单层的ILD 110b和110c被形成或涂覆在第一配线112a以及ILD 110a的露出部分的上方。ILD 110b/110c被曝光和显影，利用开口对ILD 110b/110c进行图案化以在预定位置露出下面的第一配线112a和ILD 110a的多个部分。第二配线112b通过以下处理形成：在图案化的ILD 110b/110c的上方沉积第二光刻胶层(也未示出)，对第二光刻胶层进行图案化，以及在图案化的ILD 110b/110c的上方镀上第二配线112b。然后，去除第二光刻胶层。
可选地，可通过对ILD 110a、110b和110c进行图案化以及用导电材料填充图案，通过一个或多个单或双镶嵌技术来形成RDL 104的配线112。或者，例如，可通过一个或多个减少蚀刻工艺来形成配线112，并且在每个减少蚀刻工艺之后可以在配线112的上方形成ILD 110a、110b和110c。
RDL 104包括用于连接至半导体器件或集成电路(IC)116的第一表面106。RDL 104还包括与第一表面106相对的第二表面108，用于进行例如使用封装的末端应用中的封装的电连接。配线112的一部分驻留在RDL104的第一表面106上。在一些实施例中，RDL 104的第一表面106上的配线112的多个部分包括可连接至IC 116的接触的迹线(trace)114。例如，在一些实施例中，IC 116使用迹线上接合(BOT)附接技术来附接至RDL104。
如图2所示，IC116附接至RDL 104。IC 116可包括其上形成有一个或多个电路的工件或衬底(未示出)。例如，IC 116可包括逻辑电路、存储器件或其他类型的电路。IC 116包括形成在其表面处的多个接触焊盘122。金属柱118可被形成为连接至接触焊盘122，并且可以在每个金属柱118上形成焊料块120。例如，金属柱118可包括铜或其他金属，并且是任选的；在一些实施例中，可以不包括金属柱118。此外，在一些实施例中，焊料块120可以直接形成在IC 116的接触焊盘122上。例如，通过将焊料块120接合至配线112的迹线114，IC 116被接合至RDL 104的配线112。
如图3所示，在IC 116和RDL 104的上方形成模塑料124。例如，在一些实施例中，模塑料124可包括压缩模并且可包括环氧树脂、橡胶或聚酰亚胺(PI)，尽管模塑料124可以可选地包括其他材料。如图所示，模塑料124可以至少部分地填充IC 116下方(例如，RDL 104和IC116之间)的空间。
如图4所示，然后去除载体晶片100和粘合剂102，露出RDL 104的配线112的第二表面108的多个部分126。例如，露出的部分126可以包括金属凸块的接合焊盘(landing pad)。例如，在一些实施例中，露出的部分126可包括用于焊球或焊料块的接合焊盘。
图5示出了图4的反转图。金属凸块128形成在配线112的露出部分126上。在所示实施例中，金属凸块128包括焊球。如图6所示，包括与所列出用于模塑料124的材料类似的材料的模塑料130可以任选地在金属凸块128之间形成在RDL 104的上方，尽管不要求将相同的材料用于两个模塑料。例如，在一些实施例中，模塑料130可包括大约10μm的厚度，尽管模塑料130可以包括其他尺寸。模塑料130足够薄使得金属凸块128的顶部从模塑料130突出。又例如，在一些实施中，模塑料130可包括大约为金属凸块128的高度的一半的厚度。例如，模塑料130可以有利地被大IC 116使用以提高可靠性。
然后，如图7所示，使用管芯切割或其他装置在切割线132处切割封装的多个IC 116(例如，在载体晶片100表面上同时形成多个IC 116(未示出))，并且封装的IC 116被分离，每一个都形成封装的半导体器件140。在图1至图7所示的实施例中，都使用RDL 104、一侧上的任选模塑料130以及另一侧上的模塑料124来封装每个单个IC 116。有利地，不要求衬底用于新颖的封装半导体器件140。例如，RDL 104的配线112的多个部分可以将RDL 104上的金属凸块128连接至IC 116的接触焊盘122。然后，封装的半导体器件140可以连接至印刷电路板(PCB)、连接至另一封装集成电路、连接至电或机械模块、或者连接至使用封装140的金属凸块128的其他器件。
在其他实施例中，如图8和图9的截面图所示，两个或以上的IC 116a、116b和116c可以横向地封装在单个封装中。在RDL 104形成在载体晶片100的上方之后，多个IC 116a、116b和116c接合至RDL 104的第一表面106。例如，在一些实施例中，IC 116a可包括逻辑芯片，以及IC 116b和116c可包括无源部件。可选地，IC 116a、116b和116c可用于执行其他功能。在一些实施例中，IC 116a、116b和116c可用于执行相同功能、不同功能或它们的组合。在图8和图9中示出了三个IC 116a、116b和116c；可选地，例如，可以在单个封装中横向地形成和封装多个IC 116a、116b和116c。
然后，执行参照图3至图7描述的封装技术，得到图9所示的封装IC140a。封装的半导体器件140a包括多芯片封装，其中，在封装140a中，彼此相邻横向地定位IC 116a、116b和116c。如图所示，可以通过RDL 104中的配线112将IC 116a、116b和116c连接在一起。有利地，例如，封装的半导体器件140a可包括系统级封装(SiP)。
图10至图20示出了一个实施例的截面图，其中，包括丝焊的z轴连接件134被形成为允许两个或以上的IC垂直进行封装，以及其中，包括配线136(参见图14)的x-y连接被形成在金属化层中。用于图10至图20中的各种元件的类似标号被用于描述图1至图9且避免了重复，在本文的细节中，可以不再次描述图10至图20所示的每个参考标号。
如图10所示，在如图1所示形成RDL 104之后，包括丝焊的z轴连接件134形成在RDL 104的上方，连接至配线112的露出部分。如本文进一步所描述的，z轴连接件134将用于将RDL 104连接至垂直在封装内的另一层中的IC或配线。例如，图10至图20中的z轴基本上与通过RDL 104横向形成的x-y面垂直。如图11所示，至少一个IC 116a的焊料块11Sa连接至RDL 104的迹线。在图11中仅示出了一个IC 116a；可选地，在RDL104的上方形成多个IC 116a。如图12所示，模塑料124a形成在IC 116a、z轴连接件134和RDL 104的上方(例如，如图2和图3所描述的)。在所示实施例中，模塑料124a包括第一模塑料。如图13所示，使用诸如化学机械抛光(CMP)工艺160的研磨工艺去除模塑料124a的顶部，以露出包括丝焊的z轴连接件134的顶面。可选地，可以使用深蚀刻工艺来去除模塑料的一部分。在其他实施例中，可以控制模塑料的沉积，使得z轴连接件134的顶面在模塑料沉积工艺之后保持露出，由此省去了去除模塑料一部分的需要。
然后，如图14所示，配线136形成在模塑料124a的上方以及包括丝焊的z轴连接件134的上方。配线136连接至z轴连接件134，并提供用于封装的x-y连接(例如，在所示附图中，进出纸张的方向)。配线136包括其在多个部分上的迹线138。如图15所示，至少一个IC 116b和/或116c附接至配线136。在图15中示出了两个IC 116b和116c；可选地，例如，可以在RDL 104的表面的上方形成多个IC 116b和116c。如图所示，IC 116b和116c的多个部分可以驻留在下面层中的IC 116a的上方。IC 116b的焊料块118b连接至配线136的迹线138，而IC 116C的焊料块118c也连接至配线136的迹线138。
如图16所示，在结构的上方(例如，在IC 116b和116c、配线136以及第一模塑料124a的上方)形成包括与所描述用于第一模塑料124a的材料类似的材料的第二模塑料124b。如图17所示，然后取出载体晶片100和粘合剂102。如图18所示，金属凸块128形成在RDL 104上，并且如图19所示，模塑料130可以可选地形成在金属凸块128之间的RDL 104的上方。然后，在切割线132处切割RDL 104以形成图20所示的封装半导体器件140b。
封装半导体器件140b包括多芯片封装，其中，在封装中垂直地定位IC116a、IC 116b和IC 116c。如图所示，IC 116a、116b和116c可以通过RDL104中的配线112以及通过由包括丝焊的z轴连接件134所提供的垂直连接来连接在一起。例如，封装半导体器件140b可以有利地包括SiP。
图21和图22示出了包括具有丝焊的z轴连接件134的实施例的截面图，其中，第二RDL 104b形成在z轴连接件的上方。在该实施例中，图10所示的RDL 104被标为图21和图22中的RDL 104a。如图10至图14所描述，执行封装处理步骤。然后，在配线136的上方形成包括绝缘材料142的RDL 104b。在该实施例中，配线136是RDL 104b的一部分并且提供用于封装的x-y连接。如图21所示，使用光刻对绝缘材料142进行图案化以露出配线136的多个部分。如图17至图20所描述地继续处理，形成图22所示的封装半导体器件140c。RDL 104b的露出区域可用于将封装半导体器件140c附接至另一IC、PCB或者另一类型的器件(未示出)。
如图23所示，在另一实施例中，在封装半导体器件140d中可以不存在任何x-y连接或第二RDL。执行图10至图13所示的处理步骤，但是不形成图14所示的配线136。此外，执行图17至图20所示的处理步骤，留下图23所示的封装半导体器件140d。例如，根据末端应用，包括z轴连接件134的丝焊的露出端146可用于连接至另一封装或器件。
图24和图25示出了一个实施例的截面图，其中，z轴连接件134包括焊球，以及在金属化层(即，配线136)中制造x-y连接。在该实施例中，如图24所示，在形成图1所示RDL 104之后，包括焊球的z轴连接件134形成在RDL 104的上方，连接至配线112的露出部分。如图25所示，包含焊球的z轴连接件134将RDL 104连接至随后形成的IC 116b和116c。执行参照图11至图20所描述的制造工艺，形成图25所示的封装半导体器件140e。封装半导体器件140e包括多芯片封装，其中，在封装中垂直地定位IC 116a、IC 116b和116C。如图所示，IC 116a、116b和116c可以通过RDL 104中的配线112和/或通过由包含焊球的z轴连接件134提供的垂直连接连接在一起。例如，封装半导体器件140e可以有利地包括SiP。
可以类似于图10至图20所示实施例的修改来修改图24和图25所示的实施例。例如，如参照图21和图22所描述的，如图26所示，可以形成第二RDL 104a。焊球包括z轴连接件134，其将RDL 104a连接至图26所示封装半导体器件140f的第二RDL 104b。在另一实施例中，如图27所示，配线136和第二RDL 104b都不包括在封装半导体器件140g中。有利地，该实施例中的封装半导体器件140g在一侧上具有金属凸块128以及在另一侧具有包括焊球的z轴连接件。
图28和图29示出了一个实施例的截面图，其中，z轴连接件134包括金属柱，以及其中，在金属化层(即，配线136)中制造x-y连接。在该实施例中，如图28所示，在如图1所示形成RDL 104之后，包括金属柱的z轴连接件134形成在RDL 104的上方，连接至配线112的露出部分。如图29所示，包括金属柱的z轴连接件134将RDL 104连接至随后形成的IC116b和116c。
可通过首先形成RDL 104然后在RDL 104的上方形成光刻胶层(未示出)来形成金属柱。针对用于金属柱的期望图案对光刻胶进行图案化。然后，可使用电镀技术形成金属柱。然后，去除光刻胶。
执行参照图11至图20所描述的制造工艺步骤，形成图29所示的封装半导体器件140h。封装半导体器件140h包括多芯片封装，其中，在封装中垂直地定位IC 116a、IC 116b和116C。如图所示，IC 116a、116b和116c可以通过RDL 104中的配线112和/或通过由包含金属柱的z轴连接件134提供的垂直连接连接在一起。例如，封装半导体器件14h可以有利地包括SiP。
类似于图10至图20所示实施例以及图24和图25所示实施例的修改，可以修改图28和图29所示的实施例。例如，如参照图21和图22所描述的，如图30所示，可以形成第二RDL 104b。金属柱包括z轴连接件134，其将RDL 104a连接至封装半导体器件140i的第二RDL 104b。在另一实施例中，如图31所示，配线136和第二RDL 104b都不包括在封装半导体器件140j中。该实施例中的封装半导体器件140j在一侧上具有金属凸块128以及在另一侧上具有包括金属柱的z轴连接件134。
图32至图38示出了一个实施例的截面图，其中，与至少一个其他IC116b和116c一起垂直地封装包括衬底通孔(TSV)IC的IC 116a(参见图36)。如图32所示，IC 116a包括形成在其表面上的衬底148和绝缘材料149。多个TSV 150形成在绝缘材料149中以及衬底148的多个部分中。多个金属化层152形成在TSV 150和绝缘材料149的上方。金属化层152包括形成在多个绝缘材料层158中的多个导线和通孔154。
在参照图1描述的封装步骤之后，如本文的先前实施例所描述的，IC116a连接至RDL 104a，例如，如图32所示，IC 116a的接触焊盘122a通过金属柱118a和焊料块120a连接至配线112的迹线114。如图33所示，第一模塑料124a形成在IC 116a和RDL 104的上方，并且还如图33所示，封装露出给一个或多个CMP处理器160，或者去除模塑料124a的顶部且还去除IC 116a的衬底148的一部分的蚀刻工艺露出TSV 150的顶面162。如图34所示，包括绝缘材料164的隔离层形成在IC 116a和模塑料124a的上方，并且使用光刻对绝缘164进行图案化，在绝缘材料164中形成开口166，以及露出TSV 150的顶面162。如图35所示，导电材料形成在绝缘材料164的上方并使用光刻进行图案化，形成连接至TSV 150的顶面162的配线136。在该实施例中，配线136和绝缘材料164起到第二RDL 10b的功能。
如图36所示，至少一个IC 116a或116c连接至第二RDL 104b的配线136。在图36中示出了两个IC 116b和116c；可选地，例如，如本文描述的其他实施例，可以在RDL 104b的表面的上方形成多个IC 116b和116c。IC 116b和116c的至少多个部分可以驻留在下面层中的IC 116a的上方，并且如图所示，在一些实施例中，IC 116b和116c的整体可以驻留在IC 116a的上方。IC 116b的焊料块118b连接至配线136的迹线138，并且IC 116c的焊料块118c也连接至配线136的迹线138。
如图37所示，在结构的上方(例如，在IC 116b和116c、配线136以及绝缘材料164的上方)形成包括与如针对第一模塑料124a所描述材料类似的材料的第二模塑料124b。如图37所示，然后还去除载体晶片100和粘合剂102。如图38所示，金属凸块128形成在RDL 104a上，并且模塑料130可以可选地形成在金属凸块128之间的RDL 104的上方。然后，切割该结构以形成图38所示的封装半导体器件140k。
新颖的封装半导体器件140k包括3DIC，其包括具有TSV 150的IC116a。封装半导体器件140k包括多芯片封装，其中，在封装中垂直地定位IC 116a以及IC 116b和116c。IC 116a、116b和116c可以通过第一RDL 104a中的配线112、通过由IC 116a的TSV 150提供的垂直连接、和/或通过第二RDL 104b的配线136而连接在一起。例如，封装半导体器件140k可以有利地包括SiP。
图39示出了图32至图38所示实施例的可选实施例，其中，第二RDL104b形成在包括TSV IC的IC 116a的上方。如先前参照图22、图26和图30所示实施例所描述的，封装半导体器件140m包括单个IC 116a，并且可以针对RDL 104b的露出部分上的封装制造电连接。
在图1至图39所示的实施例中，首先提供载体晶片100，并且RDL 104或第一RDL 104a形成在载体晶片100的上方。当不再需要封装工艺流程之后，去除载体晶片100。因此，载体晶片100是封装工艺中的牺牲部件。
在图40至图66所示的实施例中，所使用的载体晶片包括衬底268，其包括形成封装的RDL 104和接合焊盘期间的牺牲器件。用于描述图1至图39的类似标号被用于图40至图66的各个元件。为了避免重复，在本文不再详细描述图40至图66所示的每个参考标号。此外，用于描述图1至图39的类似材料x00、x02、x04等用于描述所示的各种材料层和部件，其中，在图40至图66中x＝2。
图40至图47示出了根据本公开另一实施例的封装一个IC 216a或者横向地封装两个或以上的IC 216a和216b的方法的截面图，其中，封装的连接包括具有焊球的金属凸块。首先，如图40所示，提供衬底268。例如，衬底可包括诸如硅的半导体材料。例如，在一些实施例中，衬底268包括裸硅晶片。衬底268在本文(例如在权利要求)中也被称为载体晶片。在所示实施例中，衬底268包括第一载体晶片。
如图40所示，绝缘材料210还形成在衬底268的上方并使用光刻进行图案化。如图41所示，例如使用诸如干或湿蚀刻工艺的蚀刻工艺去除衬底268的顶面。例如，绝缘材料210可用作蚀刻工艺中的掩模。绝缘材料210将用作用于RDL 204的绝缘材料。
接下来，如图42所示，配线212形成在绝缘材料210的上方。例如，配线212通过以下处理形成：在绝缘材料210和衬底268的露出部分上沉积导电材料，以及对导电材料进行图案化以形成配线212。例如，可通过Ti/Cu的第一层上的溅射以及随后在Ti/Cu层上电镀Ni/Cu来形成配线212。可以可选地使用其他方法来形成配线212。配线212包括具有用于连接焊料块220以将IC 216a或216b连接至RDL 204a的迹线214的多个部分。在该实施例中，配线212和绝缘材料210形成RDL 204。
如本文其他实施例所描述的以及如图43所示，例如，使用BOT技术，IC 216a和216b连接至配线212的迹线214。模塑料224形成在IC 216a和216b的上方以及RDL 204的上方。衬底268包括IC 216被单独封装的第一区域272a以及IC 216a和216b(以及任选地与未示出的IC)被封装在一起的第二区域272b。
如图44所示，第二载体晶片200使用粘合剂202接合或附接至模塑料224。如图44所示，露出该结构进而进行研磨或CMP工艺260，去除衬底268或第一载体晶片的一部分，以及留下露出的配线212的顶面274。如图45所示，使用蚀刻工艺276去除衬底268的剩余部分，留下露出的RDL 204的绝缘材料210。例如，蚀刻工艺276可包括干式或湿式硅蚀刻工艺。配线212的多个部分在绝缘材料210的顶面的上方突出。因此，在封装工艺中，已经在该点处从结构中去除包括第一载体晶片的衬底268。
如图46所示，金属凸块228形成在配线212的露出部分上。例如，金属凸块228包括焊球并且可以使用焊球点滴工艺来形成。载体晶片200和粘合剂202被释放或去除，并且在切割线232处切割封装，如图47所示，在切割工艺之后，形成在第一区域272a中包括单个IC 216a的封装半导体器件280a，以及形成在第二区域272b中包括多个IC 216a和216b的封装半导体器件280b。如先前实施例所描述的，可选的模塑料(未示出)还可以形成在金属凸块228之间的绝缘材料210的上方。诸如先前实施例所示的模塑料130的可选模塑料还可以包括在本文的剩余实施例中(在附图中未示出)。
因此，根据图40至图47所示的实施例，使用两个载体晶片268和200形成包括RDL 204和模塑料224的封装半导体器件280a和280b。在该实施例中，封装半导体器件280a和280b的金属凸块228包括焊球。
图48至图52示出了图40至图47所示实施例的可选实施例，其中，焊膏被用于形成封装的金属凸块228。在如图42所示形成RDL 204的配线212之后，如图48所示，焊膏282形成在配线212以及绝缘材料210的露出部分的上方。焊膏282粘附至配线212且不粘附至绝缘材料210。如图49所示，焊膏282进入回流工艺284，在回流工艺284之后，在配线212图案内的焊膏282的上方形成凹陷区域286。
如图50所示，IC 216a和216b连接至配线212的迹线214，并且如图51所示，模塑料224形成在IC 216a和216b的上方以及RDL 204的上方。如图51所示，第二载体晶片200还使用粘合剂202接合或附接至模塑料224。接下来是参照图44和图45示出和描述的封装工艺，并且如图52所示，针对蚀刻工艺露出该结构以从绝缘材料210上方的焊膏282的表面上去除配线，留下露出的焊膏282。如图52所示，去除第二载体晶片200，并且切割该结构，留下在第一区域272a(未示出)中包括单个IC 216b的封装半导体器件，以及留下包括从第二区域272b中切割的多个IC 216a和216b的封装半导体器件280c。
在该实施例中，不同于先前实施例中形成焊球以形成金属凸块228，金属凸块228包括形成在RDL 204的配线214内的焊膏282。该实施例的优点在于不需要形成焊球的处理步骤。包括焊膏282的金属凸块228包括可用于将封装半导体器件280c连接至PCB、另一集成电路、另一封装或其他器件的接合焊盘。如先前实施例所描述的，可选的模塑料(未示出)还可以形成在金属凸块228之间的绝缘材料210的上方
图53至图57示出了一个实施例的截面图，其中，多个IC垂直地封装在一起或者垂直且横向地封装在一起。封装工艺最初为如参照图40至图43所描述的相同过程。然后，如图53所示，在该实施例中包括第一模塑料224a的模塑料224被蚀刻以在第一模塑料224a内形成用于通孔的图案290。如图54所示，用导电材料填充用于通孔的图案290以在第一模塑料224a中形成通孔292。在该实施例中，通孔292用作z轴连接件234。如图55所示，包括x-y连接的配线236形成在模塑料224a和通孔292的上方，并且IC 216a和216b连接至配线236。如图56所示，第二模塑料224b形成在IC 216a和216b、配线236和第一模塑料224a的上方，并且第二载体晶片200使用粘合剂202连接至第二模塑料224b。执行如图44至图47所描述的封装工艺，并且如图57所示，在切割线232处切割该结构，在第一区域272a中形成封装半导体器件280d以及在第二区域282b中形成封装半导体器件280e。
图58示出了图53至图57所示实施例的可选实施例，其中，如图52的实施例所描述的，封装的金属凸块由焊膏282形成。接下来为与参照图53至图56以及图58所描述的封装工艺组合的参照图48至图52描述的封装工艺，以实现图58所示的封装半导体器件280f和280g。
图59至图65示出了一个实施例的截面图，其中，IC 216a TSV IC与至少一个其他IC垂直地封装在一起。在图59和图60中示出了用于包括TSV IC的IC 216a的制造工艺的一部分。提供衬底248，并且利用用于TSV250的图案对衬底248进行图案化。图案可以首先利用绝缘体来加衬，并且用导电材料进行填充以形成TSV 250。TSV部分地延伸穿过衬底248。例如，在后端工艺(BEOL工艺)中，金属化层252形成在绝缘材料249和TSV 250的上方，并且如图所示，金属柱218a和焊料块220a形成在IC216a的接触222a的上方。在切割线296处切割管芯216a。
如图61所示，接下来为参照图40至图42所描述的封装工艺，并且包括TSV的IC 216a附接至配线212。如图61所示，第一模塑料224a形成在IC 216的上方，并且CMP工艺260用于去除管芯216a的衬底248的一部分，露出管芯216的TSV的表面262。接下来为如参照图34至图36所描述的类似工艺流程：形成并图案化绝缘材料264(图62)，形成配线236(图63)，以及配线236和绝缘材料264形成第二RDL 204a，并且IC 216b和216c附接至配线236(图64)。然后为图56和图57所描述的处理步骤，以实现图65所示的封装半导体器件280h和280i。
图66示出了图59至图65所示实施例的可选实施例，其中，如参照图58所描述的，封装的金属凸块282由焊膏形成，形成所示的封装半导体器件280j和280k。
如图67的截面图所示，本文所描述的z轴连接件134可以可选地包括金属立柱凸块堆叠件。例如，包括z轴连接件134的本公开的实施例可以包括金属立柱凸块堆叠件而不是本文先前所描述的其他z轴连接件类型。每个金属立柱凸块堆叠件都包括金属立柱198，其上形成有多个凸块199，它们沿着立柱198的高度垂直地设置。两个或以上的焊料块199可形成在每个立柱198上。例如，立柱198可包括Au、Cu、其他金属或它们的组合，并且凸块199可包括焊料、其他材料或它们的组合。
本公开实施例的优点包括提供了用于半导体器件的新颖封装方法和结构。在一些实施例中，独立地封装IC 116、116a、116b、216a或216b。在其他实施例中，多个IC 116、116a、116b、116c、216a、216b或216c被封装在单个封装中并且可以在单个材料层中垂直堆叠或横向配置。IC可包括提供垂直连接的TSV IC，或者垂直连接(z轴连接件)可以使用丝焊、焊球、金属柱或金属立柱凸块堆叠件来制造。RDL 104、104a、104b、204、204a和204b可以使用载体晶片或衬底来形成。一个载体晶片或两个载体晶片可用于形成本文所描述的新颖封装。可以在封装和制造工艺流程中容易地实施新颖的封装方法和结构。
有利地，实施例的新颖封装方法和结构不需要衬底，这节省了时间、金钱、空间和重量。封装高度可靠，这是因为不存在CTE失配问题(因为没有衬底)，并且具有低制造成本和高产量。使用BOT技术附接和接合IC，这使得大大减少了成本。
本文所描述的实施例采用芯片重新分布和模制技术以使用载体晶片100、200和268有效地重新执行新晶片，放大了用于RDL布局的芯片面积。通过实施TSV芯片重新分布，通过在模塑料中钻通孔，可以实施3D-SiP。实施例组合了3D-TSV和扇出晶片级处理(WLP)以实现高输入/输出扇出。简化了芯片重新分布模制方法，并且实现了大量的管芯位移控制。在一些实施例中，裸硅晶片被用作处理载体晶片268，并且还用作牺牲工具来形成RDL和3D结构球形焊盘。在一些实施例中(例如，在图46、图47、图57和图65所示的实施例中)，用于球形焊盘的3D结构导致改进的接合可靠性并利于大封装的封装。有利地，在一些实施例中，使用晶片级工艺制造本文所描述的新颖封装结构。
利用本文描述的实施例可以实现具有小形状因数的SiP结构。例如，更多的成熟封装类型可附接至诸如无芯片球栅阵列(FCBGA)、丝焊BGA、晶片级芯片尺寸封装(WLCSP)或无源器件的封装。通过本文所描述的实施例可以实现诸如3D eWLB封装和3D-TSV eWLB封装的3D晶片级接合(WLB)封装、SiP、3D-SiP、PoP结构和扇出WLP。
本公开的实施例包括封装本文所描述的半导体器件或管芯116、116a、116b、116c和116d的方法，并且还包括使用本文描述的方法和材料封装的封装半导体器件140、140a、140b、140c、140d、140e、140f、140g、140h、140i、140j、140k、140m、280、280a、280b、280c、280d、280e、280f、280g、280h、280i、280j和280k。实施例还包括用于本文所描述半导体器件的封装。
根据本公开的一个实施例，封装半导体器件包括具有第一表面和与第一表面相对的第二表面的RDL。至少一个集成电路连接至RDL的第一表面，以及多个金属凸块连接至RDL的第二表面。模塑料设置在至少一个集成电路和RDL的第一表面的上方。
根据另一实施例，用于半导体器件的封装包括RDL，其包括至少一个ILD和至少一个金属化层。至少一个金属化层形成在至少一个ILD中。多个迹线设置在RDL的第一表面上，并且多个接合焊盘设置在RDL的第二表面上，第二表面与第一表面相对。多个接合焊盘通过至少一个金属化层中的配线分别电连接至多个迹线。
根据又一实施例，封装半导体器件的方法包括提供载体晶片以及在载体晶片的上方形成RDL。RDL包括至少一个ILD和至少一个金属化层。至少一个金属化层形成在至少一个ILD中，并具有第一表面和与第一表面相对的第二表面。该方法包括：将至少一个集成电路连接至RDL的第一表面；以及在至少一个集成电路和RDL的第一表面的上方形成模塑料。多个金属凸块形成在RDL的第二表面上，并且去除载体晶片。
尽管详细描述了实施例及其优点，但应该理解，在不背离由所附权利要求限定的实施例的精神和范围的情况下，可以进行各种改变、替换和修改。例如，本领域的技术人员可以容易地理解可以改变本文所描述的许多特征、功能、工艺和材料，同时在本公开的范围之内。此外，本申请的范围不限于说明书中描述的工艺、机器、制造、物质组成、装置、方法和步骤的特定实施例。本领域的技术人员应该容易地从公开中理解，可以根据公开利用现有或稍后开发的执行与本文所描述对应实施例基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、装置、方法和步骤。因此，所附权利要求用于在它们的范围内包括这些工艺、机器、制造、物质组成、装置、方法和步骤。

Claims (10)

1.一种封装半导体器件，包括：
再分布层(RDL)，所述RDL包括第一表面和与所述第一表面相对的第二表面；
至少一个集成电路，连接至所述RDL的所述第一表面；
多个金属凸块，连接至所述RDL的所述第二表面；以及
模塑料，设置在所述至少一个集成电路和所述RDL的所述第一表面的上方。
2.根据权利要求1所述的封装半导体器件，其中，所述至少一个集成电路包括具有形成在其中的多个衬底通孔(TSV)的衬底，其中，所述至少一个集成电路包括至少一个第一集成电路，还包括设置在所述至少一个第一集成电路的至少一部分的上方的至少一个第二集成电路，所述至少一个第二集成电路的多个部分电连接至所述至少一个第一集成电路的多个部分，电连接至所述RDL，或者既电连接至所述至少一个第一集成电路又电连接至所述RDL。
3.根据权利要求1所述的封装半导体器件，其中，所述至少一个集成电路包括至少一个第一集成电路，还包括至少设置在所述RDL上方的至少一个第二集成电路，所述至少一个第二集成电路通过设置在所述RDL与所述至少一个第二集成电路之间的模塑料中的多个连接电连接至所述RDL。
4.根据权利要求3所述的封装半导体器件，其中，所述至少一个第二集成电路被设置在所述至少一个第一集成电路的至少一部分的上方。
5.一种用于半导体器件的封装件，包括：
再分布层(RDL)，所述RDL包括至少一个层间电介质(ILD)和至少一个金属化层，所述至少一个金属化层形成在所述至少一个ILD中，所述RDL具有第一表面和与所述第一表面相对的第二表面，其中，在所述RDL的所述第一表面上设置多个迹线，以及其中，多个接合焊盘被设置在所述RDL的所述第二表面上，所述多个接合焊盘通过所述至少一个金属化层中的配线分别电连接至所述多个迹线。
6.根据权利要求5所述的封装件，还包括：
多个焊料块，分别连接至所述多个接合焊盘；以及
模塑料，设置在所述多个焊料块之间的所述RDL的所述第二表面的上方。
7.根据权利要求5所述的封装件，其中，沿着x-y轴设置所述多个迹线，所述RDL还包括沿着z轴设置的多个z轴连接件件，所述z轴基本上垂直于所述x-y轴。
8.根据权利要求7所述的封装件，其中，所述多个z轴连接件件包括连接至所述封装件的集成电路的引线接合件、金属柱、焊球、金属立柱凸块堆叠件、或衬底通孔。
9.根据权利要求7所述的封装件，其中，所述RDL的所述至少一个金属化层包括至少一个第一金属化层，其中，所述封装件还包括设置在所述多个z轴连接件和所述RDL上方的至少一个第二金属化层。
10.根据权利要求9所述的封装件，其中，所述至少一个第二金属化层包括连接至所述多个z轴连接件的多个接触焊盘。
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Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253111A (zh) * 2013-06-27 2014-12-31 英特尔公司 用于ic封装的硅空间转变器
CN104851816A (zh) * 2015-04-13 2015-08-19 华进半导体封装先导技术研发中心有限公司 一种多芯片高密度封装方法
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
CN105225965A (zh) * 2015-11-03 2016-01-06 中芯长电半导体（江阴）有限公司 一种扇出型封装结构及其制作方法
CN105321903A (zh) * 2014-07-17 2016-02-10 台湾积体电路制造股份有限公司 具有重分布线的堆叠集成电路
CN105489580A (zh) * 2014-09-17 2016-04-13 日月光半导体制造股份有限公司 半导体衬底及半导体封装结构
CN106531710A (zh) * 2017-01-11 2017-03-22 中芯长电半导体（江阴）有限公司 一种集成供电系统的封装件及封装方法
CN106558565A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
CN106684056A (zh) * 2017-03-22 2017-05-17 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装结构及其制备方法
CN106783649A (zh) * 2017-01-11 2017-05-31 中芯长电半导体（江阴）有限公司 一种集成供电系统封装件的封装方法
CN106981467A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
CN106981468A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
CN107146778A (zh) * 2017-06-30 2017-09-08 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN107180766A (zh) * 2017-05-11 2017-09-19 王家恒 扇出型封装结构及其制作方法、终端设备
CN107195551A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 扇出型叠层封装结构及其制备方法
CN107195625A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 双面塑封扇出型系统级叠层封装结构及其制备方法
US9941249B2 (en) 2014-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Multi-wafer stacking by Ox-Ox bonding
CN108109928A (zh) * 2017-12-29 2018-06-01 中芯长电半导体（江阴）有限公司 半导体芯片的封装结构及封装方法
CN108352379A (zh) * 2015-12-21 2018-07-31 英特尔Ip公司 系统级封装装置以及用于形成系统级封装装置的方法
US10056353B2 (en) 2013-12-19 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
CN108962842A (zh) * 2017-05-26 2018-12-07 南茂科技股份有限公司 指纹识别芯片的封装结构及其制造方法
US10157891B2 (en) 2013-12-19 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
CN110504172A (zh) * 2018-05-16 2019-11-26 中芯长电半导体（江阴）有限公司 垂直打线结构、堆叠芯片封装结构及方法
CN110783687A (zh) * 2018-07-30 2020-02-11 群创光电股份有限公司 封装结构与使用其的天线装置
CN112542451A (zh) * 2019-09-23 2021-03-23 苹果公司 用于集成专用集成电路和光学元件的嵌入式封装概念
CN112786540A (zh) * 2019-11-06 2021-05-11 富泰华工业（深圳）有限公司 扇出型封装结构及其制作方法
CN112928028A (zh) * 2021-01-22 2021-06-08 广东佛智芯微电子技术研究有限公司 一种具有嵌入式线路的板级芯片封装方法及其封装结构
US20210273013A1 (en) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked image sensor device and method of forming same
CN115332088A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 一种基于中介层的封装及制作方法

Families Citing this family (326)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8058726B1 (en) 2008-05-07 2011-11-15 Amkor Technology, Inc. Semiconductor device having redistribution layer
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US20130075894A1 (en) * 2011-09-23 2013-03-28 Texas Instruments Incorporated Integrated circuit and method of making
US9219029B2 (en) 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US8552557B1 (en) * 2011-12-15 2013-10-08 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8664090B1 (en) 2012-04-16 2014-03-04 Amkor Technology, Inc. Electronic component package fabrication method
KR20130140321A (ko) * 2012-06-14 2013-12-24 에스케이하이닉스 주식회사 임베디드 패키지 및 제조 방법
US8872326B2 (en) * 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8970023B2 (en) * 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9245862B1 (en) 2013-02-12 2016-01-26 Amkor Technology, Inc. Electronic component package fabrication method and structure
US8890284B2 (en) * 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9362236B2 (en) 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
CN104051383B (zh) * 2013-03-15 2018-02-27 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件
US9142530B2 (en) * 2013-03-21 2015-09-22 Stats Chippac Ltd. Coreless integrated circuit packaging system and method of manufacture thereof
KR101473093B1 (ko) * 2013-03-22 2014-12-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101494814B1 (ko) * 2013-04-15 2015-02-23 앰코 테크놀로지 코리아 주식회사 팬 아웃 반도체 패키지 및 그 제조 방법
KR101488608B1 (ko) * 2013-07-19 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
TWI527173B (zh) 2013-10-01 2016-03-21 旭德科技股份有限公司 封裝載板
US9466581B2 (en) 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9553059B2 (en) * 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
KR101601388B1 (ko) * 2014-01-13 2016-03-08 하나 마이크론(주) 반도체 패키지 및 그 제조 방법
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
KR20150091932A (ko) 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9406642B1 (en) * 2014-03-11 2016-08-02 Stats Chippac Ltd. Integrated circuit packaging system with insulated trace and method of manufacture thereof
US9418877B2 (en) * 2014-05-05 2016-08-16 Qualcomm Incorporated Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US9466560B2 (en) 2014-05-28 2016-10-11 United Microelectronics Corp. Interposer fabricating process and wafer packaging structure
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
TWI655727B (zh) * 2014-06-17 2019-04-01 恆勁科技股份有限公司 封裝基板及包含該封裝基板的覆晶封裝電路
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9425178B2 (en) * 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9613910B2 (en) 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9892952B2 (en) 2014-07-25 2018-02-13 Semiconductor Components Industries, Llc Wafer level flat no-lead semiconductor packages and methods of manufacture
US10468381B2 (en) * 2014-09-29 2019-11-05 Apple Inc. Wafer level integration of passive devices
US9502322B2 (en) * 2014-10-24 2016-11-22 Dyi-chung Hu Molding compound supported RDL for IC package
US9679862B2 (en) * 2014-11-28 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device having conductive bumps of varying heights
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9972602B2 (en) * 2015-02-23 2018-05-15 Marvell World Trade Ltd. Method and apparatus for interconnecting stacked dies using metal posts
US10497660B2 (en) * 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9659805B2 (en) 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US9484227B1 (en) 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US10170444B2 (en) * 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US9793231B2 (en) 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US10276541B2 (en) * 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
KR102398663B1 (ko) 2015-07-09 2022-05-16 삼성전자주식회사 칩 패드, 재배선 테스트 패드 및 재배선 접속 패드를 포함하는 반도체 칩
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9373605B1 (en) 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9564345B1 (en) 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9761534B2 (en) 2015-09-21 2017-09-12 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10784206B2 (en) 2015-09-21 2020-09-22 Mediatek Inc. Semiconductor package
US9929112B2 (en) 2015-09-25 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10068844B2 (en) 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US10720788B2 (en) 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
US10304700B2 (en) 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9953892B2 (en) 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US9953963B2 (en) 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9786614B2 (en) 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9793245B2 (en) * 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9735118B2 (en) 2015-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas and waveguides in InFO structures
KR102109569B1 (ko) * 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10074472B2 (en) 2015-12-15 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. InFO coil on metal plate with slot
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US10050013B2 (en) 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US9984998B2 (en) 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US20170213801A1 (en) * 2016-01-22 2017-07-27 Micron Technology, Inc. Method for manufacturing a package-on-package assembly
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9768303B2 (en) 2016-01-27 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for FinFET device
US10903166B2 (en) 2016-01-28 2021-01-26 Intel IP Corporation Integrated circuit packages
DE102016118802B4 (de) 2016-01-29 2022-12-08 Taiwan Semiconductor Manufacturing Co. Ltd. Drahtloses Ladepaket mit in Spulenmitte integriertem Chip und Herstellungsverfahren dafür
US9761522B2 (en) 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9904776B2 (en) 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US9754805B1 (en) 2016-02-25 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging method and structure
US10797038B2 (en) 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US9842815B2 (en) 2016-02-26 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9847320B2 (en) 2016-03-09 2017-12-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the same
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
WO2017160231A1 (en) * 2016-03-14 2017-09-21 Agency For Science, Technology And Research Semiconductor package and method of forming the same
US9935009B2 (en) * 2016-03-30 2018-04-03 International Business Machines Corporation IR assisted fan-out wafer level packaging using silicon handler
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US9935024B2 (en) 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9859229B2 (en) 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US9947552B2 (en) 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US9997464B2 (en) 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9922895B2 (en) 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US9754914B1 (en) * 2016-05-10 2017-09-05 Rosemount Aerospace Inc. Method to provide die attach stress relief using gold stud bumps
US9806059B1 (en) 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10797025B2 (en) 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US9870997B2 (en) 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
US9852957B2 (en) 2016-05-27 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Testing, manufacturing, and packaging methods for semiconductor devices
US9941248B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures, pop devices and methods of forming the same
US9941216B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9812381B1 (en) 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9985006B2 (en) * 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11056436B2 (en) 2016-06-07 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out structure with rugged interconnect
US10354114B2 (en) 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US9812426B1 (en) 2016-06-29 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, semiconductor device, and method of fabricating the same
US9653391B1 (en) 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9793230B1 (en) 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10163800B2 (en) 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9824902B1 (en) 2016-07-12 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9661794B1 (en) 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
US9691708B1 (en) 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10062654B2 (en) 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US9799615B1 (en) 2016-07-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures having height-adjusted molding members and methods of forming the same
US10276506B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US9984960B2 (en) 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10276542B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10541226B2 (en) 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10163860B2 (en) 2016-07-29 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10134708B2 (en) 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10297551B2 (en) 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10658334B2 (en) 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
KR101982044B1 (ko) 2016-08-31 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10128182B2 (en) 2016-09-14 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9922896B1 (en) 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9837359B1 (en) 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9911672B1 (en) 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US10515899B2 (en) 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US20180102298A1 (en) * 2016-10-06 2018-04-12 Mediatek Inc. Semiconductor device
US10157846B2 (en) 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US10163801B2 (en) 2016-10-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US9837366B1 (en) 2016-11-28 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10692813B2 (en) 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US10128193B2 (en) 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10037963B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10304793B2 (en) 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163824B2 (en) 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180166419A1 (en) * 2016-12-12 2018-06-14 Nanya Technology Corporation Semiconductor package
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US9972581B1 (en) 2017-02-07 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Routing design of dummy metal cap and redistribution line
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
TWI618214B (zh) 2017-04-13 2018-03-11 力成科技股份有限公司 具有重佈線路層的晶片結構
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017012352B4 (de) 2017-06-30 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren mit einem Trennfilm als Isolierfilm im Gehäuse und Gehäuse
US10269589B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10475747B2 (en) * 2017-08-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10629540B2 (en) 2017-09-27 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN107785339A (zh) * 2017-10-13 2018-03-09 中芯长电半导体（江阴）有限公司 3d芯片封装结构及其制备方法
US10283377B1 (en) * 2017-11-07 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US10553533B2 (en) * 2017-11-08 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US20190148325A1 (en) * 2017-11-10 2019-05-16 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing the same
DE102018102086A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-packages und verfahren zu deren herstellung
US10784203B2 (en) 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11177201B2 (en) 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10529650B2 (en) 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10304716B1 (en) 2017-12-20 2019-05-28 Powertech Technology Inc. Package structure and manufacturing method thereof
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11488881B2 (en) 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11062915B2 (en) 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10665559B2 (en) * 2018-04-11 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Device, semiconductor package and method of manufacturing semiconductor package
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10631392B2 (en) 2018-04-30 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. EUV collector contamination prevention
US10790254B2 (en) * 2018-05-09 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
CN208638447U (zh) * 2018-06-29 2019-03-22 宁波舜宇光电信息有限公司 线路板组件、感光组件及摄像模组
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US11004803B2 (en) 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10573572B2 (en) * 2018-07-19 2020-02-25 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing a semiconductor package structure
US11289373B2 (en) * 2018-07-31 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11056459B2 (en) * 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10658348B2 (en) 2018-09-27 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having a plurality of first and second conductive strips
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
DE102019101999B4 (de) 2018-09-28 2021-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung mit mehreren polaritätsgruppen
US10861841B2 (en) 2018-09-28 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple polarity groups
US10665520B2 (en) 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11011451B2 (en) 2018-12-05 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11538735B2 (en) 2018-12-26 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit packages with mechanical braces
US10978382B2 (en) 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11107791B2 (en) * 2019-03-14 2021-08-31 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11145560B2 (en) 2019-04-30 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacturing
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11380620B2 (en) 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11004758B2 (en) 2019-06-17 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11133258B2 (en) 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11387191B2 (en) 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10879114B1 (en) 2019-08-23 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive fill
TWI759844B (zh) * 2019-10-09 2022-04-01 財團法人工業技術研究院 多晶片封裝件及其製造方法
US11587905B2 (en) 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11410968B2 (en) * 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
KR20210047607A (ko) 2019-10-22 2021-04-30 삼성전자주식회사 반도체 패키지
TWI713165B (zh) * 2019-11-25 2020-12-11 南茂科技股份有限公司 晶片封裝結構及其製造方法
US11227837B2 (en) 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant
US11227795B2 (en) 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
TWI720847B (zh) * 2020-03-17 2021-03-01 欣興電子股份有限公司 晶片封裝結構及其製作方法
US11393746B2 (en) 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11948930B2 (en) 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11552053B2 (en) 2020-06-25 2023-01-10 Apple Inc. Miniaturization of optical sensor modules through wirebonded ball stacks
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US11532524B2 (en) 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11652037B2 (en) 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
KR20220026809A (ko) 2020-08-26 2022-03-07 삼성전자주식회사 반도체 패키지
KR20220034596A (ko) 2020-09-11 2022-03-18 삼성전자주식회사 반도체 패키지
US11756871B2 (en) * 2020-09-15 2023-09-12 Sj Semiconductor (Jiangyin) Corporation Fan-out packaging structure and method
US11454888B2 (en) 2020-09-15 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11868047B2 (en) 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
KR20220067630A (ko) 2020-11-17 2022-05-25 삼성전자주식회사 반도체 패키지
US20220199535A1 (en) * 2020-12-18 2022-06-23 Intel Corporation Microelectronic structures including bridges
US20230106976A1 (en) * 2021-09-29 2023-04-06 Texas Instruments Incorporated Semiconductor die with solder restraining wall
US20230100769A1 (en) * 2021-09-29 2023-03-30 International Business Machines Corporation High density interconnection and wiring layers, package structures, and integration methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1806329A (zh) * 2003-06-19 2006-07-19 3M创新有限公司 包括含有填料以降低热膨胀系数的苯环丁烯的介电复合材料
CN101371355A (zh) * 2006-07-24 2009-02-18 揖斐电株式会社 中继基板和利用该中继基板的电子设备
US20090057862A1 (en) * 2007-08-31 2009-03-05 Jong-Woo Ha Integrated circuit package-in-package system with carrier interposer
US20100237482A1 (en) * 2009-03-20 2010-09-23 Joungin Yang Integrated circuit packaging system with layered packaging and method of manufacture thereof
US20110062592A1 (en) * 2009-09-11 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination Resistance of Stacked Dies in Die Saw
CN102169841A (zh) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 凹入的半导体基底和相关技术

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3882539B2 (ja) 2000-07-18 2007-02-21 ソニー株式会社 半導体発光素子およびその製造方法、並びに画像表示装置
TW511405B (en) * 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
TWI221336B (en) 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US20050205981A1 (en) 2004-03-18 2005-09-22 Kabushiki Kaisha Toshiba Stacked electronic part
TWI236721B (en) 2004-06-29 2005-07-21 Advanced Semiconductor Eng Leadframe for leadless flip-chip package and method for manufacturing the same
GB2418532A (en) 2004-09-28 2006-03-29 Arima Optoelectronic Textured light emitting diode structure with enhanced fill factor
WO2006035528A1 (ja) * 2004-09-29 2006-04-06 Murata Manufacturing Co., Ltd. スタックモジュール及びその製造方法
JP2009054970A (ja) 2007-08-29 2009-03-12 Shinko Electric Ind Co Ltd 半導体装置
US9922955B2 (en) 2010-03-04 2018-03-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP
US8357563B2 (en) 2010-08-10 2013-01-22 Spansion Llc Stitch bump stacking design for overall package size reduction for multiple stack
US8508045B2 (en) * 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8587120B2 (en) 2011-06-23 2013-11-19 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1806329A (zh) * 2003-06-19 2006-07-19 3M创新有限公司 包括含有填料以降低热膨胀系数的苯环丁烯的介电复合材料
CN101371355A (zh) * 2006-07-24 2009-02-18 揖斐电株式会社 中继基板和利用该中继基板的电子设备
US20090057862A1 (en) * 2007-08-31 2009-03-05 Jong-Woo Ha Integrated circuit package-in-package system with carrier interposer
US20100237482A1 (en) * 2009-03-20 2010-09-23 Joungin Yang Integrated circuit packaging system with layered packaging and method of manufacture thereof
US20110062592A1 (en) * 2009-09-11 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination Resistance of Stacked Dies in Die Saw
CN102024802A (zh) * 2009-09-11 2011-04-20 台湾积体电路制造股份有限公司 集成电路结构及其形成方法
CN102169841A (zh) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 凹入的半导体基底和相关技术

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104253111A (zh) * 2013-06-27 2014-12-31 英特尔公司 用于ic封装的硅空间转变器
CN104253111B (zh) * 2013-06-27 2018-05-01 英特尔公司 用于ic封装的硅空间转变器
US10056353B2 (en) 2013-12-19 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US11798916B2 (en) 2013-12-19 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10157891B2 (en) 2013-12-19 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10510729B2 (en) 2013-12-19 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US9941249B2 (en) 2014-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Multi-wafer stacking by Ox-Ox bonding
US10269768B2 (en) 2014-07-17 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
CN105321903A (zh) * 2014-07-17 2016-02-10 台湾积体电路制造股份有限公司 具有重分布线的堆叠集成电路
US11923338B2 (en) 2014-07-17 2024-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
CN105321903B (zh) * 2014-07-17 2018-12-14 台湾积体电路制造股份有限公司 具有重分布线的堆叠集成电路
US10629568B2 (en) 2014-07-17 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
CN105489580A (zh) * 2014-09-17 2016-04-13 日月光半导体制造股份有限公司 半导体衬底及半导体封装结构
US9984989B2 (en) 2014-09-17 2018-05-29 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and semiconductor package structure
CN104851816A (zh) * 2015-04-13 2015-08-19 华进半导体封装先导技术研发中心有限公司 一种多芯片高密度封装方法
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
US11133286B2 (en) 2015-09-30 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
CN106558565A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
US10483234B2 (en) 2015-09-30 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
CN105225965B (zh) * 2015-11-03 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型封装结构及其制作方法
CN105225965A (zh) * 2015-11-03 2016-01-06 中芯长电半导体（江阴）有限公司 一种扇出型封装结构及其制作方法
CN108352379B (zh) * 2015-12-21 2022-05-17 英特尔公司 系统级封装装置以及用于形成系统级封装装置的方法
CN108352379A (zh) * 2015-12-21 2018-07-31 英特尔Ip公司 系统级封装装置以及用于形成系统级封装装置的方法
CN106531710A (zh) * 2017-01-11 2017-03-22 中芯长电半导体（江阴）有限公司 一种集成供电系统的封装件及封装方法
CN106783649A (zh) * 2017-01-11 2017-05-31 中芯长电半导体（江阴）有限公司 一种集成供电系统封装件的封装方法
CN106684056A (zh) * 2017-03-22 2017-05-17 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装结构及其制备方法
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
US11887952B2 (en) 2017-03-30 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redistribution layer
US11417620B2 (en) 2017-03-30 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redestribution layer
CN107180766A (zh) * 2017-05-11 2017-09-19 王家恒 扇出型封装结构及其制作方法、终端设备
CN106981468A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
CN106981467A (zh) * 2017-05-15 2017-07-25 中芯长电半导体（江阴）有限公司 扇出型晶圆级封装结构及其制备方法
CN108962842A (zh) * 2017-05-26 2018-12-07 南茂科技股份有限公司 指纹识别芯片的封装结构及其制造方法
CN107146778A (zh) * 2017-06-30 2017-09-08 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN107195551A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 扇出型叠层封装结构及其制备方法
CN107195625A (zh) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 双面塑封扇出型系统级叠层封装结构及其制备方法
CN108109928A (zh) * 2017-12-29 2018-06-01 中芯长电半导体（江阴）有限公司 半导体芯片的封装结构及封装方法
CN110504172A (zh) * 2018-05-16 2019-11-26 中芯长电半导体（江阴）有限公司 垂直打线结构、堆叠芯片封装结构及方法
CN110783687A (zh) * 2018-07-30 2020-02-11 群创光电股份有限公司 封装结构与使用其的天线装置
CN112542451A (zh) * 2019-09-23 2021-03-23 苹果公司 用于集成专用集成电路和光学元件的嵌入式封装概念
CN112786540A (zh) * 2019-11-06 2021-05-11 富泰华工业（深圳）有限公司 扇出型封装结构及其制作方法
US11462481B2 (en) 2019-11-06 2022-10-04 Kore Semiconductor Co., Ltd. Fan-out packaging structure and method of making same
US11594571B2 (en) * 2020-02-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked image sensor device and method of forming same
US20210273013A1 (en) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked image sensor device and method of forming same
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CN115332088A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 一种基于中介层的封装及制作方法

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