CN105321903B - 具有重分布线的堆叠集成电路 - Google Patents

具有重分布线的堆叠集成电路 Download PDF

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Publication number
CN105321903B
CN105321903B CN201410844501.8A CN201410844501A CN105321903B CN 105321903 B CN105321903 B CN 105321903B CN 201410844501 A CN201410844501 A CN 201410844501A CN 105321903 B CN105321903 B CN 105321903B
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substrate
metal pad
dielectric layer
conductive plunger
opening
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CN105321903A (zh
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何承颖
林政贤
许文义
洪丰基
杨敦年
蔡映麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种集成电路结构，其包括第一和第二半导体芯片。第一半导体芯片包括第一衬底和位于第一衬底下面的多个第一介电层。第二半导体芯片包括第二衬底和位于第二衬底上方的多个第二介电层，其中多个第一介电层和多个第二介电层彼此接合。金属焊盘位于多个第二介电层中。重分布线位于第一衬底的上方。导电插塞电连接至重分布线。导电插塞包括从第一衬底的顶面延伸至第一衬底的底面的第一部分和从第一衬底的底面延伸至金属焊盘的第二部分。第二部分的底面接触金属焊盘的顶面。本发明涉及具有重分布线的堆叠集成电路。

Description

具有重分布线的堆叠集成电路
技术领域
本发明涉及具有重分布线的堆叠集成电路。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业已经经历了快速增长。在大多数情况下，集成密度的提高源自最小化部件尺寸的不断减小(例如，向着亚20nm节点缩小半导体工艺节点)，这允许更多的部件集成到给定的区域内。最近随着微型化、更高速和更大带宽以及更低功耗和低延迟的需求的增长，对更小且更有创意的半导体管芯的封装技术的需求也已增加。
随着半导体技术的进一步发展，已经出现了作为有效替代以进一步减少半导体器件的物理尺寸的的堆叠式半导体器件。在堆叠式半导体器件中，在不同的半导体晶圆上形成诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个以上的半导体晶圆可以安装在彼此的顶上以进一步减少半导体器件的形式因数。
两个半导体晶圆可以通过合适的接合技术接合在一起。常用的接合技术包括直接接合、化学活化接合、等离子体活化接合、阳极接合、共熔接合、玻璃融块接合、粘合接合、热压接合、反应接合等。一旦两个半导体晶圆接合在一起，两个半导体晶圆之间的界面可以提供堆叠式半导体晶圆之间的导电通路。
堆叠式半导体器件的有利特征是通过采用堆叠式半导体器件可以实现更高的密度。此外，堆叠半导体器件可以实现更小的形状因数、成本效益高、增加的性能以及较低的功耗。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种集成电路结构，包括：第一半导体芯片，其包括：第一衬底；多个第一介电层，位于所述第一衬底下面；和第二半导体芯片，其包括：第二衬底；多个第二介电层，位于所述第二衬底上方，其中，所述多个第一介电层的底层接合至所述多个第二介电层的顶层；和金属焊盘，位于所述多个第二介电层中的一层中；重分布线，位于所述第一衬底上方；第一导电插塞，位于所述重分布线的下面并且电连接至所述重分布线，其中，所述第一导电插塞包括：第一部分，从所述第一衬底的顶面延伸至所述第一衬底的底面；和第二部分，从所述第一衬底的底面延伸至所述金属焊盘，其中，所述第二部分的底面接触所述金属焊盘的顶面，并且所述第一部分和所述第二部分形成连接的区域。
在上述集成电路结构中，所述第一导电插塞包括从所述第一衬底的顶面延伸至所述第二半导体芯片内的均质材料，在所述均质材料中没有形成界面。
在上述集成电路结构中，进一步包括引线接合件，位于所述重分布线上方并且接合至所述重分布线。
在上述集成电路结构中，进一步包括所述第一衬底上方的介电层，其中，所述重分布线包括延伸至所述介电层内以接触所述第一导电插塞的通孔。
在上述集成电路结构中，所述第一半导体芯片进一步包括形成环形件的额外的金属焊盘，所述环形件中具有开口，并且所述第一导电插塞的第二部分进一步包括：第三部分，位于所述额外的金属焊盘上方；以及第四部分，穿透所述额外的金属焊盘以延伸至所述第二半导体芯片的金属焊盘。
在上述集成电路结构中，进一步包括双镶嵌结构，所述双镶嵌结构包括金属线和所述金属线下面的通孔，其中，所述双镶嵌结构使所述重分布线与所述第一导电插塞互连。
在上述集成电路结构中，所述第一导电插塞的第二部分包括从所述第一衬底的底面延伸至所述金属焊盘的基本上直的边缘。
在上述集成电路结构中，所述第一半导体芯片进一步包括：额外的金属焊盘，位于所述多个第一介电层中；以及第二导电插塞，从所述第一衬底的顶面延伸至所述额外的金属焊盘，其中，所述第二导电插塞停止在所述额外的金属焊盘的顶面上，并且所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
在上述集成电路结构中，所述第一半导体芯片进一步包括：额外的金属焊盘，位于所述多个第一介电层中；以及第二导电插塞，从所述第一衬底的顶面延伸至所述额外的金属焊盘，其中，所述第二导电插塞停止在所述额外的金属焊盘的顶面上，并且所述额外的金属焊盘将所述第一导电插塞物理连接至所述第二导电插塞。
根据本发明的另一方面，还提供了一种集成电路结构，包括：第一半导体芯片，包括：第一衬底；多个第一介电层；和第一金属焊盘，位于所述多个第一介电层中的一层中；第二半导体芯片，包括：第二衬底；多个第二介电层，位于所述第二衬底上方，其中，所述多个第一介电层的底层接合至所述多个第二介电层的顶层；和第二金属焊盘，位于所述多个第二介电层中的一层中；第一导电插塞，将所述第一金属焊盘电连接至所述第二金属焊盘，其中，所述第一导电插塞包括：第一部分，从所述第一衬底的顶面延伸至所述第一金属焊盘的顶面；和第二部分，从所述第一金属焊盘的顶面延伸至所述第二金属焊盘的顶面，其中，所述第二部分的边缘与所述第一金属焊盘的侧壁物理接触；以及重分布线，位于所述第一衬底上方，其中，所述重分布线电连接至所述第一导电插塞。
在上述集成电路结构中，所述第一导电插塞的第一部分进一步包括：第一子部分，位于所述第一衬底中；以及第二子部分，位于所述多个第一介电层中，其中，所述第一子部分的宽度大于所述第二子部分的宽度。
在上述集成电路结构中，所述第一导电插塞从所述第一衬底的顶面连续延伸至所述第二金属焊盘的顶面。
在上述集成电路结构中，所述第一导电插塞包括：导电阻挡件，从所述第一衬底的顶面延伸至所述第二金属焊盘的顶面；以及填充金属，由所述导电阻挡件环绕。
在上述集成电路结构中，进一步包括引线接合件，所述引线接合件位于所述重分布线上方并且接合至所述重分布线。
在上述集成电路结构中，所述第一半导体芯片进一步包括:第三金属焊盘，位于所述多个第一介电层中；以及第二导电插塞，从所述第一衬底的顶面延伸至所述第三金属焊盘，其中，所述第二导电插塞停止在所述第三金属焊盘的顶面上，并且所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
在上述集成电路结构中，所述第一半导体芯片进一步包括：第三金属焊盘，位于所述多个第一介电层中；以及第二导电插塞，从所述第一衬底的顶面延伸至所述第三金属焊盘，其中，所述第二导电插塞停止在所述第三金属焊盘的顶面上，并且所述第三金属焊盘将所述第一导电插塞物理连接至所述第二导电插塞。
根据本发明的又一方面，还提供了一种方法，包括：第一芯片接合至第二芯片，其中，所述第一芯片中的多个第一介电层接合至所述第二芯片中的多个第二介电层；在所述第一芯片的第一衬底中形成第一开口；穿过所述第一开口蚀刻所述多个第一介电层和所述多个第二介电层以形成第二开口，其中，所述多个第二介电层中的第一金属焊盘暴露于所述第二开口；填充导电材料以在所述第一开口和所述第二开口中形成第一导电插塞；和在所述第一衬底上方形成介电层；以及形成重分布线，所述重分布线包括位于所述介电层上方的一部分，其中，所述重分布线通过所述介电层中的开口电连接至所述第一导电插塞。
在上述方法中，进一步包括在重分布线上形成引线接合件。
在上述方法中，所述第二开口包括上部和下部，所述下部位于所述上部的下面并且连接至所述上部，并且所述第二开口的上部停止在所述多个第一介电层中的第二金属焊盘的顶面上，其中，所述第二开口的下部穿透所述第二金属焊盘，所述第二金属焊盘形成环绕所述第二开口的下部的环形件。
在上述方法中，进一步包括：当形成所述第一开口时，同时形成穿透所述第一衬底的第三开口；当形成所述第二开口时，同时形成位于所述第三开口下面并且连接至所述第三开口的第四开口，其中，通过所述第三开口和所述第四开口暴露出位于所述多个第一介电层中的第二金属焊盘的顶面；以及当实施填充导电材料以形成所述第一导电插塞时，同时填充所述第三开口和所述第四开口以形成第二导电插塞，其中，所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7示出了根据一些示例性实施例的包括堆叠管芯并且包括连接两个芯片的互连结构的封装件在形成中的中间阶段的截面图，其中使用了金属硬掩模；
图8和图9示出了根据一些其他实施例的包括堆叠管芯并且包括连接两个芯片的互连结构的封装件在形成的中间阶段的截面图，其中使用了金属硬掩模；
图10至图17示出了根据一些示例性实施例的包括堆叠管芯和连接两个芯片的互连结构的封装件在形成的中间阶段的截面图，其中未使用金属硬掩模；
图18和图19示出了根据一些其他实施例的包括堆叠管芯并且包括连接两个芯片的互连结构的封装件在形成的中间阶段的截面图，其中未使用金属硬掩模；以及
图20A至图20D示出了根据本发明的各个实施例的各个金属焊盘的顶视图，其中金属焊盘用于形成导电插塞。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，本文可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了包括堆叠管芯/芯片和使堆叠芯片互连的互连结构的封装件，以及其结构的形成方法。示出了形成互连结构的中间阶段。讨论了实施例的变化。贯穿各种视图和示例性实施例中，相似的参考标号用于指示相似的元件。
图1至7示出了根据一些实施例的RDL在接合和形成的中间阶段的截面图。图1示出了根据本发明的一些实施例的彼此接合的晶圆110和210的截面图。第一半导体晶圆110和第二半导体晶圆210均包括半导体衬底(例如，第一衬底102和第二衬底202)和在半导体衬底上方形成的多个互连结构(例如，金属焊盘106A、106B、108、206A、206B和208)。
如图1所示，第一半导体晶圆110可以包括第一衬底102和第一衬底102下面的多个金属间介电层104。此外，在每个介电层104中形成多条金属线(示意性地示出)，金属通孔和导电插塞(未示出)互连多条金属线。根据一些实施例，在金属间介电层104中形成金属焊盘106(包括106A和106B)。尽管图1示出了在介电层104的中间层中形成金属焊盘106，但是金属焊盘106可以在介电层104的任何层中。在介电层104中也形成金属焊盘108。根据一些实施例，在相同的金属层中形成金属焊盘106(包括106A和106B)和108。
第一衬底102可以由硅制成，但是它也可以由诸如硅、锗、镓、砷的其他的III族、IV族和/或V族元素或它们的组合形成。另外，可用的其他的衬底包括多层衬底、梯度衬底、混合取向衬底或它们的组合。
第一晶圆110和第二晶圆210可以进一步包括各种电路103和203(在图7中作为实例示出)。在第一衬底102上形成的电路103可以是适于特定应用的任何类型的电路。根据一些实施例，电路103可以包括各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件、电容器、电阻器、二极管、光二极管、熔丝等。
可以互连电路103以实施一种或多种功能。电路103可以包括存储器件、处理结构、传感器、放大器、电力分配器、输入/输出电路等。本领域的普通技术人员应当意识到，提供以上的实例是用于说明目的并不旨在将各种实施例限制在任何具体的应用中。
可以通过任何合适的形成工艺(例如，利用蚀刻的光刻、单镶嵌、双镶嵌等)制成金属焊盘106并且金属焊盘106可以使用诸如铜、铝、铝合金、铜合金等的合适的导电材料制成。图20A至图20D示出了金属焊盘106的一些示例性顶视图，示出了金属焊盘106形成具有开口的环形件。因此，每个金属焊盘106A和106B的两个示出的部分(图1)是集成的金属焊盘的部分。
如图1所示，第一半导体晶圆110堆叠在第二半导体晶圆210的顶上。半导体晶圆210也可以包括电路203(在图7中作为实例示出)，电路203可以具有所讨论的用于电路103的任何器件。例如，第一半导体晶圆110和第二半导体晶圆210通过诸如氧化物至氧化物接合的合适的接合技术接合在一起。根据一些实施例，在氧化物至氧化物的接合工艺中，半导体晶圆110和210的表层是氧化物层(例如，氧化硅)，其通过熔融接合彼此接合起来。
图2示出了在向下薄化和蚀刻第一衬底102之后的图1所示的半导体器件的截面图。在整个说明书中，背离晶圆210的第一衬底102的侧面称为第一衬底102的背侧。研磨第一衬底102的背侧从而去除第一衬底102的背部(在图1中用虚线所示)。产生的衬底102具有小于约5μm的厚度。
在薄化衬底102之后，可以通过合适的沉积或光刻技术在第一衬底102上方形成诸如光刻胶(未示出)的图案化的掩模。可以对第一半导体晶圆110的衬底102应用诸如反应离子蚀刻(RIE)或任何其他合适的各向异性蚀刻或图案化工艺的合适的蚀刻工艺。因此，在第一衬底102中形成多个通口114(包括114A和114B)和116。
图3示出了根据本发明的一些实施例的在半导体结构上方沉积介电层113之后的图2中所示的半导体器件的截面图。如图3所示，在开口114和116的底部和侧壁上形成介电层113。介电层113形成为共形层，共形层的水平部分和垂直部分具有彼此相近的厚度。
介电层113可以由可被用于集成电路制造的各种介电材料制成。例如，介电层113可以由二氧化硅、氮化硅、氮氧化硅、碳化硅等形成。此外，上述介电材料的组合也可以用于形成介电层113。根据一些实施例，使用诸如化学汽相沉积(CVD)方法或原子层沉积(ALD)的合适的技术形成介电层113。介电层113的厚度可以在从约至约的范围内。
图4示出了根据本发明的一些实施例的在半导体器件上方形成掩模117之后的图3所示的半导体器件的截面图。图案化的掩模117形成为延伸到开口114和116(图3所示)内。如图4所示，图案化的掩模117形成后，沿着开口114和116的侧壁形成开口118(包括118A和118B)和120。图案化的掩模117可以是光刻胶层。
图4也示出了根据本发明的各个实施例的对半导体器件应用蚀刻工艺之后的半导体器件的截面图。实施诸如干蚀刻的合适的蚀刻工艺以形成开口118和120。开口118和120是相应的重叠的开口114和116的延伸。
开口118的顶视尺寸等于或稍大于相应的下面的金属焊盘106中的开口的顶视尺寸。开口的形成经历了两个蚀刻阶段。在第一蚀刻阶段，蚀刻金属焊盘106上方的介电层104的部分，从而形成开口118A1和118B1。同时，开口120也同时形成。当金属焊盘106A、106B和108暴露时，结束第一蚀刻阶段。选择针对蚀刻金属焊盘106A、106B和108具有较低蚀刻率的蚀刻气体。相应地，金属焊盘106A、106B和108作为金属硬掩模以停止蚀刻工艺。尽管蚀刻率低，仍然可以部分地蚀刻掉金属焊盘106和108，从而在金属焊盘106和108的暴露的部分中形成凹槽。在金属焊盘106的蚀刻中，金属焊盘106中的金属原子可以溅射到介电层104的侧壁。因此，可以将凹槽502的深度控制的尽可能小以减少金属原子不期望地溅射到介电层104的侧壁上。
在第二蚀刻阶段，金属焊盘106和108的暴露部分作为蚀刻停止层以停止蚀刻。相应地，蚀刻停止于金属焊盘108。另一方面，穿过金属焊盘106A和106B中的开口继续蚀刻，并且蚀刻与金属焊盘106A和106B中的开口对准的介电层104和204。因此形成从晶圆110延伸到晶圆210内的开口118A2和118B2。当暴露出金属焊盘206(包括206A和206B)时，完成蚀刻，金属焊盘206作为第二蚀刻阶段的蚀刻停止层。蚀刻之后，去除图案化的掩模117。
图5示出了根据本发明的各个实施例的导电材料已填充到开口114、116、118和120中之后的截面图。因此，形成导电插塞122和124。由于导电插塞122穿透晶圆110，在下文中可选地将导电插塞122称为通孔。在一些实施例中，导电插塞122和124的形成包括形成共形的导电阻挡层123。在图7中的导电插塞122A中示意性地示出了导电阻挡123和上面的填充金属材料127，但是在其他实施例中它们也包括在所有其他的导电插塞122、124和125(例如，图6和图7)中。阻挡层123可以由钛、氮化钛、钽、氮化钽或它们的组合形成。在一些实施例中，导电阻挡层123是具有基本上均匀厚度的共形层，其可以使用诸如ALD、等离子体增强的化学汽相沉积(PECVD)等的合适的制造技术形成。
此外，在导电阻挡层123上方可以沉积晶种层(未示出)。晶种层可以由铜、镍、金、任何它们的组合等形成。可以通过诸如PVD、CVD等的合适的沉积技术形成晶种层。
一旦在开口中已沉积阻挡层123和晶种层，沉积金属材料127以填充开口114、116、118和120的剩余部分。金属材料可以包括钨、钛、铝、铜或它们的合金。在一些实施例中，可以通过电镀工艺在开口中填充金属材料。在填充金属材料之后，实施诸如化学机械抛光(CMP)的平坦化以去除金属材料的过量部分。金属材料127(和导电阻挡层123)从衬底102的顶面继续延伸到介电层204内，由于导电阻挡层123和金属材料12中的每个均在单个沉积步骤中由同质材料形成，因此在导电阻挡层123和金属材料127中不存在界面。
如图5所示，导电插塞124包括第一衬底102中的部分124A和介电层104中的部分124B。部分124A的宽度W1大于部分124B的宽度W2。导电插塞停止在金属焊盘108上。
又如图5所示，每个导电插塞122A和122B包括三个部分。第一部分从金属焊盘206延伸到金属焊盘106。如图5所示，第一部分(122A1/122B1)具有宽度W3。第二部分从金属焊盘106到第一衬底102的前侧。如图5所示，第二部分(122A2/122B2)具有宽度W4。第三部分(122A3/122B3)从第一衬底102的前侧延伸到第一衬底102的背侧。如图5所示，第三部分具有宽度W5。第一部分和可能地第二部分，可以物理接触相应的金属焊盘106的内侧壁。在一些实施例中，宽度W4大于或等于宽度W3，并且宽度W5大于宽度W4。每个导电插塞122A和122B的三个部分形成穿透晶圆110的连续的通孔，其中三个部分之间没有形成界面。
平坦化之后，形成蚀刻停止层126和介电层128。蚀刻停止层126可以包括氮化硅、氮氧化硅、碳氧化硅、碳化硅等。介电层128由不同于蚀刻停止层126的材料的材料形成，但是介电层128的材料也可以选自与蚀刻停止层126相同的候选材料。在一些示例性实施例中，蚀刻停止层126包括氮化硅，而介电层128包括氧化硅。根据一些实施例，介电层128的厚度在约和约之间的范围内。
参照图6，图案化介电层128和蚀刻停止层126，从而形成开口130(包括130A和130B)和132。分别通过开口130和132暴露出导电插塞122和124。
接下来，如图7所示，形成RDL 134(包括134A、134B和134C)。应当理解，除了图6中所示的部件外，图7也示出诸如导电插塞122C和125的额外的部件，其也在形成导电插塞122A、122B、124的同时形成。根据一些实施例，RDL 134由诸如铝铜、氧化铝、铜、镍、金、钨、钛、它们的合金或它们的多层的金属材料制成。形成工艺可以包括在图6的结构上方沉积诸如铜层的晶种层，在晶种层上方形成图案化的掩模层(诸如光刻胶，未示出)，电镀RDL 134，去除图案化的掩模层，并且去除晶种层的未被RDL 134覆盖的部分。
在后续的步骤中，将接合的晶圆110和210锯切为多个封装件310，每个封装件310都具有如图7所示相同的结构。如图中所示，封装件310包括来自晶圆110的芯片110’和来自晶圆210的芯片210’。可以在RDL焊盘134A2上实施引线接合。引线接合包括接合球136A和136B以及连接至相应的接合球136A和136B的金属线138A和138B。
根据本发明的实施例，导电插塞122A、122B和122C使器件与芯片110’和210’中的金属线互连。RDL 134A包括通孔134A1并且延伸至开口130A(图6)内和RDL焊盘134A2。此外，迹线部分134A3可以互连通孔134A1和RDL 134A2，并且通过导电插塞122A将引线接合件136A电连接至芯片110’和210’。RDL 134B用作路由线以路由芯片110’中的信号。例如，RDL134B可以用于在导电插塞122B和125之间电气地路由信号。在一些实施例中，在RDL 134B上不实施引线接合或倒装芯片接合。RDL134C连接至引线接合球136B和金属线138B。RDL 134C电连接至导电插塞124，导电插塞124停止在金属焊盘108并且不穿透芯片110’。通过金属焊盘108，RDL 134C进一步连接至导电插塞122C，导电插塞122C进一步使芯片110’和210’互连。因此，RDL 134A、134B和134C的形成提高了封装件310中的电信号的路由能力。
应当注意，虽然图7示出了堆叠在一起的两个半导体芯片，本领域普通技术人员应当意识到，图7所示的堆叠式半导体器件仅是实例。可以有许多替代、变型和改进。例如，堆叠式半导体器件可以容纳两个以上半导体芯片。
图8和9示出了根据本发明的可选实施例的堆叠芯片在形成的中间阶段的截面图。除非另有具体说明，否则在这些实施例中的部件的材料和形成方法与相似部件的材料和形成方法基本相同，这些实施例中的部件用与图1至图7所示的实施中相同的参考标号指示。因此，可以在图1至图7所示的实施例的讨论中找到关于图8和9(以及图10至图19)所示的部件的形成工艺和材料的细节。
这些实施例的初始阶段与图1至图5所示的基本相同。接下来，如图8所示，在介电层128中形成金属线140(其共同地形成金属层)和通孔142。可以使用双镶嵌工艺形成金属线140和通孔142，双镶嵌工艺包括在介电层128和蚀刻停止层126中形成沟槽和通孔开口和用金属材料填充沟槽和通孔开口以分别形成金属线140和通孔142。在可选实施例中，单镶嵌工艺可以用于形成金属线140和通孔142。可以形成一个层级以上的金属层。例如，图8示出了在介电层148中形成包括金属线144和相应的通孔146的额外的金属层。在金属线144上方形成蚀刻停止层150。
参照图9，形成RDL 134A、134B和134C以及引线接合件136A/138A和136B/138B。形成工艺和材料可以与图7所示的实施例相同，并且因此在此不重复。与图7中所示的实施例相类似，RDL 134A、134B和134C与导电插塞122A、122B、122C、124和125组合以路由芯片110’和210’之间的信号并且路由芯片110’内的信号。
图10至图17示出了根据本发明的可选实施例的堆叠芯片的形成。在这些实施例中，未形成如图7和图9所示的金属焊盘106。下文讨论简要的形成过程。
参照图10，使晶圆110和210彼此接合，随后薄化第一衬底102。虚线示意性地代表在薄化中去除的衬底102的部分。如图10所示，在晶圆210中形成金属焊盘206(包括206A和206B)。不同于图1中的实施例，在晶圆110中不形成与金属焊盘206重叠的金属焊盘。另一方面，在晶圆110的介电层104中的与金属焊盘206未对准的位置形成金属焊盘108。
参照图11，通过蚀刻薄化的衬底102来形成开口114(包括114A和114B)和116，从而暴露出下面的介电层104。接下来，如图12所示，在衬底102的背面和侧壁上形成介电层113。从而，使衬底102暴露的表面绝缘。
图13示出了掩模层117的形成，掩模层117掩蔽开口116(图12)，并且使得开口114A和114B的一些部分暴露。然后实施各向异性蚀刻步骤以蚀刻介电层113、104和一些部分的介电层204。实施蚀刻直到暴露出金属焊盘206。如图13所示，由于没有形成金属硬掩模(诸如图7和图9中的106)，产生的开口118(包括118A和118B)穿过介电层104一直延伸并且到晶圆210内。开口118A和118B在金属焊盘206上停止。然后去除掩模层117。
参照图14，形成并图案化掩模层152，掩模层152可以是光刻胶。掩模层152覆盖开口118A和118B(图13)并且保留衬底102中的开口116的中心部分暴露。然后实施各向异性蚀刻来蚀刻介电层104以形成开口120，各向异性蚀刻停止在金属焊盘108。在形成开口120后去除掩模层152。
如图13和图14所示，根据这些实施例，在光刻阶段而不是在形成开口120的阶段形成开口118A和118B。这部分是因为金属焊盘108远高于金属焊盘206，并且因此如果同时形成开口118A、118B和120，则金属焊盘108不能用作有效的蚀刻停止层。另外，金属焊盘108可能被不期望地蚀刻穿。
图15至图17所示的剩余的工艺步骤与图6和图7中的基本相同。如图17所示，形成导电插塞122(包括122A、122B和122C)、124、125，RDL 134(包括134A、134B和134C)和引线接合件136/138。图17示出了除了在图10至图16的步骤中所示的导电插塞和通孔之外的一些额外的导电插塞和通孔。然而，通过本发明的教导能够实现额外的导电插塞和通孔的结构和形成。
在图17中，每个导电插塞122A、122B和122C包括两部分，穿透衬底102的第一部分和穿透介电层104并进入介电层204内且一直到达金属焊盘206的第二部分。与图7和图9的实施例相类似，根据这些实施例，RDL 134可以用于连接至使芯片110’和210’互连的导电插塞122。此外，RDL 134可以用作接合焊盘。
图18和19示出了根据可选实施例的堆叠芯片在形成的中间阶段的截面图。除了在介电层128和148中形成包括金属线140和144以及通孔142和146的双镶嵌结构外，这些实施例与图10至图17中的实施例相类似。双镶嵌结构使RDL 134和下面的导电插塞122、124和125互连以提高封装件310的信号路由能力。剩下的部件与图17中的基本相同并且因此在此不讨论。
图20A至图20D示出了根据本发明的各个实施例的金属硬掩模(金属焊盘)106的各个顶视图。图20A示出了金属焊盘106为圆形形状，具有均为圆形的内边缘和外边缘。图20B示出了金属焊盘106的外边缘具有圆形的形状，而金属焊盘106的内边缘具有矩形(诸如方形)的形状。图20C示出了金属焊盘106是环形形状，具有均为圆形的内边缘和外边缘。图20D示出了金属焊盘106的外边缘具有圆形的形状，而金属焊盘106的内边缘具有矩形(诸如方形)的形状。
本发明的实施例有一些有利的特征。通过连续的导电插塞(例如图7、9、17和19中的导电插塞122)使封装件中的两个半导体芯片的有源电路彼此连接。这些连续的导电插塞帮助减小封装件的尺寸(footage)。此外，与通过包括多个部分的导电插塞连接的传统的堆叠式半导体器件相比，连接在两个半导体晶圆/管芯之间的连续的导电插塞帮助降低功耗并且防止寄生干扰。薄化的衬底也可以导致导电插塞的长度和间距的降低。
根据本发明的一些实施例，一种集成电路结构包括第一和第二半导体芯片。第一半导体芯片包括第一衬底和位于第一衬底下面的多个第一介电层。第二半导体芯片包括第二衬底和位于第二衬底上方的多个第二介电层，其中，多个第一介电层接合至多个第二介电层。金属焊盘位于多个第二介电层中。重分布线位于第一衬底上方。导电插塞位于重分布线的下面并且电连接至重分布线。导电插塞包括从第一衬底的顶面延伸至第一衬底的底面的第一部分和从第一衬底的底面延伸至金属焊盘的第二部分。第二部分的底面接触金属焊盘的顶面。第一部分和第二部分形成连续的区域。
根据本发明的可选实施例，一种集成电路结构包括第一半导体芯片和第二半导体芯片。第一半导体芯片包括第一衬底、多个第一介电层和位于多个第一介电层中的一层中的第一金属焊盘。第二半导体芯片包括第二衬底和位于第二衬底上方的多个第二介电层。多个第一介电层的底层结合至多个第二介电层的顶层。第二半导体芯片进一步包括位于多个第二介电层中的一层中的第二金属焊盘。导电插塞将第一金属焊盘电连接至第二金属焊盘。导电插塞包括从第一衬底的顶面延伸至第一金属焊盘的顶面的第一部分和从第一金属焊盘的顶面延伸至第二金属焊盘的顶面的第二部分。第二部分的边缘与第一金属焊盘的侧壁物理接触。重分布线位于第一衬底的上方，其中重分布线电连接至导电插塞。
根据本发明的又一些可选实施例，一种方法包括：将第一芯片接合至第二芯片，其中，将第一芯片中的多个第一介电层接合至第二芯片中的多个第二介电层。在第一芯片的第一衬底中形成第一开口。穿过第一开口蚀刻多个第一介电层和多个第二介电层以形成第二开口。多个第二介电层中的金属焊盘暴露于第二开口。填充导电材料以在第一开口和第二开口中形成导电插塞。在第一衬底的上方形成介电层。形成重分布线。重分布线包括位于介电层上方的一部分。通过介电层中的开口将重分布线电连接至导电插塞。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种集成电路结构，包括：
第一半导体芯片，包括：
第一衬底，由半导体材料形成；
多个第一介电层，位于所述第一衬底下面；
介电层，具有与所述第一衬底的顶面共面的顶端以及与所述第一衬底的底面共面的底端；和
第二半导体芯片，包括：
第二衬底；
多个第二介电层，位于所述第二衬底上方，其中，所述多个第一介电层的底层接合至所述多个第二介电层的顶层；和
金属焊盘，位于所述多个第二介电层中的一层中；
重分布线，位于所述第一衬底上方；
第一导电插塞，位于所述重分布线的下面并且电连接至所述重分布线，其中，所述第一导电插塞包括：
第一部分，从所述第一衬底的半导体材料的顶面延伸至所述第一衬底的半导体材料的底面，其中，所述介电层环绕所述第一部分并且与所述第一部分接触；和
第二部分，从所述第一衬底的半导体材料的底面延伸至所述金属焊盘，其中，所述第二部分的底面接触所述金属焊盘的顶面，并且所述第一部分和所述第二部分形成连接的区域，其中，所述第一部分的宽度大于所述第二部分的宽度。
2.根据权利要求1所述的集成电路结构，其中，所述第一导电插塞包括从所述第一衬底的顶面延伸至所述第二半导体芯片内的均质材料，在所述均质材料中没有形成界面。
3.根据权利要求1所述的集成电路结构，进一步包括引线接合件，位于所述重分布线上方并且接合至所述重分布线。
4.根据权利要求1所述的集成电路结构，进一步包括所述第一衬底上方的介电层，其中，所述重分布线包括延伸至所述介电层内以接触所述第一导电插塞的通孔。
5.根据权利要求1所述的集成电路结构，其中，所述第一半导体芯片进一步包括形成环形件的额外的金属焊盘，所述环形件中具有开口，并且所述第一导电插塞的第二部分进一步包括：
第三部分，位于所述额外的金属焊盘上方；以及
第四部分，穿透所述额外的金属焊盘以延伸至所述第二半导体芯片的金属焊盘。
6.根据权利要求1所述的集成电路结构，进一步包括双镶嵌结构，所述双镶嵌结构包括金属线和所述金属线下面的通孔，其中，所述双镶嵌结构使所述重分布线与所述第一导电插塞互连。
7.根据权利要求1所述的集成电路结构，其中，所述第一导电插塞的第二部分包括从所述第一衬底的底面延伸至所述金属焊盘的直的边缘。
8.根据权利要求1所述的集成电路结构，其中，所述第一半导体芯片进一步包括：
额外的金属焊盘，位于所述多个第一介电层中；以及
第二导电插塞，从所述第一衬底的顶面延伸至所述额外的金属焊盘，其中，所述第二导电插塞停止在所述额外的金属焊盘的顶面上，并且所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
9.根据权利要求1所述的集成电路结构，其中，所述第一半导体芯片进一步包括：
额外的金属焊盘，位于所述多个第一介电层中；以及
第二导电插塞，从所述第一衬底的顶面延伸至所述额外的金属焊盘，其中，所述第二导电插塞停止在所述额外的金属焊盘的顶面上，并且所述额外的金属焊盘将所述第一导电插塞物理连接至所述第二导电插塞。
10.一种集成电路结构，包括：
第一半导体芯片，包括：
第一衬底；
多个第一介电层；和
第一金属焊盘，位于所述多个第一介电层中的一层中；
介电层，具有与所述第一衬底的顶面共面的顶端以及与所述第一衬底的底面共面的底端；
第二半导体芯片，包括：
第二衬底；
多个第二介电层，位于所述第二衬底上方，其中，所述多个第一介电层的底层接合至所述多个第二介电层的顶层；和
第二金属焊盘，位于所述多个第二介电层中的一层中；
第一导电插塞，将所述第一金属焊盘电连接至所述第二金属焊盘，其中，所述第一导电插塞包括：
第一部分，包括：
第一子部分，从所述第一衬底的半导体材料的顶面延伸至所述第一衬底的半导体材料的底面，其中，所述介电层环绕所述第一子部分并且与所述第一子部分接触；
第二子部分，与所述第一子部分直接接触，其中，所述第二子部分从所述第一衬底的半导体材料的底面延伸至所述第一金属焊盘的顶面，其中，所述第一子部分的宽度大于所述第二子部分的宽度；和
第二部分，从所述第一金属焊盘的顶面延伸至所述第二金属焊盘的顶面，其中，所述第二部分的边缘与所述第一金属焊盘的侧壁物理接触，其中，所述第二子部分的宽度大于所述第二部分的宽度；以及
重分布线，位于所述第一衬底上方，其中，所述重分布线电连接至所述第一导电插塞。
11.根据权利要求10所述的集成电路结构，其中，所述第一导电插塞从所述第一衬底的顶面连续延伸至所述第二金属焊盘的顶面。
12.根据权利要求10所述的集成电路结构，其中，所述第一导电插塞包括：
导电阻挡件，从所述第一衬底的顶面延伸至所述第二金属焊盘的顶面；以及
填充金属，由所述导电阻挡件环绕。
13.根据权利要求10所述的集成电路结构，进一步包括引线接合件，所述引线接合件位于所述重分布线上方并且接合至所述重分布线。
14.根据权利要求10所述的集成电路结构，其中，所述第一半导体芯片进一步包括:
第三金属焊盘，位于所述多个第一介电层中；以及
第二导电插塞，从所述第一衬底的顶面延伸至所述第三金属焊盘，其中，所述第二导电插塞停止在所述第三金属焊盘的顶面上，并且所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
15.根据权利要求10所述的集成电路结构，其中，所述第一半导体芯片进一步包括：
第三金属焊盘，位于所述多个第一介电层中；以及
第二导电插塞，从所述第一衬底的顶面延伸至所述第三金属焊盘，其中，所述第二导电插塞停止在所述第三金属焊盘的顶面上，并且所述第三金属焊盘将所述第一导电插塞物理连接至所述第二导电插塞。
16.一种形成集成电路结构的方法，包括：
第一芯片接合至第二芯片，其中，所述第一芯片中的多个第一介电层接合至所述第二芯片中的多个第二介电层；
在所述第一芯片的第一衬底中形成第一开口；
在所述第一开口的底部和侧壁上形成介电层；
穿过所述第一开口蚀刻所述介电层、所述多个第一介电层和所述多个第二介电层以形成第二开口，其中，所述多个第二介电层中的第一金属焊盘暴露于所述第二开口；
填充导电材料以在所述第一开口和所述第二开口中形成第一导电插塞，其中，所述第一导电插塞包括：第一部分，从所述第一衬底的半导体材料的顶面延伸至所述第一衬底的半导体材料的底面，其中，所述介电层环绕所述第一部分并且与所述第一部分接触；和第二部分，从所述第一衬底的半导体材料的底面延伸至所述第一金属焊盘，其中，所述第二部分的底面接触所述第一金属焊盘的顶面，其中，所述第一部分的宽度大于所述第二部分的宽度；
在所述第一衬底上方形成介电层；以及
形成重分布线，所述重分布线包括位于所述介电层上方的一部分，其中，所述重分布线通过所述介电层中的开口电连接至所述第一导电插塞。
17.根据权利要求16所述的方法，进一步包括在重分布线上形成引线接合件。
18.根据权利要求16所述的方法，其中，所述第二开口包括上部和下部，所述下部位于所述上部的下面并且连接至所述上部，并且所述第二开口的上部停止在所述多个第一介电层中的第二金属焊盘的顶面上，其中，所述第二开口的下部穿透所述第二金属焊盘，所述第二金属焊盘形成环绕所述第二开口的下部的环形件。
19.根据权利要求16所述的方法，进一步包括：
当形成所述第一开口时，同时形成穿透所述第一衬底的第三开口；
当形成所述第二开口时，同时形成位于所述第三开口下面并且连接至所述第三开口的第四开口，其中，通过所述第三开口和所述第四开口暴露出位于所述多个第一介电层中的第二金属焊盘的顶面；以及
当实施填充导电材料以形成所述第一导电插塞时，同时填充所述第三开口和所述第四开口以形成第二导电插塞，其中，所述重分布线将所述第一导电插塞电连接至所述第二导电插塞。
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