TWI553824B - 具有再分配線的堆疊式積體電路以及其形成方法 - Google Patents

具有再分配線的堆疊式積體電路以及其形成方法 Download PDF

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TWI553824B
TWI553824B TW103138143A TW103138143A TWI553824B TW I553824 B TWI553824 B TW I553824B TW 103138143 A TW103138143 A TW 103138143A TW 103138143 A TW103138143 A TW 103138143A TW I553824 B TWI553824 B TW I553824B
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Taiwan
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substrate
metal pad
opening
conductive plug
dielectric layers
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TW103138143A
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TW201605012A (zh
Inventor
何承穎
林政賢
許文義
洪豐基
楊敦年
蔡映麟
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台灣積體電路製造股份有限公司
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Description

具有再分配線的堆疊式積體電路以及其形成方法
本揭露涉及具有再分配線的堆疊式積體電路。
由於各種電子元件(例如，電晶體、二極體、電阻、電容等)集成密度的持續改進，半導體工業經歷了快速發展。在很大程度上，這種集成密度的改進來自不斷減少最小特徵尺寸(例如，將半導體工藝節點收縮至亞20nm節點)，從而允許在給定的區域集成更多的元件。隨著近來對小型化、更高速度和更大帶寬以及更低功率消耗和延遲的需求之增長，更小和更具創造性的半導體晶粒封裝技術的需要也已增加。
隨著半導體技術的進一步發展，作為一種有效替換，堆疊式半導體裝置已經出現，以進一步減少半導體裝置的物理尺寸。在堆疊式半導體裝置中，在不同的半導體晶圓上形成有源電路，如邏輯電路、存儲器、處理器電路等。兩個或更複數個半導體晶圓安置在另一個晶圓之上以進一步減少半導體裝置的形狀係數。
兩個半導體晶圓可通過合適的結合技術結合在一起。通常使用的結合技術包括直接結合、化學活化結合、電漿活化結合、陽極結 合、共晶結合、玻璃粉結合、粘接、熱壓縮結合、反應結合和/或其他。一旦兩個半導體晶圓結合在一起，這兩個半導體晶圓之間的交界面可提供堆疊式半導體裝置晶圓之間的導電通路。
堆疊式半導體裝置之優勢特點是：通過使用堆疊式半導體裝置可實現高得多的密度。而且，堆疊式半導體裝置可實現更小的形狀係數、高成本效益、提升的性能和更低的功耗。
根據本發明的一些實施例，積體電路結構包括第一半導體晶圓和第二半導體晶圓。第一半導體晶圓包括第一基底和在第一基底下面的第一複數個介電層。第二半導體晶圓包括第二基底和在第二基底之上的第二複數個介電層，其中第一複數個介電層結合到第二複數個介電層。金屬墊在第二複數個介電層中。再分配線在第一基底之上。導電插塞在再分配線的下面並電耦合到該再分配線。導電插塞包括自第一基底的頂表面延伸至第一基底的底表面的第一部分以及自第一基底的底表面延伸至金屬墊的第二部分。第二部分的底表面接觸金屬墊的頂表面。第一部分和第二部分形成連續區域。
根據本發明之可替換實施例，積體電路結構包括第一半導體晶圓和第二半導體晶圓。第一半導體晶圓包括第一基底、第一複數個介電層和在第一複數個介電層的一層中的第一金屬墊。第二半導體晶圓包括第二基底和第二基底之上的第二複數個介電層。第一複數個介電層的底層結合到第二複數個介電層的頂層。第二半導體晶圓進一步包括在第二複數個介電層的一層中的第二金屬墊。導電插塞將第一金屬墊電耦合到第二金屬墊。導電插塞包括自第一基底的頂表面延伸至第一金屬墊的頂表面的第一部分，以及自第一金屬墊的頂表面延伸至第二金屬墊的頂表面的第二部分。第二部分的邊緣與第一金屬墊的側 壁實質地接觸。再分配線在第一基底之上，其中該再分配線電耦合到導電插塞。
根據本發明之又一可替換實施例，一種方法包括：將第一晶片結合到第二晶片，其中第一晶片中的第一複數個介電層結合到第二晶片中的第二複數個介電層。在第一晶片的第一基底形成第一貫通開口。通過第一開口蝕刻第一複數個介電層以及第二複數個介電層以形成第二開口。第二複數個介電層的金屬墊暴露於第二開口。填充導電材料以在第一開口和第二開口形成導電插塞。在該第一基底之上形成介電層。形成再分配線。該再分配線包括在介電層之上的部分。該再分配線通過介電層中的開口電耦合到導電插塞。
102‧‧‧第一基底
103‧‧‧電子電路
104‧‧‧金屬間介電層
106‧‧‧金屬墊
106A‧‧‧金屬墊
106B‧‧‧金屬墊
108‧‧‧金屬墊
110‧‧‧半導體晶圓
110'‧‧‧晶片
113‧‧‧介電層
114‧‧‧開口
114A‧‧‧開口
116‧‧‧開口
117‧‧‧掩模
118‧‧‧開口
118A‧‧‧開口
118A1‧‧‧開口
118A2‧‧‧開口
118B‧‧‧開口
118B1‧‧‧開口
118B2‧‧‧開口
120‧‧‧開口
122‧‧‧導電插塞
122A‧‧‧導電插塞
122A1‧‧‧導電插塞的第一部分
122A2‧‧‧導電插塞的第二部分
122A3‧‧‧導電插塞的第三部分
122B‧‧‧導電插塞
122B1‧‧‧導電插塞的第一部分
122B2‧‧‧導電插塞的第二部分
122B3‧‧‧導電插塞的第三部分
122C‧‧‧導電插塞
123‧‧‧導電阻擋層
124‧‧‧導電插塞
124A‧‧‧導電插塞的部分
124B‧‧‧介電層的部分
126‧‧‧蝕刻阻止層
127‧‧‧金屬材料
128‧‧‧介電層
130‧‧‧開口
130A‧‧‧開口
130B‧‧‧開口
132‧‧‧開口
134‧‧‧再分配線(RDL)
134A‧‧‧再分配線(RDL)
134A1‧‧‧通孔
134A2‧‧‧RDL墊
134A3‧‧‧痕跡部分
134B‧‧‧RDL
134C‧‧‧RDL
136A‧‧‧結合球
136B‧‧‧結合球
138A‧‧‧金屬線
138B‧‧‧金屬線
140‧‧‧金屬線
142‧‧‧通孔
144‧‧‧金屬線
146‧‧‧通孔
148‧‧‧介電層
150‧‧‧蝕刻阻止層
152‧‧‧掩模層
202‧‧‧第二基底
204‧‧‧金屬間介電層
206‧‧‧金屬墊
206A‧‧‧金屬墊
206B‧‧‧金屬墊
210‧‧‧晶圓
210'‧‧‧晶圓
310‧‧‧封裝件
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
W4‧‧‧寬度
W5‧‧‧寬度
當閱讀隨附的附圖時，從以下詳細的描述可以最清楚地理解本發明的各個方面。需要強調的是，根據本行業的標準做法，不是按比例繪製各個特徵。事實上，各個特徵的尺寸可以任意增大或減小以便進行清楚的討論。
圖1到圖7是根據一些示例性實施例的形成封裝件的中間階段的截面圖，該封裝件包括堆疊式晶粒並包括連接兩個晶片的互聯結構，其中使用金屬硬掩模；圖8和圖9是根據另一些實施例的形成封裝件的中間階段的截面圖，該封裝件包括堆疊式晶粒並包括連接兩個晶片的互聯結構，其中使用金屬硬掩模；圖10到圖17是根據一些示例性實施例的形成封裝件的中間階段的截面圖，該封裝件包括堆疊式晶粒並包括連接兩個晶片的互聯結構，其中未使用金屬硬掩模；圖18和圖19是根據另一些實施例的形成封裝件的中間階段的截 面圖，該封裝件包括堆疊式晶粒並包括連接兩個晶片的互聯結構，其中未使用金屬硬掩模；以及圖20A到圖20D是根據本發明各種實施例的各種金屬墊的俯視圖，其中該金屬墊用來形成導電插塞。
如下公開提供了很多不同的實施例或示例，用於實施本發明的不同特徵。如下描述了元件和佈置的具體示例，以簡化本發明。當然，它們僅僅是示例，並不是旨在限制本發明。例如，以下描述中在第二特徵之上或在第二特徵上形成第一特徵可以包括形成直接接觸的第一特徵和第二特徵的實施例，還可以包括在第一特徵和第二特徵之間可以形成附加特徵從而使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本公開可以在各個示例中重複使用附圖標記和/或字母。這種重複使用用於簡化和清楚的目的，其本身並不表明所述的各個實施例和/或配置之間的關係。
而且，空間關係術語，例如“之下”、“下方”、“下面”、“之上”、“上方”等，在此用於簡化描述附圖所示的一個單元和特徵對另一個單元或特徵的關係。除了附圖中描寫的方向，空間關係術語旨在包含使用或操作的裝置的不同方向。設備可以以其他方式定向(旋轉90度或者在其他方向)，並可以據此同樣地解釋本文所使用的空間關係描述語。
根據各種示例性實施例提供包括堆疊式晶粒/晶片和將堆疊式晶片互聯的互聯結構之封裝件及其形成方法。示出了形成互聯結構的中間階段。討論實施例的各種變形。貫穿各種示圖和說明性實施例，類似的參考編號用來指明類似的元件。
圖1至圖7是根據一些實施例的結合和形成再分配線 (Redistribution Lines，RDL)的中間階段的截面圖。圖1是根據本發明一些實施例的晶圓110和210彼此結合的截面圖。第一半導體晶圓110和第二半導體晶圓210都包括半導體基底(例如，第一基底102和第二基底202)以及在半導體基底上形成的複數個互聯結構(例如，金屬墊106A、106B、108、206A、206B和208)。
如圖1所示，第一半導體晶圓110包括第一基底102和位於第一基底102之下的複數個金屬間介電層104。此外，在每個介電層104中形成複數個金屬線(示意性示出)，金屬通孔和導電插塞(未示出)互聯複數個金屬線。根據一些實施例，金屬墊106(包括106A和106B)在金屬間介電層104中形成。儘管圖1示出金屬墊106在金屬間介電層104的中間層中形成，但是金屬墊106可在金屬間介電層104的任意一層中形成。金屬墊108也可在介電層104中形成。根據一些實施例，金屬墊106(包括106A和106B)和108在相同金屬層中形成。
第一基底102可由矽形成，儘管它也可由其他第III族、第IV族和第V族元素形成，例如矽、鍺、鎵、砷或其組合。而且，可使用的其他基底包括多層基底、梯度基底、混合取向基底，或它們的組合。
第一晶圓110和第二晶圓210可進一步包括各種電子電路103和203(以圖7所示為例)。在第一基底102上形成的電子電路103可以是適合特定應用的任意類型的電路。根據一些實施例，電子電路103可包括各種N型金屬-氧化物-半導體(NMOS)和/或P型金屬-氧化物-半導體(PMOS)裝置、電容、電阻、二極體、光電二極體、熔絲和/或諸如此類。
電子電路103可互聯以執行一個或複數個功能。電子電路103可包括記憶體裝置、處理結構、感測器、放大器、功率分配器、輸入/輸出電路和/或諸如此類。本領域普通技術人員會理解上面的例子是用於說明性的目的，而並不是旨在將各種實施例限制於任一特定應 用。
可通過任一合適的形成工藝(例如，利用蝕刻的平版印刷術、單鑲嵌、雙鑲嵌等)製作金屬墊106，並可使用合適的導電材料(例如，銅、鋁、鋁合金、銅合金等)形成金屬墊106。圖20A到圖20D示出了金屬墊106的一些示例性俯視圖，其示出了金屬墊106形成具有開口的環。因此，金屬墊106A和106B每一者的兩個示例性部分(圖1)是集成之金屬墊的部分。
如圖1所示，第一半導體晶圓110堆疊在第二半導體晶圓210之上。半導體晶圓210也可包括電路203(以圖7所示為例)，其可具有針對電路103討論的任何裝置。第一半導體晶圓110和第二半導體晶圓210通過合適的結合技術(例如，氧化物到氧化物的結合)結合在一起。根據一些實施例，在氧化物到氧化物結合過程中，半導體晶圓110和210的表面層是氧化層(例如，二氧化矽)，其通過熔融結合彼此結合在一起。
圖2示出了在薄化和蝕刻第一基底102後圖1所示的半導體裝置的截面圖。在本文的整個描述中，第一基底102背對晶圓210的一面被稱為基底102的背面。基底102的背面被磨薄從而去除第一基底102的後面部分(在圖1用虛線示出)。最終的基底102之厚度小於大約5μm。
在薄化基底102後，使用合適的沉積和光刻技術在第一基底102上形成諸如光阻(未示出)的圖案化掩模。合適的蝕刻工藝，例如反應離子蝕刻(RIE)或任何其他合適的各向異性蝕刻或圖案化形成工藝，可應用於第一半導體晶圓110的基底102。這樣，在第一基底102中形成複數個貫通開口104(包括114A和114B)和116。
圖3是根據本發明之各種實施例的在半導體結構上沉積介電層113之後圖2所示的半導體裝置的截面圖。如圖3所示，開口114和116的底部和側壁上形成介電層113。介電層113作為共形層而形成，該共形層 的水平部分和垂直部分的厚度彼此接近。
可由積體電路製造中使用的各種介電材料來形成介電層113。例如，可由二氧化矽、氮化矽、氧氮化矽、碳化矽等來形成介電層113。此外，前述介電材料的組合也可用來形成介電層113。根據一些實施例，可使用諸如化學氣相沉積(CVD)方法或原子層沉積(ALD)之合適技術來形成介電層113。介電層113的厚度可在大約1kÅ至大約3kÅ的範圍內。
圖4是根據本發明之各種實施例在半導體裝置上形成掩模117層後，圖3所示的半導體裝置之截面圖。圖案化掩模117延伸至開口114和116(如圖3所示)。如圖4所示，在圖案化掩模117沿開口114和116的側壁形成之後，形成開口118(包括118A和118B)和120。圖案化掩模117可以是光阻層。
圖4也示出根據本發明之各種實施例的在蝕刻過程應用於半導體裝置之後，半導體裝置的截面圖。執行合適的蝕刻過程(例如，乾蝕刻)以形成開口118和120。開口118和120分別是開口114和116上疊加的延伸部分。
開口118的俯視尺寸等於或略微大於位於金屬墊106之下的相應開口的俯視尺寸。開口的形成歷經兩個蝕刻階段。在第一個蝕刻階段，蝕刻金屬墊106上的介電層104的部分，形成開口118A1和118B1。在此期間，開口120也同時形成。第一蝕刻階段結束於暴露金屬墊106A、106B和108時。選擇具有很低蝕刻速率之腐蝕氣體來蝕刻金屬墊106A、106B和108。因此，金屬墊106A、106B和108起著金屬硬掩模的作用來阻止蝕刻過程。儘管蝕刻速率很低，金屬墊106和108仍然被部分地蝕刻掉，從而在金屬墊106和108的暴露部分形成凹槽。在蝕刻金屬墊106的過程中，金屬墊106中的金屬原子可濺射到介電層104的側壁。因此，凹槽502的深度被控制得儘量小，以減少不需要的金 屬原子濺射到介電層104的側壁。
在第二蝕刻階段，金屬墊106和108的暴露部分作為蝕刻阻止層來阻止蝕刻。因此，蝕刻在金屬墊108處終止。另一方面，通過金屬墊106A和106B的開口繼續蝕刻，且蝕刻對準金屬墊106A和106B的開口的介電層104和204。開口118A2和118B2因此形成，從晶圓110延伸至晶圓210。當暴露金屬墊206(包括206A和206B)時蝕刻結束，金屬墊206作為第二蝕刻階段的蝕刻阻止層。在蝕刻之後，去除圖案化掩模117。
圖5示出根據本發明各種實施例的導電材料已被填入開口114、116、118和120之後的截面圖。從而，形成了導電插塞122和124。因為導電插塞122穿透晶圓110，其在下文中還可稱為貫通孔。在一些實施例中，導電插塞122和124的形成包括形成共形導電阻擋層123。導電阻擋層123和上面覆蓋的填充金屬材料127示意性地示出在圖7的導電插塞122A中，儘管在其他實施例中它們也可包含在所有其他導電插塞122、124和125中(例如，圖6和圖7)。可由鈦、氮化鈦、鉭、氮化鉭或它們的組合形成阻擋層123。在一些實施例中，導電阻擋層123是厚度大體上均勻的共形層，其可以使用合適的製造技術(例如，ALD、電漿增強化學氣相沉積(PECVD)等)而形成。
此外，種晶層(未示出)可在導電阻擋層123上沉積。種晶層可由銅、鎳、金、及其任意組合和/或諸如此類而形成。種晶層可通過合適的沉積技術而形成，例如，PVD、CVD和/或諸如此類的。
一旦阻擋層123和種晶層在開口沉積，就沉積金屬材料127來填充開口114、116、118和120其餘的開口。金屬材料可包括鎢、鈦、鋁、銅或它們的合金。在一些實施例中，可通過電鍍過程填充金屬材料至開口。在填充金屬材料後，執行諸如化學機械拋光(CMP)的平坦化技術來去除金屬材料的過多部分。金屬材料127(以及導電阻擋層 123)不斷地自基底102的頂表面延伸至介電層204，其中沒有形成交介面，這是因為由同質材料形成的導電阻擋層123和金屬材料127的每一者是在單個沉積步驟中形成的。
如圖5所示，導電插塞124包括第一基底102中的部分124A和介電層104中的部分124B。部分124A的寬度W1大於部分124B的寬度W2。導電插塞124在金屬墊108處終止。
仍然如圖5所示，導電插塞122A和122B的每一者均包括三個部分。第一部分自金屬墊206延伸至金屬墊106。如圖5所示，第一部分(122A1/122B1)具有寬度W3。第二部分自金屬墊106至第一基底102的正面。如圖5所示，第二部分(122A2/122B2)具有寬度W4。第三部分(122A3/122B3)自第一基底102的正面延伸至第一基底102的背面。如圖5所示，第三部分具有寬度W5。第一部分，也可能是第二部分，可實質地接觸各自金屬墊106的內側壁。在一些實施例中，寬度W4大於或等於寬度W3，而寬度W5大於寬度W4。導電插塞122A和122B的每一者的三個部分形成穿透晶圓110的連續通孔，其中這三個部分之間沒有形成交介面。
在平坦化處理後，形成蝕刻阻止層126和介電層128。蝕刻阻止層126可包括氮化矽、氧氮化矽、矽碳氧化物、碳化矽等。儘管用於介電層128的材料也可從與蝕刻阻止層126相同的備選材料中選擇，但介電層128由與蝕刻阻止層126的材料不同之材料形成。在一些示例性實施例中，蝕刻阻止層126包括氮化矽，而介電層128包括二氧化矽。根據一些實施例，介電層128的厚度在大約4kÅ至大約12kÅ的範圍內。在平坦化處理後，介電層113具有與第一基底102之頂表面共平面之上端以及與第一基底102之底表面共平面之下端，且介電層113環繞並接觸導電插塞122A和122B的一部分，例如上述之自第一基底102的正面延伸至第一基底102的背面的第三部分(122A3/122B3)。
參照圖6，圖案化介電層128和蝕刻阻止層126，從而形成開口130(包括130A和130B)和132。導電插塞122和124分別通過開口130和132而暴露。
接下來，如圖7所示，形成RDL 134(包括134A、134B和134C)。可以看出，除了在圖6中示出的特徵，圖7還示出了諸如導電插塞122C和125的附加特徵，這些附加特徵與導電插塞122A、122B和124同時形成。根據一些實施例，RDL 134由金屬材料形成，如鋁銅、鋁、銅、鎳、金、鎢、鈦，它們的合金，或它們的多層。形成過程可包括在圖6的結構上沉積種晶層(例如，銅層)，在種晶層上形成圖案化掩模層(例如光阻，未示出)，電鍍RDL 134，去除圖案化掩模層並去除未被RDL 134覆蓋的種晶層部分。
在隨後的步驟中，結合的晶圓110和210被切割成複數個封裝件310中，每一個具有如圖7所示的相同結構。如圖所示，封裝件310包括來自晶圓110的晶片110’和來自晶圓210的晶片210’。在RDL墊134A2上執行焊線。焊線包括結合球136A和136B以及連接到各自結合球136A和136B的金屬線138A和138B。
根據本發明的實施例，導電插塞122A、122B和122C使裝置和晶片110’和210’的金屬線互聯。RDL 134A包括通孔134A1並延伸至開口130A(圖6)和RDL墊134A2。此外，痕跡部分134A3可將通孔134A1與RDL134A2互聯並通過導電插塞122A將焊線136A電耦合到晶片110’和210’。RDL 134B被用作路由(routing)線路，用來路由晶片110’中的信號。例如，RDL 134B可被用來電路由導電插塞122B和125之間的信號。在一些實施例中，RDL 134B焊線上沒有執行焊線和覆晶結合。RDL 134C連接到焊線球136B和金屬線138B。RDL 134C電連接到導電插塞124，其在金屬墊108處終止並不穿透晶片110’。通過金屬墊108、RDL 134C進一步連接到導電插塞122C，導電插塞122C進一步 將晶片110’與晶片210’互聯。因此，RDL 134A、134B和134C的形成改進封裝件310中電信號之路由能力。
需要注意的是，儘管圖7示出了堆疊在一起的兩個半導體晶圓，本領域普通技術人員能夠意識到圖7所示的堆疊式半導體裝置僅僅是一個示例。可以有很多替換、改變和修改。例如，堆疊式半導體裝置可容納超過兩個半導體晶圓。
圖8和圖9示出根據可替換實施例的形成堆疊晶片之中間階段的截面圖。除非特定說明，在這些實施例中的元件之材料和形成方法實質上與圖1至圖7所示實施例中之類似參考數字指示的類似元件相同。因此，關於圖8和圖9(以及圖10到圖19)所示元件的形成過程和材料之細節可在對圖1至圖7所示實施例的討論中找到。
這些實施例的起始步驟實質上與圖1至圖5的相同。接下來，如圖8所示，在介電層128中形成金屬線140(其共同形成金屬層)和通孔142。金屬線140和通孔142可使用雙鑲嵌過程形成，其包括形成介電層128和蝕刻阻止層126中的溝槽和通孔開口，並使用金屬材料填充溝槽和通孔開口以分別形成金屬線140和通孔142。在可替換的實施例中，可使用單鑲嵌過程來形成金屬線140和通孔142。可形成超過一層的金屬層。例如，圖8示出了在介電層148中形成包括金屬線144的額外金屬層以及各自的通孔146。在金屬線144上形成蝕刻阻止層150。
參照圖9，形成RDL 134A、134B和134C以及焊線136A/138A和136B/138B。該形成過程和材料可與圖7所示實施例中的相同，因此這裏不再贅述。類似於圖7所示的實施例，RDL 134A、134B和134C與導電插塞122A、122B、122C、124和125結合，以路由晶片110’和210’之間的信號並路由晶片110’內的信號。
圖10到圖17示出根據本發明之可替換實施例的堆疊晶片的形成。在這些實施例中，不形成如圖7和圖9所示的金屬墊106。下面簡 要討論形成過程。
參照圖10，在薄化第一基底102後，在晶圓110和210彼此結合。虛線圖示薄化過程中去除的基底102的部分。如圖10所示，在晶圓210中形成金屬墊206(包括206A和206B)。不同於圖1的實施例，晶圓110中沒有形成與金屬墊206重疊的金屬墊。另一方面，晶圓110的介電層104中在不與金屬墊206對準的位置處形成金屬墊108。
參照圖11，通過蝕刻薄化後的基底102形成開口114(包括114A和114B)和116，從而暴露下面的介電層104。接下來，如圖12所示，在基底102的後表面和側壁形成介電層113。因此，基底102暴露的表面是絕緣的。
圖13示出了掩模層117的形成，其掩蓋開口116(圖12)並暴露開口114A和114B的一些部分。然後執行各向異性蝕刻步驟來蝕刻介電層113、104和介電層204的一些部分。執行蝕刻直到暴露金屬墊206。如圖13所示，因為沒有形成金屬硬掩模(例如圖7和圖9的106)，最終的開口118(包括118A和118B)穿過介電層104一直延伸至晶圓210。開口118A和118B在金屬墊206處終止。然後去除掩模層117。
參照圖14，形成並圖案化掩模層152(可以是光阻)。掩模層152覆蓋開口118A和118B(圖13)並暴露基底102的開口116之中間部分。然後執行各向異性蝕刻以蝕刻介電層104以形成開口120，開口120在金屬108處終止。在形成開口120後去除掩模層152。
如圖13和圖14所示，根據這些實施例，在平版印刷步驟而不是在形成開口120的步驟中形成開口118A和118B。這部分是因為金屬墊108比金屬墊206高很多，因此，如果開口118A、118B和120同時形成，金屬墊108不能作為一個有效的蝕刻阻止層。否則，金屬墊108可能被不希望的蝕穿。
圖15至圖17所示的剩餘過程步驟實質上與圖6和圖7的相同。如 圖17所示，形成導電插塞122(包括122A、122B和122C)、124、125、RDL 134(包括134A、134B和134C)以及焊線136/138。圖17示出了不同於圖10至圖16的步驟示出的一些額外導電插塞和通孔。然而，額外導電插塞和通孔之結構和形成可通過本發明的教示而實現。
在圖17中，導電插塞122A、122B和122C中每一者包括兩個部分，其中第一部分穿透基底102而第二部分穿透介電層104到介電層204並一直到金屬墊206。類似於圖7和圖9，根據這些實施例之RDL 134可被用來連接將晶片110’與晶片210’互聯的導電插塞122。此外，RDL 134可被用作結合墊。
圖18和圖19示出根據可替換實施例的形成堆疊晶片的中間階段的截面圖。這些實施例類似於圖10至圖17的實施例，除了在介電層128和148中形成包括金屬線140和144以及通孔142和146的雙鑲嵌結構。雙鑲嵌結構將RDL 134與下面的導電插塞122、124和125互聯，以改進封裝件310的信號路由能力。其餘的特徵實質上與圖17的相同，因而這裏不再討論。
圖20A至圖20D示出根據本發明之各種實施例的金屬硬掩模(金屬墊)106的各種俯視圖。圖20A示出金屬墊是圓形的，內邊緣和外邊緣都是圓形的。圖20B示出金屬墊106的外邊緣是圓形的，而金屬墊106的內邊緣是矩形的(例如正方形)。圖20C示出金屬墊106是環形的，內邊緣和外邊緣都是圓形的。圖20D示出金屬墊106的外邊緣是圓形的，而金屬墊106的內邊緣是矩形的(例如正方形)。
本發明的實施例具有一些優勢特徵。封裝件中兩個半導體晶圓的有源電路通過連續的導電插塞(例如，圖7、圖9、圖17和圖19的導電插塞122)彼此連接。這種連續的導電插塞有助於減少封裝件的長度。而且，與由包括複數個部分的導電插塞連接的傳統堆疊式半導體裝置相比，在兩個半導體晶圓/晶粒之間耦合的連續導電插塞有助於 削減功耗並防止寄生干擾。薄化後的基底也將減少導電插塞的長度和間距。
前面概括了複數個實施例的特徵，使得本領域技術人員可更好地理解本發明的各個方面。本領域技術人員應該明白他們可以將本發明當作基礎，用來設計或修改用於執行相同目的和/或獲得在此介紹的實施例的相同好處的其他過程和結構。本領域技術人員也可意識到這樣等同的構造並不脫離本發明的精神和保護範圍，並且在不脫離本發明的精神和保護範圍的情況下，他們可以在此做各種改變、替換和修改。
102‧‧‧第一基底
103‧‧‧電子電路
104‧‧‧金屬間介電層
106‧‧‧金屬墊
108‧‧‧金屬墊
110‧‧‧半導體晶圓
110'‧‧‧晶片
122‧‧‧導電插塞
123‧‧‧導電阻擋層
124‧‧‧其他導電插塞
125‧‧‧其他導電插塞
127‧‧‧金屬材料
134‧‧‧再分配線(RDL)
134A1‧‧‧通孔
134A2‧‧‧RDL墊
134A3‧‧‧痕跡部分
136A‧‧‧結合球
136B‧‧‧結合球
138A‧‧‧金屬線
138B‧‧‧金屬線
202‧‧‧第二基底
204‧‧‧金屬間介電層
206‧‧‧金屬墊
210‧‧‧半導體晶圓
210'‧‧‧晶片
310‧‧‧封裝件

Claims (10)

  1. 一種積體電路結構，其包括：第一半導體晶圓，包括：第一基底；以及在該第一基底下面的第一複數個介電層；第二半導體晶圓，包括：第二基底；該第二基底之上的第二複數個介電層，其中該第一複數個介電層的底層結合到該第二複數個介電層的頂層；以及該第二複數個介電層之一層中的金屬墊；第一介電層，該第一介電層具有與該第一基底之頂表面共平面之上端以及與該第一基底之底表面共平面之下端；再分配線(RDL)，其位於該第一基底之上；以及第一導電插塞，其位於該再分配線的下面並電耦合至該再分配線，其中，該第一導電插塞包括：第一部分，其自該第一基底的頂表面延伸至該第一基底的底表面，其中該第一介電層環繞並接觸該導電插塞的該第一部分；以及第二部分，其自該第一基底的底表面延伸至該金屬墊，其中，該第二部分的底表面接觸該金屬墊的頂表面，且其中該第一部分和該第二部分形成連續區域。
  2. 如請求項1所述的積體電路結構，其中，該第一導電插塞包括自該第一基底的頂表面延伸至該第二半導體晶圓的同質材料，該同質材料中沒有形成交介面。
  3. 如請求項1所述的積體電路結構，進一步包括：雙鑲嵌結構，該雙鑲嵌結構包括金屬線和該金屬線下面的通孔，其中，該雙鑲嵌結構將該再分配線與該第一導電插塞互聯。
  4. 如請求項1所述的積體電路結構，其中，該第一半導體晶圓進一步包括形成環的額外金屬墊，該環中具有開口，且其中該第一導電插塞的該第二部分進一步包括：第三部分，位於該額外金屬墊之上；以及第四部分，其穿透該額外金屬墊以延伸到該第二半導體晶圓的金屬墊。
  5. 如請求項1所述的積體電路結構，其中，該第一半導體晶圓進一步包括：額外金屬墊，位於該第一複數個介電層中；以及第二導電插塞，其自該第一基底的頂表面延伸至該額外金屬墊，其中，該第二導電插塞在該額外金屬墊之頂表面處終止，且其中，該再分配線將該第一導電插塞電耦合至該第二導電插塞或該額外金屬墊將該第一導電插塞實質地連接該第二導電插塞。
  6. 一種積體電路結構，其包括：第一半導體晶圓，包括：第一基底；第一複數個介電層；以及第一金屬墊，其位於該第一複數個介電層的一層中；第二半導體晶圓，包括： 第二基底；第二複數個介電層，其位於該第二基底之上，其中該第一複數個介電層的底層結合到該第二複數個介電層的頂層；以及第二金屬墊，其位於該第二複數個介電層的一層中；第一介電層，該第一介電層具有與該第一基底之頂表面共平面之上端以及與該第一基底之底表面共平面之下端；第一導電插塞，其將第一金屬墊電耦合到第二金屬墊，其中該第一導電插塞包括：第一部分，其自該第一基底的頂表面延伸至該第一金屬墊的頂表面，其中該第一介電層環繞並接觸該第一部分；以及第二部分，其自該第一金屬墊的該頂表面延伸至第二金屬墊的頂表面，其中，該第二部分的邊緣與該第一金屬墊的側壁實質地接觸；以及再分配線，其位於該第一基底之上，其中該再分配線電耦合到該第一導電插塞。
  7. 如請求項6所述的積體電路結構，其中該第一導電插塞連續地自該第一基底的頂表面延伸至該第二金屬墊的頂表面，或其中該第一導電插塞的該第一部分進一步包括：該第一基底中的第一子部分；該第一複數個介電層中的第二子部分，其中，該第一子部分的寬度大於該第二子部分的寬度。
  8. 一種方法，其包括：將第一晶片結合到第二晶片，其中該第一晶片中的第一複數個介電層結合到該第二晶片中的第二複數個介電層； 在該第一晶片的第一基底中形成第一貫通開口；通過該第一開口蝕刻該第一複數個介電層以及該第二複數個介電層以形成第二開口，其中該第二複數個介電層中的第一金屬墊暴露於該第二開口；填充導電材料以在該第一開口和該第二開口中形成導電插塞；以及在該第一開口中形成第一介電層，其中該第一介電層具有與該第一基底之頂表面共平面之上端以及與該第一基底之底表面共平面之下端，且該第一介電層環繞並接觸該第一開口中的該導電插塞；在該第一基底之上形成第二介電層；以及形成再分配線，該再分配線包括在該第二介電層之上的部分，其中，該再分配線通過該第二介電層中的開口電耦合到該第一導電插塞。
  9. 如請求項8所述的方法，其中，該第二開口包括上部和位於該上部下面並與該上部連接的下部，且其中，該第二開口的該上部在該第一複數個介電層中的第二金屬墊的頂表面處終止，且其中，該第二開口的該下部穿透該第二金屬墊，該第二金屬墊形成環繞該第二開口之該下部的環。
  10. 如請求項8所述的方法，進一步包括：當形成該第一開口時，同時形成穿透該第一基底的第三開口；當形成該第二開口時，同時形成該第三開口下面的且與該第三開口連接的第四開口，其中，該第一複數個介電層中的第二金屬墊之頂表面通過該第三開口和該第四開口而暴露；以及 當執行填充該導電材料以形成該第一導電插塞時，同時填充該第三開口和該第四開口以形成第二導電插塞，其中，該再分配線將該第一導電插塞電耦合到該第二導電插塞。
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