CN105225965A - 一种扇出型封装结构及其制作方法 - Google Patents

一种扇出型封装结构及其制作方法 Download PDF

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Publication number
CN105225965A
CN105225965A CN201510741725.0A CN201510741725A CN105225965A CN 105225965 A CN105225965 A CN 105225965A CN 201510741725 A CN201510741725 A CN 201510741725A CN 105225965 A CN105225965 A CN 105225965A
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projection cube
layer
fan
cube structure
chip
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CN201510741725.0A
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CN105225965B (zh
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林正忠
蔡奇风
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201510741725.0A priority Critical patent/CN105225965B/zh
Publication of CN105225965A publication Critical patent/CN105225965A/zh
Priority to PCT/CN2016/076236 priority patent/WO2017075929A1/zh
Priority to US15/571,581 priority patent/US10056350B2/en
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Publication of CN105225965B publication Critical patent/CN105225965B/zh
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Abstract

本发明提供一种扇出型封装结构及其制作方法，所述方法包括以下步骤：S1：提供一基板，在所述基板上表面形成粘胶层；S2：在所述粘胶层上表面形成再分布引线层；S3：在所述再分布引线层上表面键合至少一个第一芯片并制作至少两个第一凸块结构；所述第一芯片与所述第一凸块结构均与所述再分布引线层电连接，且所述第一凸块结构的顶部高于所述第一芯片的顶部；S4：在所述再分布引线层上表面形成塑封层，所述塑封层覆盖所述第一芯片，且暴露出所述第一凸块结构的上端；S5：去除所述基板及粘胶层，在所述再分布引线层下表面制作第二凸块结构。本发明可以减少芯片与再分布引线层之间的偏移，提高良率；且封装过程更为简单，可以降低生产成本。

Description

一种扇出型封装结构及其制作方法
技术领域
本发明属于半导体封装领域，涉及一种扇出型封装结构及其制作方法。
背景技术
半导体工业通过持续减小最小特征尺寸来继续提高各种各样电子元件的整合密度，使得在给定的面积下可以集成更多的电子元件。目前，最先进的封装解决方案包括晶圆级芯片尺寸封装(Waferlevelchip-scalepackage)、扇出型晶圆级封装(Fan-outwaferlevelpackage)倒装芯片(Flipchip)以及堆叠型封装(PackageonPackage，POP)等等。
传统的扇出型晶圆级封装(Fan-outwaferlevelpackaging，FOWLP)一般包括如下几个步骤：首先从晶圆切下单个微芯片，并采用标准拾放设备将芯片正面朝下粘贴到载体的粘胶层上；然后形成塑封层，将芯片嵌入塑封层内；在塑封层固化后，去除载体及粘胶层，然后进行再分布引线层工艺及植球回流工艺，最后进行切割和测试。再分布引线层(RedistributionLayers，RDL)是倒装芯片组件中芯片与封装之间的接口界面。再分布引线层是一个额外的金属层，由核心金属顶部走线组成，用于将裸片的I/O焊盘向外绑定到诸如凸点焊盘等其它位置。凸点通常以栅格图案布置，每个凸点都浇铸有两个焊盘(一个在顶部，一个在底部)，它们分别连接再分布引线层和封装基板。传统的扇出型晶圆级封装容易导致芯片与RDL层之间发生偏移，导致良率较低。
堆叠型封装(PackageonPackage，PoP)可以使单个封装体内纵向堆叠多个芯片，将纵向分离的逻辑和存储球栅阵列结合，层叠的各封装体之间通过标准接口来传输信号，从而实现元件密度的倍增，使单个封装体实现更多的功能，广泛应用于手机、个人数字助理(PDA)、数码相机等领域。
先进封装中，硅通孔技术(Through-siliconvia，TSV)有着重大影响，其是穿透基片(特别是硅基片)的垂直电连接技术。TSV几乎可以代替所有封装中的引线键合(Wire-Bonding)的地方，提高所有种类芯片封装的电气性能，包括提高集成度，缩小芯片尺寸，特别是在系统集封装(System-in-Packaging，SiP)，圆片级封装(Wafer-LevelPackaging–WLP)以及三维垂直叠层封装(3DPackaging)这些先进封装之中。TSV的制造包括了通孔的制造，绝缘层的沉积，通孔的填充以及后续的化学机械平整化(CMP)和再布线(RDL)等工艺。传统的堆叠型封装与TSV工艺相关，需要一系列复杂的制造工艺，导致较高的生产成本和较低的良率。
因此，如何提供一种扇出型封装结构及其制作方法，以降低生产成本，提高良率，成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种扇出型封装结构及其制作方法，用于解决现有技术中封装成本较高、良率较低的问题。
为实现上述目的及其他相关目的，本发明提供一种扇出型封装结构的制作方法，包括以下步骤：
S1：提供一基板，在所述基板上表面形成粘胶层；
S2：在所述粘胶层上表面形成再分布引线层；
S3：在所述再分布引线层上表面键合至少一个第一芯片并制作至少两个第一凸块结构；所述第一芯片与所述第一凸块结构均与所述再分布引线层电连接，且所述第一凸块结构的顶部高于所述第一芯片的顶部；
S4：在所述再分布引线层上表面形成塑封层，所述塑封层覆盖所述第一芯片，且暴露出所述第一凸块结构的上端；
S5：去除所述基板及粘胶层，在所述再分布引线层下表面制作第二凸块结构。
可选地，还包括步骤S6：在所述第一凸块结构暴露出的上端键合至少一个第一封装体。
可选地，将所述步骤S6得到的结构通过所述第二凸块结构连接于第二封装体。
可选地，所述再分布引线层包括介质层及形成于所述介质层中的至少一层再分布金属线路。
可选地，于所述步骤S3中，所述第一芯片表面制作有第三凸块结构，所述第一芯片通过所述第三凸块结构与所述再分布引线层电连接。
可选地，于所述步骤S3中，所述第一凸块结构包括金属柱及形成于所述金属柱顶端的锡基金属帽。
可选地，所述金属柱为Cu柱或Ni柱。
可选地，于所述步骤S3中，所述第一凸块结构为金属焊球。
可选地，于所述步骤S4中，采用压模法形成所述塑封层，包括如下步骤：
S4-1：提供一压模组件，所述压模组件包括底部压块及顶部压块；
S4-2：在所述顶部压块下表面贴上隔离膜，将所述基板放置于所述底部压块表面，并在所述再分布引线层表面放置塑封材料；
S4-3：通过所述顶部压块及所述底部压块将所述基板夹紧，使所述塑封材料被压平，且所述第一凸块结构的上端嵌入所述隔离膜中；
S4-4：释放所述顶部压块及所述底部压块，并剥离所述隔离膜。
可选地，所述隔离膜为柔性聚合物材料。
可选地，于所述步骤S5中，所述第二凸块结构为金属焊球。
本发明还提供一种扇出型封装结构，包括：
再分布引线层；
键合于所述再分布引线层上表面并与所述再分布引线层电连接的至少一个第一芯片；
与所述再分布引线层电连接且顶部高于所述第一芯片的至少两个第一凸块结构；
覆盖所述第一芯片，且暴露出所述第一凸块结构的上端的塑封层；
以及制作于所述再分布引线层下表面的第二凸块结构。
可选地，所述扇出型封装结构还包括键合于所述第一凸块结构暴露出的上端的至少一个第一封装体。
可选地，所述扇出型封装结构还包括与所述第二凸块结构连接的第二封装体。
可选地，所述再分布引线层包括介质层及形成于所述介质层中的至少一层再分布金属线路。
可选地，所述第一芯片表面制作有第三凸块结构，所述第一芯片通过所述第三凸块结构与所述再分布引线层电连接。
可选地，所述第一凸块结构包括金属柱及形成于所述金属柱顶端的锡基金属帽；或者所述第一凸块结构为金属焊球。
如上所述，本发明的扇出型封装结构及其制作方法，具有以下有益效果：(1)本发明的扇出型封装结构的制作方法首先在载体上制作再分布引线层，然后再将芯片与再分布引线层连接，避免了传统塑封过程中因塑封材料加热固化过程中的收缩使得芯片与再分布引线层发生偏移的问题，大幅提高了良率。(2)本发明可通过在所述第一凸块结构暴露出的上端键合至少一个第一封装体，得到堆叠型封装结构，并且多个第一封装体可为不同类型，拓展了应用类型。(3)本发明采用第一凸块结构作为堆叠型封装的互连结构，其中，所述第一凸块结构嵌于塑封层内并暴露出上端，相对于复杂的TSV制作流程，本发明首先制作所述第一凸块结构，然后进行模压形成所述塑封层，工艺流程更为简单，且上层封装体可以直接键合于所述第一凸块结构暴露的上端，封装过程也更简单，从而降低成本。(4)本发明通过模压法结合分隔膜得到所述塑封层，使得塑封层上表面低于所述第一凸块结构顶部，避免了塑封层的减薄与激光开孔过程，不仅节省了材料、降低了污染，也避免了减薄过程导致电路结构的损坏，同时也使得堆叠型封装更容易实现。(5)本发明的扇出型封装结构不仅具有堆叠型封装能力，也具有多样封装体结合能力，满足多样的应用需求，同时还可以将得到的整个堆叠型封装体通过所述第二凸块结构键合于PCB板或其它封装体。
附图说明
图1显示为本发明的扇出型封装结构的制作方法的工艺流程图。
图2显示为本发明的扇出型封装结构的制作方法在基板上表面形成粘胶层示意图。
图3显示为本发明的扇出型封装结构的制作方法在所述粘胶层上表面形成再分布引线层的示意图。
图4显示为本发明的扇出型封装结构的制作方法在所述再分布引线层上表面键合至少一个第一芯片并制作至少两个第一凸块结构的示意图。
图5显示为本发明的扇出型封装结构的制作方法在所述再分布引线层上表面形成塑封层的示意图。
图6显示为本发明的扇出型封装结构的制作方法使用的压模组件的结构示意图。
图7显示为本发明的扇出型封装结构的制作方法在所述压模组件的顶部压块下表面贴上隔离膜，将所述基板放置于所述底部压块表面，并在所述再分布引线层表面放置塑封材料的示意图。
图8显示为本发明的扇出型封装结构的制作方法通过所述顶部压块及所述底部压块将所述基板夹紧，使所述塑封材料被压平，且所述第一凸块结构的上端嵌入所述隔离膜中的示意图。
图9显示为本发明的扇出型封装结构的制作方法释放所述顶部压块及所述底部压块，并剥离所述隔离膜的示意图。
图10显示为本发明的扇出型封装结构的制作方法压模完毕得到的结构示意图。
图11显示为本发明的扇出型封装结构的制作方法去除所述基板及粘胶层的示意图。
图12显示为本发明的扇出型封装结构的制作方法在所述再分布引线层下表面制作第二凸块结构的示意图。
图13显示为本发明的扇出型封装结构的制作方法在所述第一凸块结构暴露出的上端键合至少一个第一封装体的示意图。
图14显示为本发明的扇出型封装结构的制作方法将封装结构通过所述第二凸块结构连接于第二封装体的示意图。
元件标号说明
S1～S5步骤
1基板
2粘胶层
3再分布引线层
31介质层
32再分布金属线路
4第一芯片
41第三凸块结构
5第一凸块结构
51金属柱
52锡基金属帽
6塑封层
7第二凸块结构
8第一封装体
9第二封装体
10压模组件
101底部压块
102顶部压块
11隔离膜
12塑封材料
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图14。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本发明提供一种扇出型封装结构的制作方法，请参阅图1，显示为该方法的工艺流程图，包括以下步骤：
S1：提供一基板，在所述基板上表面形成粘胶层；
S2：在所述粘胶层上表面形成再分布引线层；
S3：在所述再分布引线层上表面键合至少一个第一芯片并制作至少两个第一凸块结构；所述第一芯片与所述第一凸块结构均与所述再分布引线层电连接，且所述第一凸块结构的顶部高于所述第一芯片的顶部；
S4：在所述再分布引线层上表面形成塑封层，所述塑封层覆盖所述第一芯片，且暴露出所述第一凸块结构的上端；
S5：去除所述基板及粘胶层，在所述再分布引线层下表面制作第二凸块结构。
首先请参阅图2，执行步骤S1：提供一基板1，在所述基板1上表面形成粘胶层2。
所述基板1可以为后续制作粘胶层2、再分布引线层3、塑封层6等提供刚性的结构或基体，其材料可选自玻璃、金属、半导体(例如Si)、聚合物或陶瓷中的至少一种。作为示例，所述基板1选用玻璃。本发明中，所述基板1可为晶圆形、方形(例如500*500mm)或其它任意所需形状。
所述粘胶层2在后续工艺中作为再分布引线层3与基板1之间的分离层，其最好选用具有光洁表面的粘合材料制成，其必须与再分布引线层3具有一定的结合力，以保证所述再分布引线层3在后续工艺中不会产生移动等情况，另外，其与所述基板1亦具有较强的结合力，一般来说，其与所述基板1的结合力需要大于与所述再分布引线层3的结合力。作为示例，所述粘胶层2的材料选自双面均具有粘性的胶带或通过旋涂工艺制作的粘合胶等。所述胶带优选采用UV胶带，其在UV光照射后很容易被撕离。在其它实施例中，所述粘胶层2也可选用物理气相沉积法或化学气相沉积法指的的其他材料层，如环氧树脂(Epoxy)、硅橡胶(siliconerubber)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等。在后续分离所述基板1时，可采用湿法腐蚀、化学机械研磨等方法去除所述粘胶层2。
然后请参阅图3，执行步骤S2：在所述粘胶层2上表面形成再分布引线层3。
具体的，所述再分布引线层3包括介质层31及形成于所述介质层31中的至少一层再分布金属线路32。作为示例，如图3所述，所述再分布引线层3包括四层再分布金属线路32，其中，顶层及底层的再分布金属线路32分别暴露于所述介质层31的上表面及下表面。各层再分布金属线路32之间通过若干导电柱相连接。
作为示例，对于所述再分布引线层3包括多层再分布金属线路32的情形，可采用交替形成介质层与再分布金属线路的方式得到。所述再分布金属线路32可选用物理气相沉积法(PVD)、化学气相沉积法(CVD)、溅射法、电镀及化学镀中的至少一种方法形成。所述介质层31可选用旋涂、物理气相沉积及化学气相沉积中的至少一种方法形成。
所述再分布金属线路32采用导电金属，包括但不限于铜、铝、钛等电的良导体。所述介质层31的材料包括但不限于环氧树脂、硅橡胶、硅树脂、PI、PBO、BCB，也可采用低K介质，例如氧化硅、磷硅玻璃、氟化玻璃等。
接着请参阅图4，执行步骤S3：在所述再分布引线层3上表面键合至少一个第一芯片4并制作至少两个第一凸块结构5；所述第一芯片4与所述第一凸块结构5均与所述再分布引线层3电连接，且所述第一凸块结构5的顶部高于所述第一芯片4的顶部。
具体的，可通过键迹法(bond-on-trace)将所述第一芯片4键合于所述再分布引线层3上表面。作为示例，所述第一芯片4表面制作有第三凸块结构41，所述第一芯片4通过所述第三凸块结构41与所述再分布引线层3电连接。所述第三凸块结构41包括但不限于铜、镍或银锡铜合金焊球。
所述第一芯片4可包括基底或更多电路结构。当所述再分布引线层3上表面键合多个第一芯片4时，各第一芯片4可为相同类型，也可以为不同类型。
本发明的扇出型封装结构的制作方法首先在载体上制作再分布引线层，然后再将芯片与再分布引线层连接，避免了传统塑封过程中因塑封材料加热固化过程中的收缩使得芯片与再分布引线层发生偏移的问题，大幅提高了良率。
具体的，所述第一凸块结构5的顶部高于所述第一芯片4的顶部。当多个第一芯片4的高度不一致时，所述第一凸块5的顶部高于所有所述第一芯片4的顶部。
本实施例中，所述第一凸块结构5包括金属柱51及形成于所述金属柱51顶端的锡基金属帽52。所述金属柱51包括但不限于Cu柱或Ni柱。可通过常规的厚光阻光刻、显影、金属沉积等工艺形成所述金属柱51，也可通过微压印、金属沉积等工艺形成所述金属柱51。
在另一实施例中，所述第一凸块结构5也可不包括金属柱，而仅仅为金属焊球(solderball)。相对于所述第一凸块结构5仅为金属焊球的方案，所述第一凸块结构5为金属柱结合锡基金属帽的方案更有利于节约封装面积。
再请参阅图5，执行步骤S4：在所述再分布引线层3上表面形成塑封层6，所述塑封层6覆盖所述第一芯片4，且暴露出所述第一凸块结构5的上端。
具体的，所述塑封层6采用热固性材料，包括但不限于聚合物材料、树脂基材料、聚酰亚胺(PI)、环氧树脂等材料中的一种或多种。
具体的，暴露出的所述第一凸块结构5的上端高度可以根据需要进行调整。本实施例中，采用压模法形成所述塑封层6，包括如下步骤：
如图6所示，执行步骤S4-1：提供一压模组件10，所述压模组件10包括底部压块101及顶部压块102。
如图7所示，执行步骤S4-2：在所述顶部压块102下表面贴上隔离膜11，将所述基板1放置于所述底部压块101表面，并在所述再分布引线层3表面放置塑封材料12。所述塑封材料12可以为液态，也可以为固态颗粒，其中固态颗粒在后续的高温高压下会转变为液态。
如图8所示，执行步骤S4-3：通过所述顶部压块102及所述底部压块101将所述基板1夹紧，使所述塑封材料被压平，且所述第一凸块结构5的上端嵌入所述隔离膜11中。
如图9所示，执行步骤S4-4：释放所述顶部压块102及所述底部压块101，并剥离所述隔离膜11。
具体的，所述隔离膜11为柔性聚合物材料，包括但不限于聚酰亚胺、环氧树脂、聚酯(PET)等。通过所述隔离膜11，在压模过程中，由于所述第一凸块结构5的上端嵌入所述隔离膜11中，使得所述第一凸块结构5的上端突出于塑封材料表面。
如图10所示，显示为压模完毕得到的结构示意图，其中被压平的塑封材料固化后即作为所述塑封层6，所述塑封层6且暴露出所述第一凸块结构5的上端。需要指出的是，为了图示的方便，所述基板1上的粘胶层2、再分布引线层3、第一芯片4未详细图示于图7、8、9及10中。
本发明通过模压法结合分隔膜得到所述塑封层，使得塑封层上表面低于所述第一凸块结构顶部，避免了塑封层的减薄与激光开孔过程，不仅节省了材料、降低了污染，也避免了减薄过程导致电路结构的损坏。
最后请参阅图11及图12，执行步骤S5：去除所述基板1及粘胶层2，在所述再分布引线层3下表面制作第二凸块结构7。
具体的，所述第二凸块结构7为金属焊球，。
至此，制作得到了本发明的扇出型封装结构。其中，所述第一凸块结构5嵌于所述塑封层6，且暴露出上端。所述塑封层6不仅起到塑封所述第一芯片4的作用，其结合所述第一凸块结构，可以替代TSV结构，实现堆叠型封装。
如图13所示，显示为在所述第一凸块结构5暴露出的上端键合至少一个第一封装体8的示意图。其中，多个第一封装体可为相同类型，也可以为不同类型，以满足不同的应用需求。
相对于复杂的TSV制作流程，本发明首先制作所述第一凸块结构，然后进行模压形成所述塑封层，工艺流程更为简单，且上层封装体可以直接键合于所述第一凸块结构暴露的上端，封装过程也更简单，从而降低成本。
此外，如图14所示，可进一步将如图13所示结构通过所述第二凸块结构7连接于第二封装体9。作为示例，所述第二封装体9为PCB板。在其他实施例中，所述第二封装体9也可以为其它封装体，此处不应过分限制本发明的保护范围。
实施例二
本发明还提供一种扇出型封装结构，如图12所示，显示为该扇出型封装结构的示意图，包括：
再分布引线层3；
键合于所述再分布引线层3上表面并与所述再分布引线层3电连接的至少一个第一芯片4；
与所述再分布引线层3电连接且顶部高于所述第一芯片4的至少两个第一凸块结构5；
覆盖所述第一芯片4，且暴露出所述第一凸块结构5的上端的塑封层6；
以及制作于所述再分布引线层3下表面的第二凸块结构7。
具体的，所述再分布引线层3包括介质层31及形成于所述介质层31中的至少一层再分布金属线路32。作为示例，所述再分布引线层3包括四层再分布金属线路32，其中，顶层及底层的再分布金属线路32分别暴露于所述介质层31的上表面及下表面。各层再分布金属线路32之间通过若干导电柱相连接。
所述再分布金属线路32采用导电金属，包括但不限于铜、铝、钛等电的良导体。所述介质层31的材料包括但不限于环氧树脂、硅橡胶、硅树脂、PI、PBO、BCB，也可采用低K介质，例如氧化硅、磷硅玻璃、氟化玻璃等。
具体的，所述第一芯片4表面制作有第三凸块结构41，所述第一芯片4通过所述第三凸块结构41与所述再分布引线层3电连接。所述第三凸块结构41包括但不限于铜、镍或银锡铜合金焊球。所述第一芯片4可包括基底或更多电路结构。当所述再分布引线层3上表面键合多个第一芯片4时，各第一芯片4可为相同类型，也可以为不同类型。
具体的，所述第一凸块结构5的顶部高于所述第一芯片4的顶部。当多个第一芯片4的高度不一致时，所述第一凸块5的顶部高于所有所述第一芯片4的顶部。
本实施例中，所述第一凸块结构5包括金属柱51及形成于所述金属柱51顶端的锡基金属帽52。所述金属柱51包括但不限于Cu柱或Ni柱。
在另一实施例中，所述第一凸块结构5也可不包括金属柱，而仅仅为金属焊球(solderball)。相对于所述第一凸块结构5仅为金属焊球的方案，所述第一凸块结构5为金属柱结合锡基金属帽的方案更有利于节约封装面积。
具体的，所述塑封层6采用热固性材料，包括但不限于聚合物材料、树脂基材料、聚酰亚胺(PI)、环氧树脂等材料中的一种或多种。所述塑封层6上暴露出的所述第一凸块结构5的上端高度可以根据需要进行调整。
本发明的扇出型封装结构不仅具有堆叠型封装能力，也具有多样封装体结合能力。如图13所示，显示为所述扇出型封装结构还包括键合于所述第一凸块结构5暴露出的上端的至少一个第一封装体8。其中，多个第一封装体可为相同类型，也可以为不同类型，从而满足多样的应用需求。
此外，如图14所示，所述扇出型封装结构还可进一步包括与所述第二凸块结构7连接的第二封装体9。所述第二封装体9可为PCB板或其它封装体。
本发明的扇出型封装结构中，所述塑封层6不仅起到塑封所述第一芯片4的作用，其结合所述第一凸块结构5，可以替代TSV结构，实现堆叠型封装。相对于复杂的TSV制作流程，本发明由塑封层6及所述第一凸块结构5组成的类TSV结构更易制备，有利于简化工艺流程，降低成本。由于所述第一凸块结构5嵌于所述塑封层6中且暴露出上端，使得堆叠型封装更容易实现。所述堆叠型封装结构可进一步通过所述第二凸块结构7与PCB板或其它封装体键合，提高封装效率。
综上所述，本发明的扇出型封装结构及其制作方法，具有以下有益效果：(1)本发明的扇出型封装结构的制作方法首先在载体上制作再分布引线层，然后再将芯片与再分布引线层连接，避免了传统塑封过程中因塑封材料加热固化过程中的收缩使得芯片与再分布引线层发生偏移的问题，大幅提高了良率。(2)本发明可通过在所述第一凸块结构暴露出的上端键合至少一个第一封装体，得到堆叠型封装结构，并且多个第一封装体可为不同类型，拓展了应用类型。(3)本发明采用第一凸块结构作为堆叠型封装的互连结构，其中，所述第一凸块结构嵌于塑封层内并暴露出上端，相对于复杂的TSV制作流程，本发明首先制作所述第一凸块结构，然后进行模压形成所述塑封层，工艺流程更为简单，且上层封装体可以直接键合于所述第一凸块结构暴露的上端，封装过程也更简单，从而降低成本。(4)本发明通过模压法结合分隔膜得到所述塑封层，使得塑封层上表面低于所述第一凸块结构顶部，避免了塑封层的减薄与开孔过程，不仅节省了材料、降低了污染，也避免了减薄过程导致电路结构的损坏，同时也使得堆叠型封装更容易实现。(5)本发明的扇出型封装结构不仅具有堆叠型封装能力，也具有多样封装体结合能力，满足多样的应用需求，同时还可以将得到的整个堆叠型封装体通过所述第二凸块结构键合于PCB板或其它封装体。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (17)

1.一种扇出型封装结构的制作方法，其特征在于，包括以下步骤：
S1：提供一基板，在所述基板上表面形成粘胶层；
S2：在所述粘胶层上表面形成再分布引线层；
S3：在所述再分布引线层上表面键合至少一个第一芯片并制作至少两个第一凸块结构；所述第一芯片与所述第一凸块结构均与所述再分布引线层电连接，且所述第一凸块结构的顶部高于所述第一芯片的顶部；
S4：在所述再分布引线层上表面形成塑封层，所述塑封层覆盖所述第一芯片，且暴露出所述第一凸块结构的上端；
S5：去除所述基板及粘胶层，在所述再分布引线层下表面制作第二凸块结构。
2.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：还包括步骤S6：在所述第一凸块结构暴露出的上端键合至少一个第一封装体。
3.根据权利要求2所述的扇出型封装结构的制作方法，其特征在于：将所述步骤S6得到的结构通过所述第二凸块结构连接于第二封装体。
4.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：所述再分布引线层包括介质层及形成于所述介质层中的至少一层再分布金属线路。
5.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：于所述步骤S3中，所述第一芯片表面制作有第三凸块结构，所述第一芯片通过所述第三凸块结构与所述再分布引线层电连接。
6.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：于所述步骤S3中，所述第一凸块结构包括金属柱及形成于所述金属柱顶端的锡基金属帽。
7.根据权利要求6所述的扇出型封装结构的制作方法，其特征在于：所述金属柱为Cu柱或Ni柱。
8.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：于所述步骤S3中，所述第一凸块结构为金属焊球。
9.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：于所述步骤S4中，采用压模法形成所述塑封层，包括如下步骤：
S4-1：提供一压模组件，所述压模组件包括底部压块及顶部压块；
S4-2：在所述顶部压块下表面贴上隔离膜，将所述基板放置于所述底部压块表面，并在所述再分布引线层表面放置塑封材料；
S4-3：通过所述顶部压块及所述底部压块将所述基板夹紧，使所述塑封材料被压平，且所述第一凸块结构的上端嵌入所述隔离膜中；
S4-4：释放所述顶部压块及所述底部压块，并剥离所述隔离膜。
10.根据权利要求9所述的扇出型封装结构的制作方法，其特征在于：所述隔离膜为柔性聚合物材料。
11.根据权利要求1所述的扇出型封装结构的制作方法，其特征在于：于所述步骤S5中，所述第二凸块结构为金属焊球。
12.一种扇出型封装结构，其特征在于，包括：
再分布引线层；
键合于所述再分布引线层上表面并与所述再分布引线层电连接的至少一个第一芯片；
与所述再分布引线层电连接且顶部高于所述第一芯片的至少两个第一凸块结构；
覆盖所述第一芯片，且暴露出所述第一凸块结构的上端的塑封层；
以及制作于所述再分布引线层下表面的第二凸块结构。
13.根据权利要求12所述的扇出型封装结构，其特征在于：所述扇出型封装结构还包括键合于所述第一凸块结构暴露出的上端的至少一个第一封装体。
14.根据权利要求12或13所述的扇出型封装结构，其特征在于：所述扇出型封装结构还包括与所述第二凸块结构连接的第二封装体。
15.根据权利要求12所述的扇出型封装结构，其特征在于：所述再分布引线层包括介质层及形成于所述介质层中的至少一层再分布金属线路。
16.根据权利要求12所述的扇出型封装结构，其特征在于：所述第一芯片表面制作有第三凸块结构，所述第一芯片通过所述第三凸块结构与所述再分布引线层电连接。
17.根据权利要求12所述的扇出型封装结构，其特征在于：所述第一凸块结构包括金属柱及形成于所述金属柱顶端的锡基金属帽；或者所述第一凸块结构为金属焊球。
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