WO2018129906A1 - 一种集成供电系统封装件的封装方法 - Google Patents

一种集成供电系统封装件的封装方法 Download PDF

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Publication number
WO2018129906A1
WO2018129906A1 PCT/CN2017/095426 CN2017095426W WO2018129906A1 WO 2018129906 A1 WO2018129906 A1 WO 2018129906A1 CN 2017095426 W CN2017095426 W CN 2017095426W WO 2018129906 A1 WO2018129906 A1 WO 2018129906A1
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Prior art keywords
power supply
supply system
packaging
rewiring layer
module
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PCT/CN2017/095426
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English (en)
French (fr)
Inventor
林章申
林正忠
何志宏
蔡奇风
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中芯长电半导体（江阴）有限公司
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Publication of WO2018129906A1 publication Critical patent/WO2018129906A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a packaging method for an integrated power supply system package.
  • the power supply system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power supply system determines the power loss of the down conversion, and the number of power rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power rails requires copying more power components, such as increasing component count, increasing board size, increasing the number of boards, increasing system size, cost, and weight.
  • the present invention provides a method of packaging an integrated power supply system package, the package including a power system die and a power supply system die located under the power system die.
  • the encapsulation method includes the following steps:
  • the power supply system die is a high-voltage power supply system die, converting a high voltage of the external power source into a plurality of different low voltages required in the power system die, and providing a plurality of docking applications.
  • the active module includes a controller and a buck converter, the passive module including a capacitor, an inductor, and a resistor.
  • the active module is laterally aligned with the passive module.
  • the rewiring layer includes: a metal wiring, a via hole, and a dielectric layer disposed around the metal wiring and the via hole, and the metal wiring is realized by the through hole and the active layer
  • the rewiring layer is provided with an under bump metal layer, and the active module, the passive module, the columnar metal lead, and the power system die pass through the under bump metal layer and the rewiring Layer electrical connection.
  • the columnar metal lead is a metal needle or a metal post.
  • the columnar metal leads are formed on the rewiring layer by bonding or electroplating.
  • the method of package molding is compression molding, transfer molding, liquid sealing molding, vacuum lamination or spin coating.
  • the plurality of solder bumps for soldering the power system die to the rewiring layer are micro bumps.
  • the packaging method of the integrated power supply system package of the present invention has the following beneficial effects:
  • the present invention provides a new method of integrating the entire power supply system into the package.
  • the power transmission efficiency is improved, and the available number of different voltage tracks is increased.
  • the invention adopts existing active components and passive modules to form a 2.5D intermediate layer, and then integrates a power system die such as an ASIC into the top of the 2.5D intermediate layer to obtain a 3D stack structure, which is directly under the bare core of the power system.
  • the tight integration of the power supply system bare core solves the problems faced by existing power supply systems.
  • the power supply system bare core can provide thousands of low-voltage power supply rails and the power system directly through the micro-bumps; due to the integration of passive modules, the parasitic resistance of the PCB board can be eliminated, and the power supply efficiency and response time of the power supply control can be improved. Reducing pressure drop and noise increases fidelity and reduces the amount of design required.
  • FIG. 1 is a schematic diagram of a packaging method of an integrated power supply system package according to an embodiment of the present invention.
  • FIGS. 2a-2f are schematic diagrams showing the process flow of a method for packaging an integrated power supply system package according to an embodiment of the present invention.
  • the present invention proposes a new method of integrating the entire power supply system into a package by using a three-dimensional chip stacking technique.
  • the package incorporating the power supply system includes a power system die and a power supply system die located under the power system die; wherein the power system die includes an active module, a passive module, and a rewiring Layer, the active module and none The source module is packaged and formed, and the rewiring layer is located on the active module and the passive module formed by the package to realize electrical connection between the active module and the passive module, and provides multiple interconnections to the bare power system.
  • a power supply track of the core the power system die is docked with the plurality of power supply tracks through a plurality of solder bumps, and is packaged and fixed on the rewiring layer; the external power source directly passes through the power supply system die core The power system is powered by the bare core.
  • the embodiment provides a method for packaging an integrated power supply system package, which includes the following steps:
  • S1 provides a carrier
  • S6 forms a base solder bump connecting the columnar metal leads, and removes the carrier
  • S7 solders the power system die to the rewiring layer through a plurality of solder bumps, realizes the interface between the power system die and the plurality of power supply tracks, and then the power system die is grounded by underfilling A package is attached to the rewiring layer.
  • a carrier 101 is provided.
  • the material of the carrier 101 may be selected from one or more of glass, stainless steel, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 101 may be of a flat type.
  • the carrier 101 may be a silicon-based circular flat plate having a certain thickness.
  • an adhesion layer 1011 is formed on the surface of the carrier 101 for adhering and fixing the rewiring layer 200.
  • the rewiring layer 200 may be adhered by means of glue or tape.
  • the adhesion layer 1011 is also removed.
  • the adhesive layer 1011 may be a double-sided tape which is heated or UV-debonded.
  • one side may be UV-debonded on the other side, and the other side may be heated and de-bonded, or one side may be directly peeled off by heating and dissolving the other side.
  • the method is different.
  • the adhesion layer 1011 may also be a sacrificial layer of laser debonding. After the sacrificial layer is formed, the rewiring layer 200 may be adhered and fixed by applying glue on the sacrificial layer. When peeling off, the sacrificial layer can be removed by laser and then the glue can be removed.
  • the sacrificial layer may be deposited by CVD on the carrier 101 or may be coated with a LTHC (light to heat) material, and the glue may be removed by chemical reagents.
  • a rewiring layer 200 is formed on the carrier 101, and a columnar metal lead 301 is formed on the rewiring layer 200 as shown in Fig. 2b.
  • the rewiring layer 200 may include: a metal connection 201, a via hole, and a dielectric layer 202 disposed around the metal connection 201 and the via hole, and the metal connection 201 is implemented through the through hole With the above
  • the material of the metal connection 201 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wiring 201 may be a Cu wire, and the seed layer of the Cu wire may be a Ti/Cu layer.
  • the method of forming the metal wiring 201 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • the through hole may be formed by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting or other suitable opening methods.
  • the filling material of the through hole may be solder or Cu, and the filling method may be electrolytic plating, electroless plating, screen printing, wire bonding or other method suitable for filling a conductive material in the through hole.
  • the rewiring layer 200 is further provided with a bump under metal layer (UBM), and the active module 401, the passive module 402 and the columnar metal lead 301, and the power system die 601 pass through the The under bump metal layer is electrically connected to the rewiring layer 200.
  • the columnar metal lead 301 is used to realize electrical connection between the package and the external device.
  • the columnar metal lead 301 is a vertical columnar metal pin or a metal post, and may be bonded or plated.
  • the rewiring layer 200 is formed, for example, by electroplating a Cu stud or a bonded copper pin or the like.
  • the active module 401 and the passive module 402 of the power supply system die are respectively soldered on the rewiring layer 200, and the rewiring layer 200 implements the active module 401 and the passive module 402.
  • the electrical connection between the two is provided, and a plurality of power supply tracks for the bare core 601 of the power system are provided.
  • the bare core of the power supply system may be a bare core of the high voltage power supply system, and the high voltage of the external power source is converted into a plurality of different low voltages required in the bare core of the power system, and the plurality of dockings are provided. Low voltage supply rail for the bare core of the electrical system.
  • the active module 401 may include a controller and a buck converter.
  • the passive module 402 may include a capacitor, an inductor, and a resistor.
  • the passive module 402 includes a capacitor module 4022, an inductor module 4021, and a resistor ( Not shown in the figure).
  • the active module 401 and the passive module 402 such as the capacitor module 4022 and the inductor module 4021 are laterally arranged and packaged in the same leveling layer to facilitate the electrical connection and layout design of the rewiring layer 200.
  • the specific arrangement position can be designed according to actual needs. The invention is not limited thereto.
  • the active module 401 and the passive module 402 and the columnar metal lead 301 are packaged on the rewiring layer 200, and the active module 401 is covered and covered.
  • the excess package molding material of the passive module 402 and the columnar metal lead 301 may be compression molding, transfer molding, liquid sealing molding, vacuum lamination, spin coating, or other suitable method.
  • the material to be packaged may be an epoxy resin, a liquid type thermosetting epoxy resin, a plastic molding compound or the like.
  • the method of grinding may include one or more of mechanical grinding, chemical polishing, and etching.
  • a base solder bump 501 connecting the columnar metal wires 301 is formed, and the carrier 101 is removed.
  • the base solder bump 501 may be a solder ball, a copper ball or a tin-copper alloy ball, etc.
  • the example uses a Ball Grid Array (BGA) solder ball.
  • BGA Ball Grid Array
  • the package can achieve mounting on the package substrate and electrical connection to external devices through the base solder bumps 501.
  • the method of removing the carrier 101 may include one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, mechanical peeling, or other suitable methods.
  • the adhesive layer 1011 can be removed by debonding, thereby removing the carrier 101.
  • the power system die 601 is soldered to the rewiring layer 200 through a plurality of solder bumps 602 to achieve docking with a plurality of the power supply tracks, and then the underfill
  • the electrical system die 601 is packaged and fixed on the rewiring layer 200.
  • the power system die may be an ASIC Die.
  • the plurality of solder bumps 602 connected to the rewiring layer 200 by the power system die 601 may be micro-bumps or conventional bumps.
  • the underfill may be a CUF (Capillary Underfill) or a molding underfill (MUF, Molding UnderFill).
  • the invention adopts existing active components and passive modules to form a 2.5D intermediate layer, and then integrates a power system die such as an ASIC into the top of the 2.5D intermediate layer to obtain a 3D stack structure, thereby directly under the bare core of the power system. Tightly integrated power supply system die.
  • the external high-voltage power supply can directly supply power to the package.
  • the power supply system of the package converts the high voltage into the voltage required by the power system, and directly supplies the die of the power system through the micro-bumps or bumps through the plurality of power supply tracks.
  • the bare core of the power supply system can provide thousands of low-voltage power supply rails and the power system directly docked through the micro-bumps; since the passive module is integrated, the parasitic resistance generated by the conventional PCB board can be eliminated, and the improved
  • the power supply efficiency and response time of the power supply control improve the fidelity by reducing the voltage drop and noise, and reduce the required design margin, thereby effectively solving the problems faced by the conventional power supply system.
  • the present invention integrates the entire power supply system into the device package by using a three-dimensional chip stacking technology, improves power transmission efficiency, increases the available number of different voltage tracks, and solves various problems faced by the existing power supply system. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种集成供电系统的封装方法，包括以下步骤：提供一载体；在载体上形成再布线层；在再布线层上形成柱状金属引线；分别将供电系统裸芯的有源模块和无源模块焊接在再布线层上；将有源模块和无源模块以及柱状金属引线在再布线层上封装成型，并研磨掉覆盖有源模块、无源模块和柱状金属引线的多余封装成型材料；形成连接柱状金属引线的底座焊料凸块，并去除载体；将用电系统裸芯焊接在再布线层上，然后通过底部填充将用电系统裸芯封装固定在再布线层上。通过使用三维芯片堆叠技术，将供电系统直接集成在用电系统裸芯下方，提高了电力输送效率，增加了不同电压轨道的可用数量。

Description

一种集成供电系统封装件的封装方法 技术领域
本发明涉及半导体封装技术领域，特别是涉及一种集成供电系统封装件的封装方法。
背景技术
所有的计算和通信系统都需要供电系统。供电系统会将电源的高电压转换成系统中离散器件所需的许多不同的低电压。供电系统的效率决定了向下转换的电力损失，而供电轨数决定了可支持的离散电压供应或器件的数量。
目前的供电技术面临着如下挑战：
一、随着过程中节点的收缩，设备电压的减小，电力输送的效率会随之降低，使功率消耗更大。
二、添加更多的供电轨道需要复制更多的供电组件，如增加元件数量、增大电路板尺寸、增加电路板的层数、加大系统体积、成本和重量。
三、由于再布线层的线距、线宽的限制，需要增加封装尺寸。
因此，如何提高电力输送效率，增加不同电压轨道的可用数量，已成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术，本发明的目的在于提供一种集成供电系统封装件的封装方法，用于解决现有技术中的种种问题。
为实现上述目的及其他相关目的，本发明提供一种集成供电系统封装件的封装方法，所述封装件包括用电系统裸芯和位于所述用电系统裸芯下方的供电系统裸芯，所述封装方法包括以下步骤：
提供一载体；
在所述载体上形成再布线层；
在所述再布线层上形成柱状金属引线；
分别将供电系统裸芯的有源模块和无源模块焊接在所述再布线层上，所述再布线层实现有源模块和无源模块之间电连接，并提供多条对接所述用电系统裸芯的供电轨道；
将所述有源模块和无源模块以及所述柱状金属引线在所述再布线层上封装成型，并研磨掉覆盖所述有源模块、无源模块和柱状金属引线的多余封装成型材料；
形成连接所述柱状金属引线的底座焊料凸块，并去除所述载体；
通过多个焊接凸块将用电系统裸芯焊接在所述再布线层上，实现用电系统裸芯与多条所述供电轨道的对接，然后通过底部填充将所述用电系统裸芯封装固定在所述再布线层上。
可选地，所述供电系统裸芯为高压供电系统裸芯，将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压，并提供多条对接所述用电系统裸芯的低压供电轨道。
可选地，所述有源模块包括控制器和降压转换器，所述无源模块包括电容、电感和电阻。
可选地，所述有源模块与所述无源模块横向排列。
可选地，所述再布线层包括：金属连线、通孔以及设于所述金属连线和通孔周围的介电层，所述金属连线通过所述通孔实现与所述有源模块、无源模块和柱状金属引线的电连接以及多层金属连线之间的层间连接。
可选地，所述再布线层上设有凸块下金属层，所述有源模块、无源模块、柱状金属引线以及用电系统裸芯通过所述凸块下金属层与所述再布线层电连接。
可选地，所述柱状金属引线为金属针或金属柱。
可选地，所述柱状金属引线采用键合或电镀的方法在所述再布线层上形成。
可选地，所述封装成型的方法为压缩成型、传递模塑、液封成型、真空层压或旋涂。
可选地，将所述用电系统裸芯焊接在所述再布线层上的多个焊接凸块为微凸块。
如上所述，本发明的集成供电系统封装件的封装方法，具有以下有益效果：
本发明提供了一种将整个供电系统集成到封装中的新方法，通过使用三维芯片堆叠技术，提高了电力输送效率，增加了不同电压轨道的可用数量。
本发明采用现有的有源元件和无源模块形成2.5D中间层，再将用电系统裸芯如ASIC集成到2.5D中间层的顶部得到3D堆栈结构，通过直接在用电系统裸芯下方紧密集成供电系统裸芯，解决了现有供电系统面临的问题。供电系统裸芯能够提供数千条低压供电轨道与用电系统通过微凸块直接对接；由于集成了无源模块，可以消除PCB板的寄生电阻，提高了供电控制的供电效率和响应时间，通过减少压降和噪声提高了保真度，减少了所需的设计余量。
附图说明
图1显示为本发明实施例提供的集成供电系统封装件的封装方法示意图。
图2a-2f显示为本发明实施例提供的集成供电系统封装件的封装方法的工艺流程示意图。
元件标号说明
101      载体
1011     黏附层
200      再布线层
201      金属连线
202      介电层
301      柱状金属引线
401      有源模块
402      无源模块
4021     电感模块
4022     电容模块
501      底座焊料凸块
601      用电系统裸芯
602      焊接凸块
S1～S7   步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
为了克服现有技术中供电系统面临的问题，本发明提出了一种通过使用三维芯片堆叠技术将整个供电系统集成到封装中的新方法。
这种集成了供电系统的封装件包括用电系统裸芯和位于所述用电系统裸芯下方的供电系统裸芯；其中，所述供电系统裸芯包括有源模块、无源模块和再布线层，所述有源模块和无 源模块封装成型，所述再布线层位于封装成型的所述有源模块和无源模块之上，实现有源模块和无源模块之间电连接，并提供多条对接所述用电系统裸芯的供电轨道；所述用电系统裸芯通过多个焊接凸块与多条所述供电轨道对接，并封装固定在所述再布线层上；外部电源直接通过所述供电系统裸芯向所述用电系统裸芯供电。
请参阅图1，本实施例提供一种上述集成供电系统封装件的封装方法，包括以下步骤：
S1提供一载体；
S2在所述载体上形成再布线层；
S3在所述再布线层上形成柱状金属引线；
S4分别将供电系统裸芯的有源模块和无源模块焊接在所述再布线层上，所述再布线层实现有源模块和无源模块之间电连接，并提供多条对接所述用电系统裸芯的供电轨道；
S5将所述有源模块和无源模块以及所述柱状金属引线在所述再布线层上封装成型，并研磨掉覆盖所述有源模块、无源模块和柱状金属引线的多余封装成型材料；
S6形成连接所述柱状金属引线的底座焊料凸块，并去除所述载体；
S7通过多个焊接凸块将用电系统裸芯焊接在所述再布线层上，实现用电系统裸芯与多条所述供电轨道的对接，然后通过底部填充将所述用电系统裸芯封装固定在所述再布线层上。
下面通过附图2a-2f来详细说明上述封装方法的具体工艺流程。
首先，如图2a所示，提供一载体101。所述载体101的材料可以选自玻璃、不锈钢、硅、氧化硅、金属或陶瓷中的一种或多种，或其他类似物。所述载体101可以为平板型。例如，所述载体101可以为具有一定厚度的硅基圆形平板。本实施例中，在所述载体101表面形成黏附层1011用于黏附固定所述再布线层200。具体地，可以采用胶水或胶带的方式黏附所述再布线层200。后续去除所述载体101时，黏附层1011也一并去除。例如，黏附层1011可以是采用加热或UV解胶的双面胶带，剥离时可以一面采用UV解胶另一面采用加热解胶，或者一面采用加热解胶另一面直接撕去，两面胶带解除粘性的方法不同。或者，黏附层1011也可以是镭射解胶的牺牲层，形成这层牺牲层后，在牺牲层上涂胶水可以黏附固定所述再布线层200。剥离时，可采用镭射去除牺牲层，然后再清除胶水。牺牲层可以在载体101上采用CVD沉积，也可以涂覆LTHC(light to heat)材料得到，胶水可以采用化学试剂清除。
然后，在所述载体101上形成再布线层200，并在所述再布线层200上形成柱状金属引线301，如图2b所示。具体地，所述再布线层200可以包括：金属连线201、通孔以及设于所述金属连线201和通孔周围的介电层202，所述金属连线201通过所述通孔实现与所述有 源模块401、无源模块402和柱状金属引线301的电连接以及多层金属连线201之间的层间连接。其中，金属连线201的材料包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。例如，金属连线201可以为Cu线，制作Cu线的种子层可以为Ti/Cu层。形成所述金属连线201的方法可以包括电解镀、化学镀、丝网印刷中的一种或多种，或其他适合的金属沉积工艺。所述通孔的形成方法可以为激光钻孔、机械钻孔、反应离子刻蚀、纳米压印或其他适合的开孔方法。所述通孔的填充材料可以为焊料或Cu，填充方法可以为电解镀、化学镀、丝网印刷、引线键合或其他适合在通孔中填充导电材料的方法。
本实施例中，所述再布线层200上还设有凸块下金属层(UBM)，所述有源模块401、无源模块402和柱状金属引线301以及用电系统裸芯601通过所述凸块下金属层与所述再布线层200电连接。所述柱状金属引线301用于实现封装件与外部器件的电连接，在本实施例中，所述柱状金属引线301为竖直柱状的金属针或金属柱，可采用键合或电镀的方法在所述再布线层200上形成，例如电镀Cu螺柱或键合铜针等。
随后，如图2c所示，分别将供电系统裸芯的有源模块401和无源模块402焊接在所述再布线层200上，所述再布线层200实现有源模块401和无源模块402之间的电连接，并提供多条对接所述用电系统裸芯601的供电轨道。本实施例中，供电系统裸芯可以为高压供电系统裸芯，将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压，并提供多条对接所述用电系统裸芯的低压供电轨道。所述有源模块401可以包括控制器和降压转换器，所述无源模块402可以包括电容、电感和电阻，本实施例中，无源模块402包括电容模块4022、电感模块4021和电阻(图中未示出)等。有源模块401与电容模块4022、电感模块4021等无源模块402横向排列封装在同一平层中，便于再布线层200的电连接和布图设计，具体排布的位置可以根据实际需要进行设计，本发明对此不作限制。
接下来，如图2d所示，将所述有源模块401和无源模块402以及所述柱状金属引线301在所述再布线层200上封装成型，并研磨掉覆盖所述有源模块401、无源模块402和柱状金属引线301的多余封装成型材料。具体地，所述封装成型方法可以为压缩成型、传递模塑、液封成型、真空层压、旋涂或其他适合的方法。封装成型的材料可以为环氧类树脂、液体型热固性环氧树脂、塑料成型化合物或类似物。研磨的方法可以包括机械研磨、化学抛光、刻蚀中的一种或多种。
然后，如图2e所示，形成连接所述柱状金属引线301的底座焊料凸块501，并去除所述载体101。本实施例中，所述底座焊料凸块501可以是焊锡球、铜球或锡铜合金球等，本实 施例采用球状引脚栅格阵列(Ball Grid Array，BGA)焊球。所述封装件通过所述底座焊料凸块501可以实现在封装基底上的固定以及与外部器件的电连接。具体地，去除所述载体101的方法可以包括机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种，或其他适合的方法。本实施例中，可以通过解胶的方式去除黏附层1011，从而去除所述载体101。
最后，如图2f所示，通过多个焊接凸块602将用电系统裸芯601焊接在所述再布线层200上，实现与多条所述供电轨道的对接，然后通过底部填充将所述用电系统裸芯601封装固定在所述再布线层200上。本实施例中，所述用电系统裸芯可以为专用集成电路裸芯(ASIC Die)。具体地，所述用电系统裸芯601与所述再布线层200连接的多个焊接凸块602可以为微凸块(μ-Bumps)或常规凸块。所述底部填充可以为毛细管底部填充(CUF，Capillary Underfill)或成型材料底部填充(MUF，Molding UnderFill)。
本发明采用现有的有源元件和无源模块形成2.5D中间层，再将用电系统裸芯如ASIC集成到2.5D中间层的顶部得到3D堆栈结构，从而直接在用电系统裸芯下方紧密集成供电系统裸芯。外部高压电源可直接向封装件供电，封装件的供电系统将高电压转化为符合用电系统需要的电压，并通过多条供电轨道通过微凸块或凸块直接供给用电系统裸芯。采用本发明的技术方案，供电系统裸芯能够提供数千条低压供电轨道与用电系统通过微凸块直接对接；由于集成了无源模块，可以消除采用传统PCB板产生的寄生电阻，提高了供电控制的供电效率和响应时间，通过减少压降和噪声提高了保真度，减少了所需的设计余量，从而可有效的解决传统供电系统面临的问题。
综上所述，本发明通过使用三维芯片堆叠技术将整个供电系统集成到器件封装中，提高了电力输送效率，增加了不同电压轨道的可用数量，解决了现有供电系统面临的多种问题。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种集成供电系统封装件的封装方法，其特征在于，所述封装件包括用电系统裸芯和位于所述用电系统裸芯下方的供电系统裸芯，所述封装方法包括以下步骤：
    提供一载体；
    在所述载体上形成再布线层；
    在所述再布线层上形成柱状金属引线；
    分别将供电系统裸芯的有源模块和无源模块焊接在所述再布线层上，所述再布线层实现有源模块和无源模块之间电连接，并提供多条对接所述用电系统裸芯的供电轨道；
    将所述有源模块和无源模块以及所述柱状金属引线在所述再布线层上封装成型，并研磨掉覆盖所述有源模块、无源模块和柱状金属引线的多余封装成型材料；
    形成连接所述柱状金属引线的底座焊料凸块，并去除所述载体；
    通过多个焊接凸块将用电系统裸芯焊接在所述再布线层上，实现用电系统裸芯与多条所述供电轨道的对接，然后通过底部填充将所述用电系统裸芯封装固定在所述再布线层上。
  2. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述供电系统裸芯为高压供电系统裸芯，将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压，并提供多条对接所述用电系统裸芯的低压供电轨道。
  3. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述有源模块包括控制器和降压转换器，所述无源模块包括电容、电感和电阻。
  4. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述有源模块与所述无源模块横向排列。
  5. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述再布线层包括：金属连线、通孔以及设于所述金属连线和通孔周围的介电层，所述金属连线通过所述通孔实现与所述有源模块、无源模块和柱状金属引线的电连接以及多层金属连线之间的层间连接。
  6. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述再布线层上 设有凸块下金属层，所述有源模块、无源模块、柱状金属引线以及用电系统裸芯通过所述凸块下金属层与所述再布线层电连接。
  7. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述柱状金属引线为金属针或金属柱。
  8. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述柱状金属引线采用键合或电镀的方法在所述再布线层上形成。
  9. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：所述封装成型的方法为压缩成型、传递模塑、液封成型、真空层压或旋涂。
  10. 根据权利要求1所述的集成供电系统封装件的封装方法，其特征在于：将所述用电系统裸芯焊接在所述再布线层上的多个焊接凸块为微凸块。
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