WO2018157546A1 - 集成有供电传输系统的封装件的封装方法 - Google Patents

集成有供电传输系统的封装件的封装方法 Download PDF

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Publication number
WO2018157546A1
WO2018157546A1 PCT/CN2017/095386 CN2017095386W WO2018157546A1 WO 2018157546 A1 WO2018157546 A1 WO 2018157546A1 CN 2017095386 W CN2017095386 W CN 2017095386W WO 2018157546 A1 WO2018157546 A1 WO 2018157546A1
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Prior art keywords
metal
module
carrier
power transmission
transmission system
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PCT/CN2017/095386
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English (en)
French (fr)
Inventor
林章申
林正忠
何志宏
周祖源
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中芯长电半导体（江阴）有限公司
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Publication of WO2018157546A1 publication Critical patent/WO2018157546A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a packaging method of a package integrated with a power transmission system.
  • the power transmission system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power transmission system determines the power loss of the down conversion, and the number of power rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power rails requires copying more power components, such as increasing component count, increasing board size, increasing the number of boards, increasing system size, cost, and weight.
  • the present invention provides a package method for the above package integrated with a power transmission system, the package method comprising the following steps:
  • the active module and the passive module are disposed on the surface of the carrier formed with the first metal connection post, and form a second metal connection column on the surface of the active module and the passive module;
  • the power transmission system is adapted to convert a high voltage provided by an external power source into a plurality of different low voltages, and provide a plurality of low voltage power supply rails;
  • the power chip is disposed on the surface of the rewiring layer, and the power chip realizes docking with the low voltage power supply track via a plurality of micro bumps;
  • the first metal connection pillar on the surface of the carrier by an electroplating process comprises the following steps:
  • step 3 the back surface of the active module and the back surface of the passive module are bonding surfaces combined with the carrier.
  • the active module includes a controller and a buck converter;
  • the passive module includes a capacitor, an inductor, and a resistor.
  • the method for packaging the first metal connecting post, the active module, the passive module and the second metal connecting post by using a molding material comprises: compression molding, transfer Molding, hydroforming, vacuum lamination or spin coating.
  • the rewiring layer formed in step 5) includes: a metal wiring, a metal plug, and a dielectric layer disposed around the metal wiring and the metal plug, wherein the metal wiring is used to implement Electrical connection of the first metal connection post, the active module and the passive module, the metal plug is used to achieve an interlayer connection between the metal wires between layers.
  • the method of forming the metal wiring includes at least one of electroplating, electroless plating, and screen printing.
  • the surface of the rewiring layer is provided with a bump metal layer electrically connected to the metal wiring, the first metal connection pillar, the active module, the passive module, and the power supply A chip is connected to the rewiring layer via the bump metal layer.
  • step 6 a step of performing underfill on a region between the micro bumps at the bottom of the power chip to fix the power chip to the On the wiring layer.
  • the method further comprises the step of forming a layer of a molding material around the underfill material filled around the bottom and bottom of the power chip.
  • the packaging method of the package incorporating the power transmission system of the present invention has the following beneficial effects:
  • the power-on chip may be an Application Specific Integrated Circuit (ASIC).
  • ASIC Application Specific Integrated Circuit
  • the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the power transmission chip which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • FIG. 1 is a flow chart showing a packaging method of a package integrated with a power transmission system according to the present invention.
  • FIGS. 2 to 12 are schematic structural views showing steps in a packaging method of a package integrated with a power transmission system according to the present invention.
  • the present invention provides a packaging method for a package integrated with a power transmission system, the packaging method comprising the following steps:
  • the active module and the passive module are disposed on the surface of the carrier formed with the first metal connection post, and form a second metal connection column on the surface of the active module and the passive module;
  • the power transmission system is adapted to convert a high voltage provided by an external power source into a plurality of different low voltages, and provide a plurality of low voltage power supply rails;
  • the power chip is disposed on the surface of the rewiring layer, and the power chip realizes docking with the low voltage power supply track via a plurality of micro bumps;
  • step 1) referring to step S1 in FIG. 1 and FIG. 2, a carrier 11 is provided.
  • the material of the carrier 11 may be selected from one or more of glass, stainless steel, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 11 may be of a flat type.
  • the carrier 11 can be, but is not limited to, a glass circular plate having a certain thickness.
  • step 1) a step of forming a peeling layer 13 on the surface of the carrier 11 is further included.
  • the release layer 13 is used to adhere to a structure to be subsequently formed.
  • the release layer 13 may be a glue layer or a tape.
  • the release layer 13 is also removed.
  • the peeling layer 13 may be a double-sided tape which is heated or UV-debonded. When peeling off, one side may be UV-debonded on the other side, and the other side may be heated and de-bonded, or one side may be directly peeled off by heat-dissolving on the other side, and the double-sided tape is used to release the adhesive. The method is different.
  • the peeling layer 13 may also be a sacrificial layer of laser debonding.
  • the glue layer on the sacrificial layer may adhere to the structure to be formed subsequently; when peeling off, the sacrificial layer may be removed by laser, and then removed. glue.
  • the sacrificial layer may be deposited by CVD on the carrier 11, or may be coated with LTHC (1ight to heat) material, and the glue may be removed by chemical reagents.
  • step 2) referring to step S2 in FIG. 1 and FIG. 4, the first metal connection pillar 12 is on the surface of the carrier 11 by an electroplating process.
  • the peeling layer 13 is formed on the surface of the carrier 11, the first metal connecting post 12 and the subsequent structures formed on the surface of the carrier 11 are formed on the peeling layer 13 s surface.
  • the first metal connection post 12 on the surface of the carrier 11 by an electroplating process includes the following steps:
  • the dummy pad may be a plated seed layer
  • the position of the first metal connecting post 12 needs to be formed on the surface of the carrier 11 or the position of the first metal connecting post 12 needs to be formed on the surface of the carrier 11 and needs to be set.
  • the location of the active module and the passive module forms the virtual pad including the following steps:
  • the exposed metal layer is removed by an etching process, and the dummy pad is obtained by removing the photoresist layer.
  • the active module 14 and the passive module 15 involved in the step 3) may be of two types, one being the front and back sides of the active module 14 and the passive module 15
  • the front surface and the back surface are respectively provided with metal pads connected to the internal structure thereof, and the other is only the front surface of the active module 14 and the front surface of the passive module 15 are provided with metal pads connected to the internal structure thereof.
  • a metal pad is not disposed on the back surface of the active module 14 and the back surface of the passive module 15.
  • step 2-1 When the front and back sides of the active module 14 of the active module 14 and the front and back sides of the passive module 15 are provided with metal pads connected to the internal structure thereof, in step 2-1), The surface of the carrier 11 needs to form a position of the first metal connection pillar 12 and a position where an active module and a passive module need to be disposed at the same time to form a dummy pad; when only the front surface of the active module 14 and the passive The front surface of the module 15 is provided with a metal pad connected to its internal structure, that is, when the back surface of the active module 14 and the back surface of the passive module 15 are not provided with a metal pad, only the step 2-1) The surface of the carrier 11 needs to form the first metal connecting post 12 to form the dummy pad.
  • the material of the first metal connection pillar 12 may include one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the material of the dummy pad may also include one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the material of the first metal connection pillar 12 may be Cu, and the material of the dummy pad may be Ti/Cu.
  • step 3 referring to step S1 in FIG. 1 and FIG. 5, the active module 14 and the passive module 15 are disposed in the The carrier 11 is formed on the surface of the first metal connection pillar 12, and a second metal connection pillar 16 is formed on the surface of the active module 14 and the passive module 15.
  • the active module 14 can include a controller and a buck converter
  • the passive module 15 can include a capacitor 151, an inductor 152, and a resistor (not shown)
  • the active module 14 and the capacitor 151, the inductor 152 level of the passive module 15 such as the resistor can be laterally arranged in the same leveling layer, facilitating electrical connection and layout design with the subsequently formed rewiring layer, of course, the active module 14
  • the specific arrangement position of the passive module 15 can be designed according to actual needs, and the present invention does not limit this.
  • the back surface of the active module 14 and the back surface of the passive module 15 are combined surfaces of the carrier 11 , that is, the active module 14 and the passive
  • the module 15 is placed face up, and the second metal connection post 16 is connected to the active module 14 and the solder pad on the front surface of the passive module 15 to facilitate electrical connection with a subsequently formed rewiring layer.
  • the alloy layer may be formed by using a flux and using a high temperature reflow process to achieve the Soldering the metal pad of the back surface of the active module 14 and the back surface of the passive module 15 to the dummy pad to fix the active module 14 and the passive module 15 to the On the carrier 11; when there is no metal pad on the back surface of the active module 14 and the back surface of the passive module 15, the active module 14 and the above may be adhered by means of glue or double-sided tape or the like.
  • the passive module 15 is fixed to the carrier 11.
  • step 4 referring to step S4 in FIG. 1 and FIGS. 6 and 7, the first metal connecting post 12, the active module 14, the passive module 15 and the The second metal connecting post 16 is packaged and a portion of the molding material 17 is removed to expose the first metal connecting post 12 and the second metal connecting post 16 .
  • the first metal connection post 12, the active module 14, the passive module 15, and the first portion may be formed by processes such as compression molding, transfer molding, hydroforming, vacuum lamination, or spin coating.
  • the two metal connecting posts 16 are packaged and formed.
  • the molding material 17 may be an epoxy resin, a liquid type thermosetting epoxy resin, a plastic molding compound or the like.
  • a portion of the molding material 17 may be removed using one or more of mechanical grinding, chemical polishing, or etching.
  • step 5 referring to the step S5 in FIG. 1 and FIG. 8, a rewiring layer 18 is formed on the surface of the molding material 17, and the rewiring layer 18 places the first metal connecting pillars 12,
  • the source module 14 and the passive module 15 are electrically connected; the active module 14, the passive module 15 and the rewiring layer 18 together constitute a power transmission system; the power transmission system is adapted to provide an external power supply
  • the high voltage is converted into a number of different low voltages and provides multiple low voltage supply rails.
  • high voltage refers to a voltage higher than the voltage required for the later-mentioned power chip
  • low voltage as used herein means lower than the “high voltage”.
  • the voltage that is, the voltage required for the powered chip.
  • the rewiring layer 18 includes: a metal wiring 182, a metal plug, and a dielectric layer 181 disposed around the metal wiring 182 and the metal plug, wherein the metal wiring 182 is used to implement the Electrical connection of the first metal connection post 12, the active module 14 and the passive module 15, the metal plug being used to achieve an interlayer connection between the metal lines 182 between the layers.
  • the material of the metal wiring 182 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wiring 182 may be a Cu wire, and the seed layer of the Cu wire may be a Ti/Cu layer.
  • the method of forming the metal wiring 182 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • a through hole may be formed in the dielectric layer 181 by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting or other suitable opening method, and then the through hole is filled with a metal material.
  • the metal plug is formed; the material of the metal plug may be solder or Cu, and the filling method may be electrolytic plating, electroless plating, screen printing, wire bonding or other method suitable for filling a conductive material in a through hole.
  • the surface of the rewiring layer 18 is provided with a bump metal layer (not shown) electrically connected to the metal wiring 182, the first metal connection pillar 12, the active module 14, the The passive module 15 and the subsequently used power chip are connected to the rewiring layer 18 via the bump metal layer.
  • the first metal connection pillar 12, the active module 14, and the Both the passive module 15 and the power chip are connected to the metal wiring 182 in the rewiring layer 18 via the bump metal layer.
  • step 6 referring to step S6 in FIG. 1 and FIG. 9, a power chip 19 is provided, and the power chip 19 is disposed on the surface of the rewiring layer 18, and the power chip 19 is provided through multiple The microbumps 20 achieve abutment with the low voltage supply rail.
  • the power chip 19 may be soldered to the rewiring layer 18 via a plurality of microbumps 20 using processes such as ultrasonic bonding, thermocompression bonding, or conventional reflow soldering.
  • the powered chip 19 can be, but is not limited to, an ASIC Die.
  • a step of underfilling the region between the microbumps 20 at the bottom of the power chip 19 is further included to fix the power chip 19 to the rewiring.
  • the power chip 19 is fixed on the rewiring layer 18 by filling an underfill material 21 with a region between the micro bumps 20 at the bottom of the power chip 19, and the filling material may be For, but not limited to, underfill.
  • the underfill may be a CUF (Capillary Underfill) or a molding underfill (MUF, Molding UnderFill).
  • the method further includes forming a layer of the molding material 22 around the underfill material 21 around the underfill and the underfill. A step of.
  • step 7 referring to step S7 in FIG. 1 and FIGS. 11 and 12, the carrier 11 is peeled off to form solder bumps 23 connected to the first metal connection post 12.
  • the carrier 11 may be peeled off by one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, mechanical peeling; preferably, in the present embodiment, the peeling layer 13 may be removed by peeling off The carrier 11.
  • the structure after peeling off the carrier 11 is as shown in FIG.
  • the solder bumps 23 may be solder balls.
  • the solder bumps 23 use a Ball Grid Array (BGA).
  • BGA Ball Grid Array
  • the package is connected to an external power source through the solder bumps 23.
  • the structure in which the solder bumps 23 connected to the first metal post 12 are formed is as shown in FIG.
  • the present invention provides a packaging method for a package integrated with a power transmission system, the packaging method comprising the steps of: 1) providing a carrier; 2) using a plating process to form a first metal connection on the surface of the carrier a column; 3) disposing an active module and a passive module on a surface of the carrier on which the first metal connection post is formed, and forming a second metal connection pillar on the surface of the active module and the passive module 4) using a molding material to package the first metal connecting post, the active module, the passive module, and the second metal connecting post, and removing part of the molding material to expose the first a metal connection post and the second metal connection pillar; 5) forming a rewiring layer on the surface of the molding material, the rewiring layer connecting the first metal connection pillar, the active module, and the passive The module is electrically connected; the active module, the passive module and the rewiring layer together constitute a power transmission system; the power transmission system is adapted to convert a high voltage provided by an external power source
  • the invention has the following beneficial effects: (1) forming an active 2.5D interposer by using existing active components and passive components, and then integrating the electric chip into the active 2.5D intermediation through microbumps or other bump structures. On the board, a three-dimensional stack structure is obtained; wherein the power chip can be an Application Specific Integrated Circuit (ASIC); (2) in a three-dimensional stack structure, an active 2.5D interposer is used as a power transmission power chip.
  • ASIC Application Specific Integrated Circuit
  • the power transmission system of the entire system circuit board is realized by the power transmission chip, and the power transmission chip includes a controller and a buck converter ( Buck converter), capacitor (CAP(3T)), inductor (L(2T)) and resistor, thus eliminating all passive components on the system board;
  • buck converter in the power transfer chip can be generated Thousands of low-voltage power transmission tracks (power supply tracks) that are connected to the power chip by microbumps;
  • the package structure of the present invention integrates work including passive components Transmission chip, the package base may be eliminated Boards such as parasitic resistance on the PCB increase power transfer efficiency and improve response time for power control; (6) improve fidelity by reducing voltage drop and noise, thereby improving response time. Better fidelity performance improvements are achieved due to the need for less design margin.

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Abstract

一种集成有供电传输系统的封装件的封装方法，包括如下步骤：1)提供一载体（11）；2)采用电镀工艺在载体（11）表面形成第一金属连接柱（12）；3)将有源模块（14）及无源模块（15）设置于载体（11）形成有第一金属连接柱（12）的表面上，并在有源模块（14）及所述无源模块（15）表面形成第二金属连接柱（16）；4)将第一金属连接柱（12）、有源模块（14）、无源模块（15）及第二金属连接柱（16）封装成型；5)在塑封材料（17）表面形成再布线层（18）；6)将用电芯片（19）设置于再布线层（18）表面，用电芯片（19）经由多个微凸块（20）实现与低电压供电轨道的对接；7)剥离载体（11），形成与第一金属连接柱（12）相连接的焊料凸块（23）。通过使用三维芯片堆叠技术，提高了电力输送效率，增加了不同电压轨道的可用数量。

Description

集成有供电传输系统的封装件的封装方法 技术领域
本发明涉及半导体封装技术领域，特别是涉及一种集成有供电传输系统的封装件的封装方法。
背景技术
所有的计算和通信系统都需要供电传输系统。供电传输系统会将电源的高电压转换成系统中离散器件所需的许多不同的低电压。供电传输系统的效率决定了向下转换的电力损失，而供电轨道数决定了可支持的离散电压供应或器件的数量。
目前的供电技术面临着如下挑战：
一、随着过程中节点的收缩，设备电压的减小，电力输送的效率会随之降低，使功率消耗更大。
二、添加更多的供电轨道需要复制更多的供电组件，如增加元件数量、增大电路板尺寸、增加电路板的层数、加大系统体积、成本和重量。
三、由于再布线层的线距、线宽的限制，需要增加封装尺寸。
因此，如何提高电力输送效率，增加不同电压轨道的可用数量，已成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术，本发明的目的在于提供一种集成有供电传输系统的封装件的封装方法，用于解决现有技术中的种种问题。
为实现上述目的及其他相关目的，本发明提供一种上述集成有供电传输系统的封装件的封装方法，所述封装方法包括以下步骤：
1)提供一载体；
2)采用电镀工艺在所述载体表面第一金属连接柱；
3)将有源模块及无源模块设置于所述载体形成有所述第一金属连接柱的表面上，并在所述有源模块及所述无源模块表面形成第二金属连接柱；
4)使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型，并去除部分所述塑封材料以裸露出所述第一金属连接柱及所述第二金属连接柱；
5)在所述塑封材料表面形成再布线层，所述再布线层将所述第一金属连接柱、所述有源模块及所述无源模块电连接；所述有源模块、所述无源模块及所述再布线层共同构成供电传输系统；所述供电传输系统适于将外部电源提供的高电压转换成多个不同的低电压，并提供多条低电压供电轨道；
6)提供用电芯片，将所述用电芯片设置于所述再布线层表面，所述用电芯片经由多个微凸块实现与所述低电压供电轨道的对接；
7)剥离所述载体，形成与所述第一金属连接柱相连接的焊料凸块。
可选地，步骤1)与步骤2)之间还包括在所述载体表面形成剥离层的步骤；步骤2)中，所述第一金属连接柱形成于所述剥离层表面；步骤3)中，所述有源模块及所述无源模块设置于所述剥离层表面；步骤7)中通过去除所述剥离层以剥离所述载体。
可选地，用电镀工艺在所述载体表面第一金属连接柱包括如下步骤：
2-1)在所述载体表面需要形成所述第一金属连接柱的位置或在所述载体表面需要形成所述第一金属连接柱的位置及需要设置有源模块及无源模块的位置形成虚拟焊垫；
2-2)在所述载体表面及所述虚拟焊垫表面形成光刻胶层；
2-3)在所述光刻胶层内对应于需要形成所述第一连接柱的所述虚拟焊垫的位置形成通孔，所述通孔暴露出所述虚拟焊垫；
2-4)采用电镀工艺在所述通孔内形成所述第一金属连接柱；
2-5)去除所述光刻胶层。
可选地，步骤3)中，所述有源模块的背面及所述无源模块的背面为与所述载体相结合的结合面。
可选地，所述有源模块包括控制器及降压变换器；所述无源模块包括电容、电感及电阻。
可选地，步骤4)中，使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型的方法包括：压缩成型、传递模塑、液压成型、真空层压或旋涂。
可选地，步骤5)中形成的所述再布线层包括：金属连线、金属插塞及设置于所述金属连线及金属插塞周围的介电层，所述金属连线用于实现所述第一金属连接柱、所述有源模块及所述无源模块的电连接，所述金属插塞用于实现各层之间的所述金属连线之间的层间连接。
可选地，形成所述金属连线的方法包括电镀、化学镀及丝网印刷中的至少一种。
可选地，所述再布线层表面设置有与所述金属连线电连接的凸块金属层，所述第一金属连接柱、所述有源模块、所述无源模块及所述用电芯片经由所述凸块金属层与所述再布线层相连接。
可选地，步骤6)与步骤7)之间还包括在所述用电芯片底部的所述微凸块之间的区域进行底部填充的步骤，以将所述用电芯片固定于所述再布线层上。
可选地，在所述用电芯片底部所述微凸块之间的区域进行底部填充之后，还包括在所述用电芯片周围及底部填充的底部填充材料周围形成塑封材料层的步骤。
如上所述，本发明的集成有供电传输系统的封装件的封装方法，具有以下有益效果：
(1)采用现有的有源元件和无源元件形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(Application Specific Integrated Circuit，简称ASIC)。
(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题。
(3)整个系统电路板的功率传输系统由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容(CAP(3T))，电感(L(2T))和电阻，从而消除了系统板上所有的无源元件。
(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片。
(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间。
(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。
附图说明
图1显示为本发明的集成有供电传输系统的封装件的封装方法的流程示意图。
图2～图12显示为本发明的集成有供电传输系统的封装件的封装方法中各步骤的结构示意图。
元件标号说明
11       载体
12       第一金属连接柱
13       剥离层
14       有源模块
15       无源模块
151      电容
152      电感
16       第二金属连接柱
17       塑封材料
18       再布线层
181      金属连线
182      介电层
19       用电芯片
20       微凸块
21       底部填充材料
22       塑封材料层
23       焊料凸块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，本发明提供一种集成有供电传输系统的封装件的封装方法，所述封装方法包括以下步骤：
1)提供一载体；
2)采用电镀工艺在所述载体表面第一金属连接柱；
3)将有源模块及无源模块设置于所述载体形成有所述第一金属连接柱的表面上，并在所述有源模块及所述无源模块表面形成第二金属连接柱；
4)使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型，并去除部分所述塑封材料以裸露出所述第一金属连接柱及所述第二金属连接柱；
5)在所述塑封材料表面形成再布线层，所述再布线层将所述第一金属连接柱、所述有源模块及所述无源模块电连接；所述有源模块、所述无源模块及所述再布线层共同构成供电传输系统；所述供电传输系统适于将外部电源提供的高电压转换成多个不同的低电压，并提供多条低电压供电轨道；
6)提供用电芯片，将所述用电芯片设置于所述再布线层表面，所述用电芯片经由多个微凸块实现与所述低电压供电轨道的对接；
7)剥离所述载体，形成与所述第一金属连接柱相连接的焊料凸块。
在步骤1)中，请参阅图1中的S1步骤及图2，提供一载体11。
作为示例，所述载体11的材料可以选自玻璃、不锈钢、硅、氧化硅、金属或陶瓷中的一种或多种，或其他类似物。所述载体11可以为平板型。例如，所述载体11可以为但不仅限于具有一定厚度的玻璃圆形平板。
请参阅图3，步骤1)之后还包括在所述载体11表面形成剥离层13的步骤。
作为示例，所述剥离层13用于黏附固定后续要形成的结构。具体地，所述剥离层13可以为胶水层或胶带。后续去除所述载体11时，剥离层13也一并去除。例如，剥离层13可以是采用加热或UV解胶的双面胶带，剥离时可以一面采用UV解胶另一面采用加热解胶，或者一面采用加热解胶另一面直接撕去，两面胶带解除粘性的方法不同。或者，剥离层13也可以是镭射解胶的牺牲层，形成这层牺牲层后，在牺牲层上涂胶水可以黏附固定后续要形成的结构；剥离时，可采用镭射去除牺牲层，然后再清除胶水。牺牲层可以在载体11上采用CVD沉积，也可以涂覆LTHC(1ight to heat)材料得到，胶水可以采用化学试剂清除。
在步骤2)中，请参阅图1中的S2步骤及图4，采用电镀工艺在所述载体11表面第一金属连接柱12。
需要说明的是，当所述载体11表面形成有所述剥离层13时，所述第一金属连接柱12及后续提到的形成与所述载体11表面的结构均形成于所述剥离层13的表面。
作为示例，用电镀工艺在所述载体11表面第一金属连接柱12包括如下步骤：
2-1)在所述载体11表面需要形成所述第一金属连接柱12的位置或在所述载体11表面 需要形成所述第一金属连接柱12的位置及需要设置有源模块及无源模块的位置形成虚拟焊垫(未示出)；
2-2)在所述载体11表面及所述虚拟焊垫表面形成光刻胶层(未示出)；
2-3)通过曝光、显影在所述光刻胶层内对应于需要形成所述第一连接柱12的所述虚拟焊垫的位置形成通孔，所述通孔暴露出所述虚拟焊垫；
2-4)采用电镀工艺在所述通孔内形成所述第一金属连接柱12，此时，所述虚拟焊垫可以为电镀的种子层；
2-5)去除所述光刻胶层。
作为示例，步骤2-1)中，在所述载体11表面需要形成所述第一金属连接柱12的位置或在所述载体11表面需要形成所述第一金属连接柱12的位置及需要设置有源模块及无源模块的位置形成所述虚拟焊垫包括如下步骤：
2-1-1)采用金属溅射或化学镀在所述载体11表面形成金属层；
2-1-2)在所述金属层表面形成光刻胶层，通过曝光、显影在所述光刻胶层内形成通孔，所述通孔定义出所述虚拟焊垫之外的区域；
2-1-3)采用刻蚀工艺去除暴露的所述金属层，去除所述光刻胶层即得到所述虚拟焊垫。
需要说明的是，步骤3)涉及的所述有源模块14及所述无源模块15可以有两种类型，一种为所述有源模块14的正面与背面及所述无源模块15的正面与背面均设有与其内部结构相连接的金属焊垫，另一种为只有所述有源模块14的正面及所述无源模块15的正面设有与其内部结构相连接的金属焊垫，所述有源模块14的背面及所述无源模块15的背面没有设置金属焊垫。当所述有源模块14所述有源模块14的正面与背面及所述无源模块15的正面与背面均设有与其内部结构相连接的金属焊垫时，步骤2-1)中，在所述载体11表面需要形成所述第一金属连接柱12的位置及需要设置有源模块及无源模块的位置同时形成虚拟焊垫；当只有所述有源模块14的正面及所述无源模块15的正面设有与其内部结构相连接的金属焊垫，即所述有源模块14的背面及所述无源模块15的背面没有设置金属焊垫时，步骤2-1)中只需在所述载体11表面需要形成所述第一金属连接柱12的位置形成所述虚拟焊垫即可。
作为示例，所述第一金属连接柱12的材料可以包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。所述虚拟焊垫的材料同样可以包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。例如，所述第一金属连接柱12的材料可以为Cu，所述虚拟焊垫的材料可以为Ti/Cu。
在步骤3)中，请参阅图1中的S1步骤及图5，将有源模块14及无源模块15设置于所 述载体11形成有所述第一金属连接柱12的表面上，并在所述有源模块14及所述无源模块15表面形成第二金属连接柱16。
作为示例，所述有源模块14可以包括控制器和降压变换器，所述无源模块15可以包括电容151、电感152和电阻(未示出)，所述有源模块14与所述电容151、所述电感152级所述电阻等无源模块15可以横向地排列在同一平层中，便于与后续形成的再布线层的电连接和布图设计，当然，所述有源模块14余所述无源模块15的具体排布的位置可以根据实际需要进行设计，本发明对此不作限制。
需要说明的是，该步骤中，所述有源模块14的背面及所述无源模块15的背面为与所述载体11相结合的结合面，即所述有源模块14及所述无源模块15正面朝上放置，所述第二金属连接柱16与所述有源模块14及所述无源模块15正面的所述焊垫相连接，以便于与后续形成的再布线层的电连接。
需要进一步说明的是，当所述有源模块14的背面及所述无源模块15的背面均设有金属焊垫时，可以借助助焊剂，并利用高温回流工艺形成合金层，以实现所述有源模块14的背面及所述无源模块15的背面的所述金属焊垫与所述虚拟焊垫的焊接固定，从而将所述有源模块14及所述无源模块15固定于所述载体11上；当所述有源模块14的背面及所述无源模块15的背面均没有金属焊垫时，可以借助胶水或双面胶等粘合物将所述有源模块14及所述无源模块15固定于所述载体11上。
在步骤4)中，请参阅图1中的S4步骤及图6及图7，使用塑封材料17将所述第一金属连接柱12、所述有源模块14、所述无源模块15及所述第二金属连接柱16封装成型，并去除部分所述塑封材料17以裸露出所述第一金属连接柱12及所述第二金属连接柱16。
作为示例，可以采用压缩成型、传递模塑、液压成型、真空层压或旋涂等工艺将所述第一金属连接柱12、所述有源模块14、所述无源模块15及所述第二金属连接柱16封装成型。所述塑封材料17可以为环氧类树脂、液体型热固性环氧树脂、塑料成型化合物或类似物。
作为示例，可以采用机械研磨、化学抛光或刻蚀中的一种或多种去除部分所述塑封材料17。
在步骤5)中，请参阅图1中的S5步骤及图8，在所述塑封材料17表面形成再布线层18，所述再布线层18将所述第一金属连接柱12、所述有源模块14及所述无源模块15电连接；所述有源模块14、所述无源模块15及所述再布线层18共同构成供电传输系统；所述供电传输系统适于将外部电源提供的高电压转换成多个不同的低电压，并提供多条低电压供电轨道。
需要说明的是，此处所述的“高电压”是指高于后续提到的用电芯片所需电压的电压，此处所述的“低电压”是指低于所述“高电压”的电压，亦即所述用电芯片所需的电压。
作为示例，所述再布线层18包括：金属连线182、金属插塞及设置于所述金属连线182及金属插塞周围的介电层181，所述金属连线182用于实现所述第一金属连接柱12、所述有源模块14及所述无源模块15的电连接，所述金属插塞用于实现各层之间的所述金属连线182之间的层间连接。
作为示例，所述金属连线182的材料包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种，或其他适合的导电金属材料。例如，所述金属连线182可以为Cu线，制作Cu线的种子层可以为Ti/Cu层。形成所述金属连线182的方法可以包括电解镀、化学镀、丝网印刷中的一种或多种，或其他适合的金属沉积工艺。可以先通过激光钻孔、机械钻孔、反应离子刻蚀、纳米压印或其他适合的开孔方法在所述介电层181内形成通孔，然后再所述通孔内填充金属材料即可形成所述金属插塞；所述金属插塞的材料可以为焊料或Cu，填充方法可以为电解镀、化学镀、丝网印刷、引线键合或其他适合在通孔中填充导电材料的方法。
作为示例，所述再布线层18表面设置有与所述金属连线182电连接的凸块金属层(未示出)，所述第一金属连接柱12、所述有源模块14、所述无源模块15及后续用到的用电芯片均经由所述凸块金属层与所述再布线层18相连接，具体的，所述第一金属连接柱12、所述有源模块14、所述无源模块15及用电芯片均经由所述凸块金属层与所述再布线层18中的所述金属连线182相连接。
在步骤6)中，请参阅图1中的S6步骤及图9，提供用电芯片19，将所述用电芯片19设置于所述再布线层18表面，所述用电芯片19经由多个微凸块20实现与所述低电压供电轨道的对接。
作为示例，可以采用超声键合、热压键合或普通的回流焊等工艺将所述用电芯片19经由多个微凸块20焊接于所述再布线层18上。
作为示例，所述用电芯片19可以为但不仅限于专用集成电路裸芯(ASIC Die)。
请参阅图10，步骤6)之后还包括在所述用电芯片19底部的所述微凸块20之间的区域进行底部填充的步骤，以将所述用电芯片19固定于所述再布线层18上。具体的，通过在所述用电芯片19底部的所述微凸块20之间的区域填充底部填充材料21将所述用电芯片19固定于所述再布线层18上，所述填充材料可以为但不仅限于底部填充胶。
具体的，所述底部填充可以为毛细管底部填充(CUF，Capillary Underfill)或成型材料底部填充(MUF，Molding UnderFill)。
作为示例，在所述用电芯片19底部所述微凸块20之间的区域进行底部填充之后，还包括在所述用电芯片19周围及底部填充的底部填充材料21周围形成塑封材料层22的步骤。
在步骤7)中，请参阅图1中的S7步骤及图11及图12，剥离所述载体11，形成与所述第一金属连接柱12相连接的焊料凸块23。
作为示例，可以采用机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种剥离所述载体11；优选地，本实施例中，可以通过去除所述剥离层13以剥离所述载体11。剥离所述载体11之后的结构如图11所示。
作为示例，所述焊料凸块23可以为焊锡球，优选地，本实施例中，所述焊料凸块23采用球栅阵列结构(Ball Grid Array，BGA)。所述封装件通过所述焊料凸块23与外部电源相连接。形成与所述第一金属连接柱12相连接的焊料凸块23的结构如图12所示。
综上所述，本发明提供一种集成有供电传输系统的封装件的封装方法，所述封装方法包括如下步骤：1)提供一载体；2)采用电镀工艺在所述载体表面第一金属连接柱；3)将有源模块及无源模块设置于所述载体形成有所述第一金属连接柱的表面上，并在所述有源模块及所述无源模块表面形成第二金属连接柱；4)使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型，并去除部分所述塑封材料以裸露出所述第一金属连接柱及所述第二金属连接柱；5)在所述塑封材料表面形成再布线层，所述再布线层将所述第一金属连接柱、所述有源模块及所述无源模块电连接；所述有源模块、所述无源模块及所述再布线层共同构成供电传输系统；所述供电传输系统适于将外部电源提供的高电压转换成多个不同的低电压，并提供多条低电压供电轨道；6)提供用电芯片，将所述用电芯片设置于所述再布线层表面，所述用电芯片经由多个微凸块实现与所述低电压供电轨道的对接；7)剥离所述载体，形成与所述第一金属连接柱相连接的焊料凸块。本发明具有以下有益效果：(1)采用现有的有源元件和无源元件形成有源2.5D中介板，然后通过微凸块或其它凸块结构将用电芯片集成在有源2.5D中介板上，得到三维堆叠结构；其中，所述用电芯片可以是专用集成电路(Application Specific Integrated Circuit，简称ASIC)；(2)在三维堆叠结构中，有源2.5D中介板作为功率传输功率芯片，紧密集成于在用电芯片下方，解决了功率传输的问题；(3)整个系统电路板的功率传输系统由所述功率传输芯片实现，所述功率传输芯片包括控制器、降压变换器(buck converter)、电容(CAP(3T))，电感(L(2T))和电阻，从而消除了系统板上所有的无源元件；(4)所述功率传输芯片中的降压变换器可以产生成千上万低电压功率传输轨道(供电轨道)，这些低电压功率传输轨道通过微凸块对接用电芯片；(5)本发明的封装结构由于集成了包含无源元件的功率传输芯片，可以消除封装基 板例如PCB板上的寄生电阻，从而提高了功率传输效率，改善了功率控制的响应时间；(6)通过减少压降和噪声提高了保真度，从而改善了响应时间。由于需要更少的设计余量，可以获得更好的保真度性能改善。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (11)

  1. 一种集成有供电传输系统的封装件的封装方法，其特征在于，包括以下步骤：
    1)提供一载体；
    2)采用电镀工艺在所述载体表面第一金属连接柱；
    3)将有源模块及无源模块设置于所述载体形成有所述第一金属连接柱的表面上，并在所述有源模块及所述无源模块表面形成第二金属连接柱；
    4)使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型，并去除部分所述塑封材料以裸露出所述第一金属连接柱及所述第二金属连接柱；
    5)在所述塑封材料表面形成再布线层，所述再布线层将所述第一金属连接柱、所述有源模块及所述无源模块电连接；所述有源模块、所述无源模块及所述再布线层共同构成供电传输系统；所述供电传输系统适于将外部电源提供的高电压转换成多个不同的低电压，并提供多条低电压供电轨道；
    6)提供用电芯片，将所述用电芯片设置于所述再布线层表面，所述用电芯片经由多个微凸块实现与所述低电压供电轨道的对接；
    7)剥离所述载体，形成与所述第一金属连接柱相连接的焊料凸块。
  2. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤1)与步骤2)之间还包括在所述载体表面形成剥离层的步骤；步骤2)中，所述第一金属连接柱形成于所述剥离层表面；步骤3)中，所述有源模块及所述无源模块设置于所述剥离层表面；步骤7)中通过去除所述剥离层以剥离所述载体。
  3. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤2)中，采用电镀工艺在所述载体表面第一金属连接柱包括如下步骤：
    2-1)在所述载体表面需要形成所述第一金属连接柱的位置或在所述载体表面需要形成所述第一金属连接柱的位置及需要设置有源模块及无源模块的位置形成虚拟焊垫；
    2-2)在所述载体表面及所述虚拟焊垫表面形成光刻胶层；
    2-3)在所述光刻胶层内对应于需要形成所述第一连接柱的所述虚拟焊垫的位置形成通孔，所述通孔暴露出所述虚拟焊垫；
    2-4)采用电镀工艺在所述通孔内形成所述第一金属连接柱；
    2-5)去除所述光刻胶层。
  4. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤3)中，所述有源模块的背面及所述无源模块的背面为与所述载体相结合的结合面。
  5. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：所述有源模块包括控制器及降压变换器；所述无源模块包括电容、电感及电阻。
  6. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤4)中，使用塑封材料将所述第一金属连接柱、所述有源模块、所述无源模块及所述第二金属连接柱封装成型的方法包括：压缩成型、传递模塑、液压成型、真空层压或旋涂。
  7. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤5)中形成的所述再布线层包括：金属连线、金属插塞及设置于所述金属连线及金属插塞周围的介电层，所述金属连线用于实现所述第一金属连接柱、所述有源模块及所述无源模块的电连接，所述金属插塞用于实现各层之间的所述金属连线之间的层间连接。
  8. 根据权利要求7所述的集成有供电传输系统的封装件的封装方法，其特征在于：形成所述金属连线的方法包括电镀、化学镀及丝网印刷中的至少一种。
  9. 根据权利要求7所述的集成有供电传输系统的封装件的封装方法，其特征在于：所述再布线层表面设置有与所述金属连线电连接的凸块金属层，所述第一金属连接柱、所述有源模块、所述无源模块及所述用电芯片经由所述凸块金属层与所述再布线层相连接。
  10. 根据权利要求1所述的集成有供电传输系统的封装件的封装方法，其特征在于：步骤6)与步骤7)之间还包括在所述用电芯片底部的所述微凸块之间的区域进行底部填充的步骤，以将所述用电芯片固定于所述再布线层上。
  11. 根据权利要求10所述的集成有供电传输系统的封装件的封装方法，其特征在于：在所述用电芯片底部所述微凸块之间的区域进行底部填充之后，还包括在所述用电芯片周围及底部填充的底部填充材料周围形成塑封材料层的步骤。
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