CN112542451A - 用于集成专用集成电路和光学元件的嵌入式封装概念 - Google Patents
用于集成专用集成电路和光学元件的嵌入式封装概念 Download PDFInfo
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Abstract
本公开涉及用于集成专用集成电路和光学元件的嵌入式封装概念。本公开描述了光学封装体和制造方法。在一个实施方案中,控制器芯片与包括光电探测器(PD)和一个或多个发射器的光学元件一起被嵌入单个封装体中。
Description
相关专利申请
本申请要求2019年9月23日提交的新加坡专利申请号10201908828W的优先权权益,该新加坡专利申请以引用方式并入本文。
技术领域
本文所述的实施方案涉及微电子封装,更具体地涉及光学封装体。
背景技术
随着微电子设备变得越来越小且越来越便携,越来越多地结合传感器来检测与设备的使用相关联的环境或背景。这些传感器包括光传感器或接近传感器,它们可以检测环境光或与目标对象诸如用户的耳部或面部的接近度。在一个具体实施中,接近传感器可以包括光源和光电探测器(PD)。在应用中,PD可以通过测量来自光源的光量来检测与目标对象的接近度。
发明内容
本公开描述了光学封装体和制造方法,其中将控制器芯片与光学元件一起嵌入单个封装体中,这些光学元件包括一个或多个光电探测器(PD)和一个或多个发射器。在一个具体实施中,控制器芯片和光学元件在单个封装级中并列布置。在其他具体实施中,控制器芯片被嵌入在第一封装级中,并且光学元件在第二封装级中被堆叠在控制器芯片的顶部上。可以使用各种解决方案对光学元件进行布线,这些解决方案包括重新分布层(RDL)、印刷电路板(PCB)、垂直通孔和引线结合(wire bonding)。在一些具体实施中,将激光直接成型(LDS)技术用于电气线路连接。
附图说明
图1是根据一个实施方案的包括并列的控制器芯片和光学元件的光学封装体的示意性横截面侧视图。
图2是根据一个实施方案的制造图1的光学封装体的方法的工艺流程。
图3A至图3F是根据一个实施方案的制造图1的光学封装体的方法的示意性横截面侧视图。
图4A至图4B是根据实施方案的光学封装体的示意性横截面侧视图,其中光学元件堆叠在控制器芯片的顶部上。
图5A是根据实施方案的制造图4A至图4B的光学封装体的方法的工艺流程。
图5B是根据一个实施方案的制造图4A的光学封装体的方法的工艺流程。
图5C是根据一个实施方案的制造图4B的光学封装体的方法的工艺流程。
图6A是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件和第二封装级的激光直接成型。
图6B是根据一个实施方案的激光直接成型通孔的示意性横截面侧视图。
图7是根据一个实施方案的制造图6A的光学封装体的方法的工艺流程。
图8是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件,具有第一封装级和第二封装级的激光直接成型。
图9是根据一个实施方案的制造图8的光学封装体的方法的工艺流程。
图10A至图10F是根据一个实施方案的制造图8的光学封装体的方法的示意性横截面侧视图。
图11是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件,具有第一封装级和第二封装级的激光直接成型。
图12是根据一个实施方案的制造图11的光学封装体的方法的工艺流程。
图13A至图13H是根据一个实施方案的制造图11的光学封装体的方法的示意性横截面侧视图。
图14是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件,具有第一封装级和第二封装级的激光直接成型。
图15是根据一个实施方案的制造图14的光学封装体的方法的工艺流程。
图16A至图16H是根据一个实施方案的制造图14的光学封装体的方法的示意性横截面侧视图。
图17是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件和引线结合。
图18是根据一个实施方案的制造图17的光学封装体的方法的工艺流程。
图19是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件和引线结合。
图20是根据一个实施方案的制造图19的光学封装体的方法的工艺流程。
图21A至图21B是根据一个实施方案的耳塞的示意性侧视图。
图22是根据一个实施方案的听筒的示意性侧视图。
图23是根据一个实施方案的移动电话的示意性侧视图。
具体实施方式
实施方案描述了光学封装体和制造方法。具体地,光学封装体可以作为光传感器或接近传感器结合到便携式电子设备中。在一方面,根据实施方案的光学封装体在单个封装体中嵌入控制器芯片以及一个或多个光电探测器(PD)和一个或多个发射器。控制器芯片可以用于控制一个或多个PD和发射器的操作。例如,控制器芯片可以为专用集成电路(ASIC)或现场可编程门阵列(FPBA)。据观察,用于接近传感器的传统光学封装体将PD和光源安装到柔性电路上。柔性电路的该端部可以被安装到壳体,而柔性电路的相反端部被引导至定位于壳体中的其他位置的电路板上的控制器。据观察,此类构型可特别容易受到机械冲击以及外部电磁干扰(EMI)的影响。在一方面,与传统的光学封装体相比,根据实施方案的光学封装体和制造方法提供另选的布局和形状因数。在一些实施方案中,光学封装体可以提供EMI抑制,并且减轻机械冲击。例如,可以通过在成品封装体上添加EMI罩或金属盖来实现EMI抑制。通过将多个元件嵌入到单个封装体中,而不是使多个元件连接在柔性电路的相对的两个端部,可以减轻机械冲击。此外,根据实施方案的光学封装体可以被视为允许独立测试和校准的系统级封装。一些实施方案可以另外与柔性衬底和硅树脂模塑料相容。
在各种实施方案中,参照附图来进行描述。然而,某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中,示出许多具体细节诸如特定构型、尺寸和工艺等,以提供对实施方案的透彻理解。在其他情况下,未对熟知的半导体工艺和制造技术进行特别详细地描述,以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此,整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外,特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在…上方”、“到”、“在…之间”和“在…上”可以指一层相对于其他层的相对位置。一层在另一层“上方”或“上”或者结合(bond)“到”另一层或者与另一层“接触”可以为直接与其他层接触或可以具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
如本文所用,术语“布线层”(routing layer)可以指包括单层结构和多层结构的各种布线,包括重新分布层(RDL)、印刷电路板(PCB)和金属迹线层,诸如通过激光直接成型形成的那些布线。本文所用的术语“发射器”包括发光二极管(LED),包括垂直腔表面发射激光器(VCSEL)。
在以下描述中,描述了可以共享类似的材料、布置或工艺的各种构型和制造顺序。为了清楚和简洁起见,在随后的例示和过程中不一定以相同的细节描述类似的特征。因此,应当理解,相对于特定例示的特定描述也可以适用于共享相同或类似特征的另选的构型和例示。
现在参考图1,根据一个实施方案,提供了光学封装体100的横截面侧视图,该光学封装体包括并列的控制器芯片120和光学元件,这些光学元件包括一个或多个发射器140和PD 130。例如,多个不同的发射器140可以被设计成以不同的波长或强度发射。在一个实施方案中,光学封装体100包括背侧布线层102,该背侧布线层包括顶侧103和底侧104,以及在背侧布线层102的顶侧103上的印刷电路板(PCB)芯110。PCB芯110可以包括多个垂直通孔112和多个腔115。控制器芯片120面朝上定位于多个腔115的第一腔内,并且光电探测器(PD)130定位于多个腔115的第二腔内。模塑料150将控制器芯片120封装在第一腔115内,并且将PD 130封装在第二腔115内。模塑料150可以由包括环氧树脂的合适的模材料以及更柔性的材料诸如硅树脂形成。前侧布线层160定位于控制器芯片120、模塑料150、PCB芯110的顶部上。孔口162在PD 130上方的前侧布线层160内形成。光学封装体100可以附加包括在背侧布线层102的底侧104上的多个焊料凸块170,例如,用于安装在电子设备的主板或其他系统元件上。
根据实施方案的光学封装体100可以包括一个或多个发射器140和一个或多个PD130。在图1所示的具体实施方案中,一个或多个发射器140定位于相应的腔115内,并且与PD130类似,相应的孔口162在相应的发射器140上方在前侧布线层160内形成。如图所示,孔口162的最大宽度可以小于对应的光学元件(例如,发射器、PD)的顶部表面的最大宽度。
根据实施方案,PCB芯110可以为层压体114。例如,PCB芯110可以为玻璃纤维织造布和聚合物(例如,树脂)的复合物。PCB芯110可以由包括FR4、预浸料、聚酰亚胺等的各种合适的PCB材料形成。PCB芯110可以是刚性的或柔性的。垂直通孔112可以为铜柱,例如在钻通穿过PCB芯110的通孔之后使用镀覆技术形成的铜柱。PCB芯110可以包括顶侧接地焊盘116和底侧接地焊盘118。
根据实施方案的光学元件可以为垂直元件,包括顶部电极和底部电极。具体地,PD130可以具有顶部电极132和底部电极134,并且发射器可以具有顶部电极142和底部电极144。前侧布线层160可以包括在PD 130的顶部电极132和发射器140的顶部电极142上形成,并且可以直接在它们之上的接触焊盘165。接触焊盘165还可以在面朝上的控制器芯片120的接触焊盘122和垂直通孔112或顶侧接地焊盘116上形成,并且可以直接在它们之上。
在诸如图1所示的实施方案中,前侧布线层160可以为前(front)重新分布层(RDL),该前重新分布层可以使用薄膜处理技术以逐层工艺直接在下层结构上形成。例如,前RDL可以包括一条或多条金属迹线166、一个或多个介电层164、通孔168,以及接触焊盘165。RDL可以由合适的材料形成。例如,介电层164可以由可光成像的介电材料形成,包括聚合物(例如,聚酰亚胺、环氧树脂、环氧共混物等)或无机材料(例如,氧化物、氮化物),而金属迹线166和通孔168可以由包括铜的合适的金属形成。类似地,接触焊盘165可以由包括铜的一种或多种金属形成。
在诸如图1所示的实施方案中,背侧布线层102为RDL。背侧布线层102可以与先前描述的前侧布线层160类似地形成。背侧布线层102可以包括一个或多个介电层107、通孔108、接触焊盘109,以及可选的金属迹线106。在一个实施方案中,一个或多个介电层107由与模塑料150相同的材料形成,并且可以与模塑料150同时形成。根据实施方案,PD 130具有电连接到背侧布线层102的底部电极134。类似地,每个发射器140具有电连接到背侧布线层102的底部电极144。背侧布线层102的通孔108可以穿过介电层107形成,以接触PD 130和发射器140。介电层107可以与模塑料150分开或为该模塑料的一部分。在一个实施方案中,通孔108延伸穿过模塑料150以分别接触PD 130和发射器140的底部电极134、144,并且可以可选地延伸穿过一个或多个附加的介电层107。通孔108可以另外接触金属迹线106或PCB芯110的底侧接地焊盘118。
图2是根据一个实施方案的制造图1的光学封装体的方法的工艺流程。图3A至图3F是根据一个实施方案的制造图1的光学封装体的方法的示意性横截面侧视图。为了清楚和简洁起见,在下面的描述中一起描述图2和图3A至图3F的结构和工艺流程。
在操作2010处,将PCB芯110放置在承载衬底200上。如图3A所示,承载衬底200可以包括支承衬底202和粘合剂层204。然后,在操作2020处,将控制器芯片120和光学元件(例如,PD 130、发射器140)放置到PCB芯110中的腔115中,如图3B所示。在一个实施方案中,腔115比控制器芯片120更深,并且光学元件较高,使得存在间隙高度。
现在参考图3C,在操作2030处,例如使用模塑料150将控制器芯片120和光学元件封装在PCB芯110中。在图3C所示的具体实施方案中,模塑料150填充腔115内尚未被控制器芯片120和光学元件占据的剩余体积,并且可以(在该处理阶段)另外覆盖包括将作为底侧接地焊盘118的部分的PCB芯110的顶部表面。然后在操作2040处可以移除承载衬底200,以在发射器140和PD 130的顶部电极142、132处暴露顶侧接地焊盘116、控制器芯片120,以及接触焊盘122。
然后在操作2050处形成前侧布线层160。如图3E所示,前侧布线层160为包括一条或多条金属迹线166、一个或多个介电层164、通孔168和接触焊盘165的RDL。在前侧布线层160中另外形成孔口162以暴露光学元件的顶部表面。
然后在操作2060处形成背侧布线层102。如图3F所示,背侧布线层102为包括一个或多个介电层107、通孔108和接触焊盘109以及可选的一条或多条金属迹线106的RDL。如图3D至图3F所示,背侧布线层102可以包括模塑料150的一部分。因此,背侧布线层102的形成可以包括从操作2030开始形成穿过模塑料150的覆盖PCB芯110的现有部分的通孔108。还可以形成附加的介电层107。介电层107可以由合适的材料形成,包括模塑料150材料、聚合物、氧化物、氮化物等。然后将焊料凸块170放置到接触焊盘109上。
图4A至图4B是根据实施方案的光学封装体100的示意性横截面侧视图,其中光学元件堆叠在控制器芯片120的顶部上。在每个实施方案中,光学封装体100包括在第一封装级180的顶部上的第一(下部)封装级180和第二(上部)封装级480。需注意,图4A至图4B所示的每个实施方案中的第一封装级180可以类似于图1的光学封装体100,其中图4A至图4B的第二封装级480使用另选的材料和工艺形成。
在一个实施方案中,诸如图4A至图4B所示,光学封装体100包括第一封装级180,该第一封装级包括包含顶侧103和底侧104的背侧布线层102,以及在背侧布线层102的顶侧103上的控制器芯片120。第一封装级180在控制器芯片120的顶部上附加包括前侧布线层160,以及在前侧布线层160和背侧布线层102之间延伸的第一多个垂直通孔112。除光学元件之外,第一封装级180可以基本上类似于图1的光学封装体100。
仍参考图4A至图4B,第二封装级480可以包括安装在前侧布线层160上并且与其电接触的一个或多个PD 130,以及安装在前侧布线层160上并且与其电接触的一个或多个发射器140。顶侧布线层460还定位于一个或多个PD 130和发射器140上并且与其电接触,并且第二多个垂直通孔412在顶侧布线层460和前侧布线层160之间延伸。孔口162在相应的发射器140和PD 130上方的顶侧布线层460内形成,类似于先前描述的孔口162。
在图4A至图4B所示的每个实施方案中,控制器芯片120在背侧布线层102上且面朝上。类似于图1,在图4A至图4B所示的每个实施方案中,第一封装级180可以在背侧布线层102的顶侧103上包括PCB芯110,其中PCB芯110包括第一多个垂直通孔112和腔115,其中控制器芯片120在腔115内且面朝上。PCB芯410可以包括顶侧接地焊盘416和底侧接地焊盘418。
顶侧布线层460可以为顶部重新分布层(RDL),该RDL可以逐层工艺在下层结构上形成。例如,顶部RDL可以包括一条或多条金属迹线466、一个或多个介电层464、通孔468,以及接触焊盘465。接触焊盘465在PD 130的顶部电极132和发射器140的顶部电极142上形成并且可以直接在它们之上。RDL可以由合适的材料形成。例如,介电层464可以由可光成像的介电材料形成,包括聚合物(例如,聚酰亚胺、环氧树脂、环氧共混物等)或无机材料(例如,氧化物、氮化物),而金属迹线466和通孔468可以由包括铜的合适的金属形成。类似地,接触焊盘465可以由包括铜的一种或多种金属形成。
参考图4A,第二封装级480可以类似于第一封装级180形成。在一个实施方案中,第二封装级480包括在前布线层160上的第二PCB芯410。类似于PCB芯110,第二PCB芯410包括多个垂直通孔412和多个腔415,并且每个PD 130和发射器140位于相应的腔415内。第二封装级480可以与第一封装级180基本上分开制造,然后结合在一起。在一个实施方案中,第二封装级480与第一封装级180混合结合。例如,这可以在面板级发生。混合结合(hybridbonding)可以包括PCB芯410和前侧布线层160之间的多个金属-金属结合(metal-metalbond)。例如,金属-金属结合可以在PCB芯410的底侧接地焊盘418或垂直通孔412和/或光学元件的底部电极144、134与前侧布线层160的金属迹线166(包括接触焊盘169)或通孔168之间形成。氧化物-氧化物结合(oxide-oxide bond)可以在PCB芯410的介电层164和PCB芯410的介电层之间形成,该介电层可以为主体414的表面层或一部分。另选地,第二封装层480用多个导电接头,诸如导电膏、导电膜或焊料凸块,被混合结合到第一封装级180。在一个实施方案中,焊料凸块(未示出)用于结合PCB芯410的底侧接地焊盘418或垂直通孔412以及前侧布线层160的金属迹线166或通孔168。
参考图4B,第二封装级480可以在第一封装级180上形成,例如使用第一封装级180作为重构衬底。在此类实施方案中,PD 130、发射器140和第二多个垂直通孔412可以被封装在模塑料490中。顶侧布线层460可以类似于图4A的顶侧布线层460形成。
图5A是根据实施方案的制造图4A至图4B的光学封装体的方法的工艺流程。在操作5010处,第一封装级180形成为包括封装在PCB芯110中的控制器芯片120。除光学元件之外,该工艺流程可以与关于图1至图3F所示和所描述的基本上相同。然后,取决于第二封装级480的结构,制造顺序可以采取不同的路径。在一个实施方案中,在操作5020处,第二封装级480被结合到第一封装级180上。例如,这可以对应于图4A所示的实施方案,其中第二封装级480包括封装在PCB芯410内的光学元件。在一个实施方案中,在操作5060处,第二封装级480在第一封装级180上形成。例如,这可以对应于图4B所示的实施方案,其中第二封装级包括封装在模塑料490内的光学元件。在另外的变型中,该模塑料可以为激光直接成型相容性模塑料。
现在参考图5B,提供了根据一个实施方案的制造图4A的光学封装体的方法的工艺流程。在操作5022处,将PCB芯410放置在承载衬底上。在操作5024处,将光学元件(例如,一个或多个PD 130和一个或多个发射器140)放置在PCB芯410中的腔415内。然后在操作5026处,用模塑料450将光学元件封装在PCB芯410中。此时,在操作5028处可以可选地形成顶侧布线层460,然后在操作5030处移除载体衬底。然后在操作5032处可以可选地在移除承载衬底之后暴露的表面上形成底侧接地焊盘418或附加的布线。然后在操作5034处将第二封装级480结合到第一封装级180。例如,这可以是混合结合或与导电凸块诸如焊料凸块的结合。在一个变型中,可以在将第二封装级480结合到第一封装级180之后形成顶侧布线层460。
图5C是根据一个实施方案的制造图4B的光学封装体的方法的工艺流程。在操作5062处,将光学元件(例如,一个或多个PD 130和一个或多个发射器140)放置到第一封装级180的前侧布线层160上。例如,可以使用导电凸块诸如导电膜、糊剂、焊料凸块等来结合光学元件。如图所示,底部电极144、134被结合到前侧布线层160的金属迹线166(或接触焊盘169)或通孔168。然后在操作5064处,用模塑料490将光学元件封装在前侧布线层160上。在一些实施方案中,模塑料490可以是不透明的,例如黑色。在一些实施方案中,然后在操作5066处形成垂直通孔412,其中先蚀刻模塑料490,然后镀覆垂直通孔412。另选地,可以在用模塑料490封装之前形成垂直通孔412。例如,这可以通过用焊料将铜引脚镀覆或群结合到前侧布线层160来实现。然后可以在模塑料490和光学元件上形成第二封装级顶侧布线层460,如先前在操作5068处所述。
如各种实施方案中所述,模塑料可以用于将光学元件封装在第二封装级中。此外,虽然已经在至少第一封装级中描述和示出了PCB芯110,但是根据实施方案,这不是必需的,并且与光学元件类似,控制器芯片可以另选地用模塑料密封。在另一个变型中,用于封装光学元件和/或控制器芯片的模塑料可以为激光直接成型(LDS)相容性材料。这样,LDS成型可以用于通过模塑料或在模塑料上形成各种互连结构,包括垂直通孔和布线层(包括接触焊盘)。
根据实施方案的LDS相容性模塑料可以包括基质材料和分散在基质材料中的LDS添加剂。例如,LDS添加剂可以为非导电金属有机化合物。这可以包括各种金属氧化物组合物,所述各种金属氧化物组合物可以与基质材料(例如,树脂)混合(例如,复合)。在一个示例性实施方案中,LDS添加剂是与基质材料复合的分散的氧化锡组合物。实施方案不限于氧化锡,并且可以使用多种其他非导电金属有机化合物,包括其他复合的金属氧化物。
可以将多种有机材料用于基质材料,这可以取决于暴露的温度。低温材料包括聚碳酸酯(PC)和丙烯腈丁二烯苯乙烯(ABS)。可以承受焊接温度的中温材料包括聚己内酰胺(PA6/6)和聚邻苯二甲酰胺(PPA)。几乎可以承受任何焊接的聚醚醚酮(PEEK)的高温材料。其他合适的材料可以包括聚丙烯(PP)、聚对苯二甲酸乙二醇酯(PET)、聚对苯二甲酸丁二醇酯(PBT)、聚苯硫醚(PPS),以及液晶聚合物(LCP)。
选择LDS添加剂和激光参数,使得在将激光施加于模塑料时非导电金属有机化合物中的元素金属与该化合物分离并且形成成核颗粒,从而形成对应于激光图案的导电路径。然后可以将成核颗粒用作随后的化学镀工艺的成核层,以完全形成互连结构。可以通过化学镀工艺形成各种金属层,包括金、镍、银、锌、锡等。
图6A是根据一个实施方案的光学封装体100的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片120的顶部上的光学元件和第二封装级激光直接成型。图6A所示的实施方案基本上类似于关于图4B所示和描述的实施方案,不同之处在于模塑料491是包括分散的非导电金属有机化合物的LDS相容性材料。在此类构型中,LDS可以用于形成迹线布线497以及垂直通孔493。另选地,迹线布线497可以类似于金属迹线466形成。在一个实施方案中,顶侧布线层460包括迹线布线497,该迹线布线包括在分散的非导电金属有机化合物中的金属的金属颗粒的成核层。类似地,垂直通孔493可以包括在分散的非导电金属有机化合物中的金属的金属颗粒的成核层。迹线布线497和垂直通孔493两者可以附加包括块状导电层(例如,铜),该块状导电层镀覆在金属颗粒的成核层的顶部上。迹线布线497和垂直通孔493可以其他方式具有与金属迹线466和垂直通孔412类似的布局和连接。
简要地参考图6B,示出了示例性垂直通孔693,该示例性垂直通孔在包括顶侧602和底侧604的LDS相容性模塑料600中形成。如图所示,可以使用激光图案沿将成为垂直通孔693的模塑料600的侧壁形成金属成核层610。另外,成核层612、614可以在模塑料的顶侧和底侧上形成以支承附加的电布线层。在例示的实施方案中,垂直通孔693填充有镀覆金属620。同样,在一些实施方案中,镀覆金属可以在模塑料的顶侧和底侧上形成的成核层612、614上形成,以形成迹线布线或接地/接触焊盘。图6B所示的示例性垂直通孔693和成核层旨在用作LDS相容性模塑料600的激光图案化的示例性例示,并且可以利用此类材料在本文所述的各种实施方案中实现。
在图6A所示的具体实施方案中,第一封装级180包括在背侧布线层102的顶侧上的PCB芯110,以及在PCB芯110中的腔115内且面朝上的控制器芯片120。PD 130、发射器140和第二多个垂直通孔493被封装在第二级模塑料491中,该第二级模塑料为包括分散的非导电金属有机化合物的LDS相容性材料。顶侧布线层460包括迹线布线497,该迹线布线可选地包括在分散的非导电金属有机化合物中的金属的金属颗粒的成核层。第二多个垂直通孔493可以类似地用金属颗粒的成核层形成。
图7是根据一个实施方案的制造图6A的光学封装体的方法的工艺流程。在操作7010处,第一封装级180形成为包括封装在PCB芯110中的控制器芯片120,如先前所述。在操作7020处,将光学元件(PD和发射器)放置在第一封装级180的前侧布线层160上。例如,前侧布线层160可以为RDL。然后在操作7030处用LDS相容性模塑料491封装光学元件。在一个实施方案中,然后在操作7040处在模塑料491中形成垂直通孔493。垂直通孔493的形成可以包括在模塑料491处引导激光以形成金属颗粒的成核层,随后进行化学镀操作以在成核层的顶部上形成垂直通孔493的块状金属层。然后在操作7050处在模塑料491上形成顶侧布线层(例如,迹线布线497)。例如,还可以通过将激光图案施加于模塑料491的表面,然后在金属颗粒的成核层上电镀块状金属层图案来形成顶侧布线层(例如,迹线布线497)。另选地,可以类似于金属迹线466形成顶侧布线层(例如,迹线布线497)。
现在参考图8,根据实施方案,提供了光学封装体100的横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件,具有第一封装级和第二封装级的LDS。图8所示的实施方案在若干方面与图6A所示的实施方案不同。需注意,第一封装级180用LDS相容性模塑料411形成。另外,所使用的处理顺序导致控制器芯片120在背侧布线层102上且面朝下,该背侧布线层可以可选地是印刷电路板(PCB)。在例示的实施方案中,控制器芯片120被封装在LDS相容性模塑料411中。前侧布线层160可以附加包括迹线布线467,该迹线布线包括在LDS相容性模塑料411中的分散的非导电金属有机化合物中的金属的金属颗粒的成核层。同样,可以类似地形成垂直通孔413。
图9是根据一个实施方案的制造图8的光学封装体的方法的工艺流程。图10A至图10F是根据一个实施方案的制造图8的光学封装体的方法的示意性横截面侧视图。为了清楚和简洁起见,在下面的描述中一起描述图9和图10A至图10F的结构和工艺流程。在操作9010处,控制器芯片120可以被安装在背侧布线层102上,在一个实施方案中,该背侧布线层可以为PCB。如图10A所示,控制器芯片120可以面朝下安装,其中接触焊盘122结合到背侧布线层102或PCB的接地焊盘105或通孔107。在一个实施方案中,导电膜、导电胶或焊料凸块有利于结合。然后在操作9020处,将控制器芯片与LDS相容性模塑料411封装在一起。
现在参考图10B,在操作9030处,在模塑料内形成垂直通孔413,并且在操作9040处,在模塑料上形成前侧布线层160。垂直通孔413可以与接地焊盘105接触。前侧布线层160可以包括使用LDS形成的单层迹线布线467,但是可以可选地包括附加的电介质和金属布线层。另选地,可以在用模塑料411密封之前形成垂直通孔413。例如,这可以通过用焊料将铜引脚镀覆或群结合到背侧布线层102来实现。
然后,在操作9050处,将包括PD 130和发射器140的光学元件放置到前侧布线层160上,如图10C所示。在一个实施方案中,这可以使用导电膜、导电膏或焊料结合(solderbonding)来实现,使得底部电极144、134被结合到迹线布线467并且与其电连接。
然后,在操作9060处,可以用第二LDS相容性模塑料491来封装光学元件,如图10D所示。现在参考图10E,在操作9070处在模塑料491内形成垂直通孔493,并且在操作9080处在模塑料491上形成顶侧布线层460。垂直通孔493可以与迹线布线467接触。顶侧布线层460可以可选地包括使用LDS形成的单层迹线布线497,但是可以可选地包括或使用另选的技术形成附加的电介质和金属布线层。另外,孔口162用顶侧布线层460形成以暴露光学元件的顶部表面。如图所示,迹线布线497可以在光学元件的顶部电极132、142上形成并且与其电接触。然后可以将焊料凸块170放置在接触焊盘109上,如图10F所示,以用于光学封装体100的进一步系统集成。
图11是根据一个实施方案的光学封装体100的另一个变型的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片120的顶部上的光学元件,具有第一封装级和第二封装级的激光直接成型。图11基本上类似于图8,不同之处在于制造方法可以是无衬底的,并且背侧布线层102可以相反地由RDL而不是PCB形成。图12是根据一个实施方案的制造图11的光学封装体的方法的工艺流程。图13A至图13H是根据一个实施方案的制造图11的光学封装体的方法的示意性横截面侧视图。为了清楚和简洁起见,在下面的描述中一起描述图11的结构以及图12和图13A至图13H的工艺流程和结构。在操作1210处,将控制器芯片120放置在承载衬底200上。如图13A所示,在操作1220处,可以将控制器芯片面朝下放置在承载衬底上,然后用LDS相容性模塑料411来封装。
现在参考图13B,在操作1230处在模塑料411内形成垂直通孔413,并且在操作1240处在模塑料411上形成前侧布线层160。前侧布线层160可以包括使用LDS形成的单层迹线布线467,但是可以可选地包括附加的电介质和金属布线层。然后,在操作1250处,将包括PD130和发射器140的光学元件放置到前侧布线层160上,如图13C所示。在一个实施方案中,这可以使用导电膜、导电膏或焊料结合来实现,使得底部电极144、134被结合到迹线布线467并且与其电连接。
然后,在操作1260处,可以用第二LDS相容性模塑料491来封装光学元件,如图13D所示。现在参考图13E至图13F,在操作1270处移除载体衬底,然后在操作1280处形成可以为RDL的背侧布线层102。如图所示,背侧布线层102可以包括介电层107、多个贯穿通孔108,以及接触焊盘109。在一个实施方案中,介电层107为可光成像的聚合物,并且可以为模塑料材料。
现在参考图13G,在操作1290处在模塑料491内形成垂直通孔493,并且在操作1292处在模塑料491上形成顶侧布线层460。顶侧布线层460可以包括使用LDS形成的单层迹线布线497,但是可以可选地包括附加的电介质和金属布线层。另外,孔口162用顶侧布线层460形成以暴露光学元件的顶部表面。如图所示,迹线布线497可以在光学元件的顶部电极132、142上形成并且与其电接触。然后可以将焊料凸块170放置在接触焊盘109上,如图13H所示,以用于光学封装体100的进一步系统集成。
图14是根据一个实施方案的光学封装体的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件,具有第一封装级和第二封装级的激光直接成型。图14的光学封装体100可以类似于包括LDS的其他光学封装体,不同之处在于图14所示的光学封装体100可以使用最后集成有控制器芯片120的无衬底封装方法来制造。图15是根据一个实施方案的制造图14的光学封装体的方法的工艺流程。图16A至图16H是根据一个实施方案的制造图14的光学封装体的方法的示意性横截面侧视图。为了清楚和简洁起见,在下面的描述中一起描述图14的结构以及图15和图16A至图16H的工艺流程和结构。
在操作1510处,将光学元件放置在承载衬底200上。如图16A所示,可以将光学元件的顶部电极142、132面朝下放置在承载衬底上,然后在操作1520处用LDS相容性模塑料491来封装。现在参考图16B,在操作1530处在模塑料491内形成垂直通孔413,并且在操作1540处在模塑料491上形成前侧布线层160。如图16C所示,前侧布线层160可以为包括一个或多个介电层和金属布线层的RDL,如前所述,并且可以包括直接在光学元件的底部电极144、134上形成的金属布线层。然后,在操作1550处,将控制器芯片120面朝下放置到前侧布线层160上,如图16D所示。在一个实施方案中,这可以使用导电膜、导电膏或使用如图所示的焊料凸块270来实现。然后,在操作1560处,可以用第二LDS相容性模塑料411来封装控制器芯片120,如图16E所示。现在参考图16F,在操作1570处,在模塑料411内形成垂直通孔413,并且在模塑料411上形成背侧布线层102。背侧布线层102可以包括使用LDS形成的单层迹线布线,并且可以包括接触焊盘109,但是可以可选地包括附加的电介质和金属布线层。
现在参考图16G至图16H,在操作1580处移除承载衬底200,然后在操作1590处形成顶侧布线层460,该顶侧布线层可以为RDL。如图所示,孔口162用顶侧布线层460形成以暴露光学元件的顶部表面。如图所示,迹线布线497可以在光学元件的顶部电极132、142上形成并且与其电接触。然后可以将焊料凸块170放置在接触焊盘109上,以用于光学封装体100的进一步系统集成。
图17是根据一个实施方案的光学封装体100的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片的顶部上的光学元件和引线结合。图18是根据一个实施方案的制造图17的光学封装体的方法的工艺流程。在例示的实施方案中,光学封装体可以包括背侧布线层102,该背侧布线层可以为PCB。背侧布线层102包括顶侧103和底侧104。在操作1810处,将控制器芯片120面朝下安装在背侧布线层102上。例如,这可以通过用焊料凸块510结合到焊盘105上来实现。在操作1820处将一个或多个光电探测器130和发射器140附接到控制器芯片120,并且在操作1830处使用结合到背侧布线层102的线材502来引线结合。如图所示,使用线材502将顶部电极142、132结合到接地焊盘105。底部电极144、134可以被结合到在控制器芯片120的顶部上形成的迹线504。迹线504继而用线材502引线结合到接地焊盘105。在操作1840处,包封引线结合的控制器芯片和光学元件。例如,这可以通过将金属盖安装到背侧布线层102上或使用模塑料500来实现。图17示出了用于在背侧布线层102上封装控制器芯片120、PD130和发射器140的模塑料500。如前所述,孔口162可以另外在光学元件的顶部表面上方形成。在一个实施方案中,模塑料500是不透明的(例如,黑色模具)。另选地,可以使用具有类似定位的孔口的金属盖。例如,示例性盖可以具有对应于所示模塑料500的外部轮廓的形状。
图19是根据一个实施方案的光学封装体100的示意性横截面侧视图,该光学封装体包括堆叠在控制器芯片120的顶部上的光学元件和引线结合。具体地,图19的实施方案将先前实施方案的第一封装级180的某些方面与光学元件的引线结合组合在一起。在一个实施方案中,光学封装体100包括背侧布线层102,该背侧布线层包括顶侧103和底侧104,以及在背侧布线层102的顶侧上的PCB芯110。该PCB芯110包括多个垂直通孔112和腔115。控制器芯片120在腔115内且面朝上,并且模塑料150将控制器芯片120封装在腔115内。前侧布线层160在控制器芯片120、模塑料150和PCB芯110的顶部上。例如,前侧布线层160可以为如前所述的RDL。一个或多个PD 130和发射器140安装在前侧布线层160的顶侧上。
在一个实施方案中,PD 130包括直接在前侧布线层160的第一接触焊盘169上方的底部电极134,以及引线结合到前侧布线层160的第二接触焊盘169的顶部电极132。一个或多个发射器140的顶部电极142和底部电极144可以类似地连接。在例示的实施方案中,PD130(和对应的线材502)被封装在第一透明模塑料600中,并且发射器140(和对应的线材502)被封装在与第一透明模塑料分开的第二透明模塑料600中。
可以使用不同的技术诸如金属盖或模塑料来包封光学元件。在例示的实施方案中,不透明模塑料在前侧布线层160上封装并且围绕预模制的PD 130和发射器140(包括透明模塑料600)。孔口162可以如前所述形成。在一个实施方案中,滤波器层601诸如带通滤波器可以在孔口162下方形成,以便选择透射穿过孔口162的光的波长。另选地,可以使用具有类似孔口的金属盖代替模塑料605。
类似于先前描述的实施方案,可以将多个焊料凸块170放置在背侧布线层102的底侧104上以进行附加的集成。另外,PCB芯110可以包括层压体114。前侧布线层160可以为RDL,该RDL包括一条或多条金属迹线166和介电层164。背侧布线层102可以另外地是RDL,并且可以可选地包括模塑料150的一部分和延伸穿过模塑料150的多个贯穿通孔108。图19的光学封装体100可以共享先前描述的其他光学封装体的附加的特征。
图20是根据一个实施方案的制造图19的光学封装体的方法的工艺流程。除光学元件之外,与第一封装级180的形成相关的操作2010至2035可以基本上类似于关于图2描述的操作2010至2060。在操作2010处,将PCB芯110放置到承载衬底200上。在操作2015处,将控制器芯片120放置到PCB芯110内的腔115中,并且在操作2020处将其密封。然后可以在操作2025处移除承载衬底200,然后在操作2030处形成前侧布线层160,并且在操作2035处形成背侧布线层102。
然后在操作2040处将包括一个或多个PD 130和发射器140的光学元件放置在前侧布线层160上,并且在操作2045处引线结合到前侧布线层160。然后,在操作2050处,将光学元件中的每个光学元件封装在透明模塑料600内,然后在操作2055处,例如通过附接盖或用不透明模塑料605模制来包封模制的光学元件。
图21A至图23示出了其中可以实现各种实施方案的各种便携式电子设备。图21A至图21B是根据一个实施方案的耳塞的示意性侧视图,该耳塞包括壳体2102和一个或多个开口2110,本文所述的光学封装体100的孔口162可以与该一个或多个开口对准。图22是根据一个实施方案的听筒的示意性侧视图,该听筒包括壳体2202,该壳体包括开口2210,本文所述的光学封装体100的孔口162可以与该开口对准。图23是根据一个实施方案的移动电话的示意性侧视图,该移动电话包括壳体2302,该壳体包括开口2310,本文所述的光学封装体100的孔口162可以与该开口对准。这些例示旨在作为示例性而非穷举的具体实施。
以下是本公开的一些示例实施方式:
实施方式19.一种光学封装体,包括:
第一封装级,包括:
背侧布线层,所述背侧布线层包括顶侧和底侧;
控制器芯片,所述控制器芯片在所述背侧布线层上;
前侧布线层,所述前侧布线层在所述控制器芯片的顶部上;以及
第一多个垂直通孔,所述第一多个垂直通孔在所述前侧布线层和所述背侧布线层之间延伸;
第二封装级,包括:
光电探测器(PD),所述PD安装在所述前侧布线层上并且与所述前侧布线层电接触;
发射器,所述发射器安装在所述前侧布线层上并且与所述前侧布线层电接触;
顶侧布线层,所述顶侧布线层在所述PD和所述发射器上并且与所述PD和所述发射器电接触;以及
第二多个垂直通孔,所述第二多个垂直通孔在所述顶侧布线层和所述前侧布线层之间延伸。
实施方式20.根据实施方式19所述的光学封装体,其中所述控制器芯片在所述背侧布线层上且面朝上。
实施方式21.根据实施方式20所述的光学封装体:
其中所述第一封装级还包括在所述背侧布线层的所述顶侧上的印刷电路板(PCB)芯,所述PCB芯包括所述第一多个垂直通孔和腔;并且
其中所述控制器芯片在所述腔内且面朝上。
实施方式22.根据实施方式21所述的光学封装体:
其中所述第二封装级还包括在所述前布线层上的第二PCB芯,所述第二PCB芯包括所述第二多个垂直通孔和多个腔;并且
其中所述PD在所述多个腔中的第一腔内,并且所述发射器在所述多个腔中的第二腔内。
实施方式23.根据实施方式22所述的光学封装体,其中所述第二封装级用多个氧化物-氧化物结合和金属-金属结合与所述第一封装级混合结合。
实施方式24.根据实施方式22所述的光学封装体,其中所述第二封装级被焊接结合到所述第一封装级。
实施方式25.根据实施方式21所述的光学封装体,其中所述PD、所述发射器和所述第二多个垂直通孔被封装在模塑料中。
实施方式26.根据实施方式25所述的光学封装体,其中所述顶侧布线层为包括一条或多条金属迹线和一个或多个介电层的顶部重新分布层(RDL)。
实施方式27.根据实施方式25所述的光学封装体:
其中所述模塑料为包括分散的非导电金属有机化合物的激光直接成型(LDS)相容性材料;并且
其中所述顶侧布线层包括迹线布线,所述迹线布线包括所述分散的非导电金属有机化合物中的所述金属的金属颗粒的成核层。
实施方式28.根据实施方式27所述的光学封装体,其中所述第二多个垂直通孔包括所述分散的非导电金属有机化合物中的所述金属的金属颗粒的所述成核层。
实施方式29.根据实施方式19所述的光学封装体:
其中所述PD、所述发射器和所述第二多个垂直通孔被封装在第二级模塑料中;并且
其中所述第二级模塑料为包括分散的非导电金属有机化合物的激光直接成型(LDS)相容性材料。
实施方式30.根据实施方式29所述的光学封装体:
其中所述第一封装级还包括在所述背侧布线层的所述顶侧上的印刷电路板(PCB)芯,所述PCB芯包括所述第一多个垂直通孔和腔;并且
其中所述控制器芯片在所述腔内且面朝上。
实施方式31.根据实施方式29所述的光学封装体,其中所述控制器芯片在所述背侧布线层上且面朝下。
实施方式32.根据实施方式31所述的光学封装体:
其中所述控制器芯片被封装在第一级模塑料中;
其中所述第一级模塑料为包括第一分散的非导电金属有机化合物的激光直接成型(LDS)相容性材料;并且
其中所述前侧布线层包括第一迹线布线,所述第一迹线布线包括在所述第一分散的非导电金属有机化合物中的第一金属的第一金属颗粒的第一成核层。
实施方式33.根据实施方式32所述的光学封装体,其中所述背侧布线层为印刷电路板(PCB)。
实施方式34.根据实施方式32所述的光学封装体,其中所述背侧布线层为包括模塑料和穿过所述模塑料的多个贯穿通孔的重新分布层(RDL)。
实施方式35.一种光学封装体,包括:
背侧布线层,所述背侧布线层包括顶侧和底侧;
控制器芯片,所述控制器芯片在所述背侧布线层上且面朝下安装;
光电探测器(PD),所述PD附接到所述控制器芯片,并且引线结合到所述背侧布线层;
发射器,所述发射器附接到所述控制器芯片,并且引线结合到所述背侧布线层;以及
模塑料,所述模塑料在所述背侧布线层上封装所述控制器芯片、所述PD和所述发射器。
实施方式36.根据实施方式35所述的光学封装体,其中所述模塑料是不透明的。
在利用实施方案的各个方面时,对本领域的技术人员将变得显而易见的是,对于形成光学封装体而言,以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述,但应当理解,所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。
Claims (18)
1.一种光学封装体,包括:
背侧布线层,所述背侧布线层包括顶侧和底侧;
印刷电路板(PCB)芯,所述PCB芯在所述背侧布线层的所述顶侧上,所述PCB芯包括多个垂直通孔和腔;
控制器芯片,所述控制器芯片在所述腔内且面朝上;
模塑料,所述模塑料将所述控制器芯片封装在所述腔内;
前侧布线层,所述前侧布线层在所述控制器芯片、所述模塑料和所述PCB芯的顶部上;以及
光电探测器(PD),所述PD安装在所述前侧布线层的顶侧上。
2.根据权利要求1所述的光学封装体,还包括安装在所述前侧布线层的所述顶侧上的发射器。
3.根据权利要求2所述的光学封装体,其中所述PD包括直接在所述前侧布线层的第一接触焊盘上方的底部电极,以及引线结合到所述前侧布线层的第二接触焊盘的顶部电极。
4.根据权利要求2所述的光学封装体,其中所述PD被封装在第一透明模塑料中,并且所述发射器被封装在与所述第一透明模塑料分开的第二透明模塑料中。
5.根据权利要求4所述的光学封装体,还包括在所述前侧布线层上并且围绕所述PD和所述发射器的金属盖。
6.根据权利要求4所述的光学封装体,还包括在所述前侧布线层上并且围绕所述PD和所述发射器的不透明模塑料。
7.根据权利要求2所述的光学封装体,还包括在所述背侧布线层的所述底侧上的多个焊料凸块。
8.根据权利要求2所述的光学封装体,其中所述PCB芯包括层压体。
9.根据权利要求1所述的光学封装体,其中所述前侧布线层为包括一条或多条金属迹线和一个或多个介电层的前重新分布层(RDL)。
10.根据权利要求1所述的光学封装体,其中所述背侧布线层为包括所述模塑料和穿过所述模塑料的多个贯穿通孔的重新分布层(RDL)。
11.一种光学封装体,包括:
背侧布线层,所述背侧布线层包括顶侧和底侧;
印刷电路板(PCB)芯,所述PCB芯在所述背侧布线层的所述顶侧上,所述PCB芯包括多个垂直通孔和多个腔;
控制器芯片,所述控制器芯片在所述多个腔中的第一腔内且面朝上;
光电探测器(PD),所述PD在所述多个腔中的第二腔内;
模塑料,所述模塑料将所述控制器芯片封装在所述第一腔内,并且将所述PD封装在所述第二腔内;
前侧布线层,所述前侧布线层在所述控制器芯片、所述模塑料、所述PCB芯的顶部上;以及
孔口,所述孔口在所述PD上方的所述前侧布线层内。
12.根据权利要求11所述的光学封装体,还包括在所述多个腔中的第三腔内的发射器,以及在所述发射器上方的所述前侧布线层内的第二孔口。
13.根据权利要求12所述的光学封装体,还包括在所述背侧布线层的所述底侧上的多个焊料凸块。
14.根据权利要求12所述的光学封装体,其中所述PCB芯包括层压体。
15.根据权利要求12所述的光学封装体,其中所述前侧布线层包括在所述PD的顶部电极上的第一接触焊盘,并且所述PD包括电连接到所述背侧布线层的底部电极。
16.根据权利要求15所述的光学封装体,还包括通孔,所述通孔延伸穿过所述模塑料的一部分,以将所述PD的所述底部电极电连接到所述背侧布线层。
17.根据权利要求11所述的光学封装体,其中所述前侧布线层为包括一条或多条金属迹线和一个或多个介电层的前重新分布层(RDL)。
18.根据权利要求11所述的光学封装体,其中所述背侧布线层为包括所述模塑料和穿过所述模塑料的多个贯穿通孔的重新分布层(RDL)。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103000593A (zh) * | 2011-09-09 | 2013-03-27 | 台湾积体电路制造股份有限公司 | 用于半导体器件的封装方法和结构 |
CN104681457A (zh) * | 2013-06-29 | 2015-06-03 | 英特尔Ip公司 | 多芯片集成的多级重布线层 |
CN105659381A (zh) * | 2014-09-26 | 2016-06-08 | 英特尔公司 | 具有引线键合的多管芯堆叠的集成电路封装 |
US20170053903A1 (en) * | 2015-08-17 | 2017-02-23 | Rohm Co., Ltd. | Optical semiconductor device |
CN107579063A (zh) * | 2016-12-27 | 2018-01-12 | 日月光半导体制造股份有限公司 | 光学装置、光学模块结构及制造程序 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4912275B2 (ja) | 2007-11-06 | 2012-04-11 | 新光電気工業株式会社 | 半導体パッケージ |
US20110064362A1 (en) | 2009-09-11 | 2011-03-17 | St-Ericsson Sa | Integrated circuit device or package and integrated circuit system, with an optical wave-guide element |
US8981511B2 (en) | 2012-02-29 | 2015-03-17 | Semiconductor Components Industries, Llc | Multi-chip package for imaging systems |
US9177884B2 (en) | 2012-10-09 | 2015-11-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method |
US20140296411A1 (en) | 2013-04-01 | 2014-10-02 | Sabic Innovative Plastics Ip B.V. | High modulus laser direct structuring composites |
TWI521671B (zh) | 2013-07-25 | 2016-02-11 | The package structure of the optical module | |
US9443835B2 (en) * | 2014-03-14 | 2016-09-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods |
KR102355023B1 (ko) | 2015-03-30 | 2022-01-25 | 엘지이노텍 주식회사 | 인쇄회로기판 |
CN104961916A (zh) | 2015-07-11 | 2015-10-07 | 刘帅 | 改性lds添加剂及含该添加剂的lcp组合物 |
US9786617B2 (en) | 2015-11-16 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip packages and methods of manufacture thereof |
US9911629B2 (en) | 2016-02-10 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated passive device package and methods of forming same |
KR102275684B1 (ko) | 2017-04-18 | 2021-07-13 | 삼성전자주식회사 | 반도체 패키지 |
US10510718B2 (en) * | 2017-08-28 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US11057984B2 (en) | 2017-11-30 | 2021-07-06 | Ii-Vi Delaware, Inc. | High-speed hybrid circuit |
US10930802B2 (en) * | 2018-05-03 | 2021-02-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US10777430B2 (en) * | 2018-06-27 | 2020-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photonic integrated package and method forming same |
US11133423B2 (en) * | 2019-07-03 | 2021-09-28 | Advanced Semiconductor Engineering, Inc. | Optical device and method of manufacturing the same |
JP7226550B2 (ja) * | 2019-07-09 | 2023-02-21 | 株式会社村田製作所 | 光学装置、およびその製造方法 |
-
2019
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-
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- 2020-06-24 US US16/911,153 patent/US11651976B2/en active Active
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-
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- 2023-05-12 US US18/316,962 patent/US20230386865A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103000593A (zh) * | 2011-09-09 | 2013-03-27 | 台湾积体电路制造股份有限公司 | 用于半导体器件的封装方法和结构 |
CN104681457A (zh) * | 2013-06-29 | 2015-06-03 | 英特尔Ip公司 | 多芯片集成的多级重布线层 |
CN105659381A (zh) * | 2014-09-26 | 2016-06-08 | 英特尔公司 | 具有引线键合的多管芯堆叠的集成电路封装 |
US20170053903A1 (en) * | 2015-08-17 | 2017-02-23 | Rohm Co., Ltd. | Optical semiconductor device |
CN107579063A (zh) * | 2016-12-27 | 2018-01-12 | 日月光半导体制造股份有限公司 | 光学装置、光学模块结构及制造程序 |
TW201823799A (zh) * | 2016-12-27 | 2018-07-01 | 日月光半導體製造股份有限公司 | 光學裝置、光學模組結構及製造程序 |
CN110223975A (zh) * | 2016-12-27 | 2019-09-10 | 日月光半导体制造股份有限公司 | 光学装置、光学模块结构及制造程序 |
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US20230386865A1 (en) | 2023-11-30 |
US11651976B2 (en) | 2023-05-16 |
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