TWI770405B - 封裝元件及其製備方法 - Google Patents
封裝元件及其製備方法 Download PDFInfo
- Publication number
- TWI770405B TWI770405B TW108126677A TW108126677A TWI770405B TW I770405 B TWI770405 B TW I770405B TW 108126677 A TW108126677 A TW 108126677A TW 108126677 A TW108126677 A TW 108126677A TW I770405 B TWI770405 B TW I770405B
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- package
- ground contacts
- conductive
- ground
- rear surface
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- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 238000000034 method Methods 0.000 claims description 50
- 229910000679 solder Inorganic materials 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 32
- 239000002245 particle Substances 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 238000000465 moulding Methods 0.000 claims description 15
- 230000005670 electromagnetic radiation Effects 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 12
- 230000008018 melting Effects 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 239000000945 filler Substances 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000007767 bonding agent Substances 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229920000058 polyacrylate Polymers 0.000 claims description 3
- 229920001225 polyester resin Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000002952 polymeric resin Substances 0.000 claims description 3
- 239000004408 titanium dioxide Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 claims description 2
- 239000000565 sealant Substances 0.000 abstract description 7
- 239000008393 encapsulating agent Substances 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 description 9
- 239000011230 binding agent Substances 0.000 description 8
- 238000001723 curing Methods 0.000 description 7
- 230000004907 flux Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 229910006913 SnSb Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000498 ball milling Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004414 compression moulding compound Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000002525 ultrasonication Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/732—Location after the connecting process
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
本揭露提供一種封裝元件及其製備方法。該封裝元件包括一支撐組件、一主元件、一密封件以及一導電封裝件。該支撐組件具有複數個接地接點。該主元件安裝在該支撐組件上。該密封件覆蓋該主元件。該導電封裝件包圍該密封件以及穿經該密封件而暴露的該等接地接點,以屏蔽電磁干擾。
Description
本申請案主張2018/12/27申請之美國臨時申請案第62/785,412號及2019/03/21申請之美國正式申請案第16/360,662號的優先權及益處,該美國臨時申請案及該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種封裝元件及其製備方法。特別是有關於一種具有電磁干擾屏蔽的封裝元件及其製備方法。
藉由提升製程速度及較小尺寸需求的驅動,半導體裝置已逐漸變得複雜。在提升製程速度及較小尺寸的優勢是明確的同時,半導體裝置的特性係亦產生問題。特別是,較高的時序速度(clock speed)會使訊號準位(signal level)轉換的頻率增加,以致於頻率較高或波長較短的電磁輻射(electromagnetic radiation)強度增加。電磁輻射可從一源半導體元件(source semiconductor device)發射而出並傳播至鄰近的半導體元件上。若是對鄰近的半導體元件的電磁輻射強度夠高的話,則電磁輻射會對(鄰近的)半導體元件的操作有不利的影響。此現象有時被稱為電磁干擾(electromagnetic interference,EMI)。尺寸較小的半導體元件會使電磁
干擾的問題更加嚴重,因為這些(尺寸較小的)半導體元件會以較高的密度配置於一電子系統中,以致於鄰近的半導體元件接收到較強且非預期的電磁輻射。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種封裝元件。該封裝元件包括一支撐組件(supporting member)、一主元件(main component)、一密封件(sealant)以及一導電封裝件(conductive encapsulant)。該支撐組件具有複數個接地接點。該主元件安裝在該支撐組件上。該密封件覆蓋該主元件。該導電封裝件包圍該密封件以及穿經該密封件而暴露的該等接地接點。
依據本揭露之一些實施例,該支撐組件包括:一基底,其中該等接地接點設置在該基底的一前表面上與設置在該基底的一後表面(back surface)上,該後表面相對該前表面設置;複數個接地通孔(grounding vias),穿透該基底,並將在該前表面上的該等接地接點電性連接到在該後表面上的該等接地接點;以及複數個銲料凸塊(solder bumps),連接到在該後表面上的該等接地接點。
依據本揭露之一些實施例,還包括至少一線路(wire),從該主元件結合到在該支撐元件上的複數個電路圖案,其中該等電路圖案設置在該前表面與該後表面上,且在該前表面上的該等電路圖案使用複數個直通穿孔電性連接在該後表面上的該等電路圖案,而該等直通穿孔延伸穿經該前表面與該後表面。
依據本揭露之一些實施例,當提供一接地電壓(grounding voltage)給該等銲料凸塊時,用於將非預期電磁輻射接地的一電性通道(electrical pathway)係引入到該等銲料凸塊、該等接地接點、該等接地通孔以及該導電封裝件中。
依據本揭露之一些實施例,該導電封裝件具有一側表面(lateral surface),係與該基底的一側壁共面(coplanar)。
依據本揭露之一些實施例,該導電封裝件包括:一樹脂結合劑(resin binder);以及複數個導電粒子,分佈在該樹脂結合劑中。
依據本揭露之一些實施例,該樹脂結合劑具有一熔點,係低於該密封件的一熔點。
依據本揭露之一些實施例,該封裝元件還包括複數個調色粒子(toner particles),分佈在該密封件中。
依據本揭露之一些實施例,該導電封裝件具有一大致平坦上表面。
本揭露之另一實施例提供一種封裝元件的製備方法。該製備方法包括下列步驟:提供一主元件(main device),包括一支撐組件以及一主元件,其中該主元件配置在該支撐組件上並電性連接該支撐組件,且該支撐組件包括包圍該主元件的複數個接地接點;執行一模封製程(molding process),以形成一密封件,進而覆蓋該主元件;以及執行一封裝製程(encapsulation process),以形成一導電封裝件,進而包圍該密封件與該等接地接點。
依據本揭露之一些實施例,該製備方法還包括將複數個銲料凸塊安裝在該等接地接點上,而該等接地接點係位在該支撐組件之一基
底的一後表面上,其中該基底具有相對該後表面設置的一前表面,該等接地接點係設置在該前表面與該後表面上,且該支撐組件還包括複數個接地通孔,係穿透該基底,並將在該前表面上的該等接地接點電性連接到在該後表面上的該等接地接點。
依據本揭露之一些實施例,該封裝膠體製程包括:將覆蓋有該密封件的該主元件放置在一第一模封腔室(first molding cavity)中;將該導電封裝件放置在一第二模封腔室(second molding cavity)中;提供一壓力以迫使覆蓋有該密封件的該主元件接觸到該導電封裝件;以及固化(curing)該導電封裝件。
依據本揭露之一些實施例,該製備方法還包括在該壓力提供之前,熔化該導電封裝件。
依據本揭露之一些實施例,該製備方法還包括在一樹脂結合劑中佈設複數個導電粒子,以形成該導電封裝件。
依據本揭露之一些實施例,該製備方法還包括在該主元件與該支撐組件之間沉積一黏著劑,以將該主元件固定在該支撐組件。
依據本揭露之一些實施例,該製備方法還包括在該密封件中提供複數個調色粒子。
由於上述的封裝元件的架構,覆蓋該主元件的該導電封裝件係包含複數個導電粒子,藉此當提供一接地電壓給該封裝膠體時,係產生用於非預期電磁輻射接地的一電性通道,以致於提供一電磁輻射屏蔽功能。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的
之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:封裝元件
10A:封裝元件
10B:封裝元件
110:支撐組件
111:周圍
112:基底
1120:側壁
1122:前表面
1124:後表面
1128:開口
114:電路圖案
116:直通穿孔
120:主元件
122:功能表面
124:結合墊
126:下表面
130:密封件
132:頂表面
134:調色粒子
136:填充材料
140:導電封裝件
1402:側向表面
142:平坦上表面
144:樹脂結合劑
146:導電粒子
148:頂壁
149:周壁
150:銲料凸塊
160:線路
162:電性介面
170:黏著劑
180:接地接點
182:接地通孔
184:穿孔
186:導體
190:底充填材料
200:主元件
210:第一模封腔室
212:第二模封腔室
30:製備方法
302:步驟
304:步驟
306:步驟
308:步驟
310:步驟
312:步驟
314:步驟
T1:厚度
T2:厚度
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一些實施例的一種封裝元件之剖視示意圖。
圖2為依據本揭露一些實施例的一種封裝元件之剖視示意圖。
圖3為依據本揭露一些實施例的一種封裝元件之剖視示意圖。
圖4為依據本揭露一些實施例的一種封裝元件的製備方法之流程示意圖。
圖5至圖11為依據本揭露一些實施例該封裝元件於製備的各中間階段之剖視示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,
重複使用「在實施例中」一語並非必須指相同實施例,然而可為相同實施例。
為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
本文中使用之術語僅是為了實現描述特定實施例之目的,而非意欲限制本發明。如本文中所使用,單數形式「一(a)」、「一(an)」,及「該(the)」意欲亦包括複數形式,除非上下文中另作明確指示。將進一步理解,當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時,該等術語規定所陳述之特徵、整數、步驟、操作、元件,及/或組件之存在,但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件,及/或上述各者之群組。
圖1為依據本揭露一些實施例的一種封裝元件10之剖視示意圖。請參考圖1,在一些實施例中,封裝元件10包括一支撐組件110、一主元件120、一密封件130以及一導電封裝件140,主元件120配置在支撐組件110上,密封件130覆蓋主元件120,導電封裝件140包圍密封件130。
在一些實施例中,支撐組件110具有一基底112、複數個電路圖案114以及複數個直通穿孔(through vias)116,基底112具有一前表面1122以及一後表面(back surface)1124,後表面1124係相對前表面1122設置,複數個電路圖案114係分別配置在前表面1122與後表面1124上,複數
個直通穿孔116係穿透基底112並電性連接到各電路圖案114。在一些實施例中,基底112係可由介電材料所製,例如雙馬來醯亞胺-三氮雜苯樹脂(BT resin)、由帶有環氧樹脂黏結劑且具有耐火性之編織玻璃纖維布所製成的一種複合材料(FR4 epoxy/glass)。在一些實施例中,各電路圖案114係可為鍍金導體(gold-plated conductors)、鍍銅導體(copper-plated conductors)、或是鍍鋁導體(aluminum-plated conductors)。在一些實施例中,直通穿孔116係可為銅導體(copper conductors)。在一些實施例中,支撐組件110係可為一印刷電路板(printed circuit board,PCB)。在一些實施例中,支撐組件110係可為一硬質印刷電路板或者是一可撓性印刷電路板。在一些實施例中,支撐組件110係可為一單層印刷電路板。在一些實施例中,支撐組件110係可為一多層印刷變路板,其係具有在基底112中的佈線(routing)(圖未示),並電性連接各電路圖案114及/或各直通穿孔116。
在一些實施例中,封裝元件10可還包括複數個銲料凸塊150,係連接到設置在後表面1124上的各電路圖案114。在一些實施例中,各銲料凸塊150係當作輸入/輸出(I/O)連接,以將主元件120電性連接到外部印刷電路板(圖未示)。
在一些實施例中,主元件120係安裝在前表面1122上。在一些實施例中,主元件120包括一功能表面(functional surface)122以及一或多個結合墊(bonding pads)124,功能表面122係面對遠離支撐組件110的方向,結合墊124係設置在功能表面122上。在一些實施例中,結合墊124係可為鋁結合墊。在一些實施例中,主元件120係以線路結合技術(wire bonding technique)電性連接支撐組件110;亦即,結合墊124係透過一或
多個線路(wires)160電性連接電路圖案114。換言之,線路160從在主元件120上的結合墊124延伸到在前表面1122上的電路圖案114。
在一些實施例中,例如環氧樹脂(epoxy)的一黏著劑(adhesive)170係可使用來將相對功能表面122設置的一下表面126連接到基底112的前表面1122,以便增加在主元件120與支撐組件110之間的黏著(adhesion)以得到更佳的可靠度(greater reliability)。
在一些實施例中,密封件(sealant)130係完全地覆蓋主元件120與線路160,以得到機械上及環境上的保護。在一些實施例中,支撐組件110的一周圍(periphery)111係穿經密封件130而暴露。在一些實施例中,密封件130係可具有一平坦頂表面132。在一些實施例中,密封件130係可包含環氧基樹脂(epoxy-based resin)、聚亞醯胺基樹脂(polyimide-based resin)、聚酯基樹脂(polyester-based resin),或是聚丙烯酸酯基聚合物樹脂(polyacrylate-based polymer resin)。
在一些實施例中,密封件130係可為透明(transparent)或是不透明(opaque)。當密封件130為不透明時,較佳者係為黑色。黑色係輻射最多熱(heat),且在從主元件120散熱到線路160與電路圖案114是最有效率的。在一些實施例中,黑色係可以增加調色粒子(toner particles)134來形成。在一些實施例中,例如包含碳(carbon)的調色粒子134係可額外地提供在密封件130中,以持續地將從主元件120所產生的熱轉移到支撐組件110,也因此改善封裝元件10的散熱特性(thermal dissipating property)。藉由在密封件130中設置調色粒子134,係可縮短密封件130的固化時間(curing time)。在一些實施例中,密封件130係可包含一填充材料(filler material)136,用以加強一機械特性(filler material)。詳而言
之,當結合主元件120時,填充材料136係所起的作用是避免密封件130的機械特性惡化。在一些實施例中,填充材料136係可包含氧化矽(silicon oxide)、二氧化矽(silicon dioxide)、二氧化鈦(titanium dioxide)或是氧化鋁(aluminum oxide)。
在一些實施例中,導電封裝件140係完全地包圍密封件130與支撐組件110的周圍111。在一些實施例中,導電封裝件140係可具有一平坦上表面142。在一些實施例中,導電封裝件140係包括一樹脂結合劑(resin binder)144以及複數個導電粒子(conductive particles)146,導電粒子146係佈設載樹脂結合劑144中,舉例來說,導電粒子146可為金屬粒子,例如鈦、鋁、銅、金、鋅(zinc),或是銀。在一些實施例中,導電封裝件140係包含具有一預設濃度(designated concentration)的導電粒子146,其係允許用於一電性連接(electrical connection)。在一些實施例中,導電封裝件140係可為一壓縮模塑(compression molding)封裝膠體或是一轉移模塑(transfer molding)封裝膠體。在一些實施例中,導電封裝件140具有一頂壁148以及一周壁(peripheral wall)149,頂壁148連接上表面142,周壁149係從頂壁148延伸,其中周壁149具有一厚度T1,係大於頂壁148的一厚度T2。
在一些實施例中,封裝元件10係還包括複數個接地接點(grounding contacts)180以及複數個接地通孔(grounding vias)182,接地接點180係設置在支撐組件110上之前表面1122與後表面1124上,接地通孔182係穿透支撐組件110並電性連接接地接點180。在一些實施例中,導電封裝件140包圍在前表面1122上的接地接點180。在一些實施例中,當提供一接地電壓給銲料凸塊150時,用於將非預期電磁輻射接地的一電性
通道(electrical pathway)係引入到連接到接地接點180的銲料凸塊150、接地通孔182以及導電封裝件140中。在一些實施例中,取決於導電封裝件140之電磁輻射入射(electromagnetic radiation incident)的接地,係可透過一電性通道發生,而所述電性通道係包含接地接點180、接地通孔182以及連接到接地接點180的銲料凸塊150。在一些實施例中,封裝元件10係可為一微間距球柵陣列(fine-pitch ball grid array,FBGA)封裝元件。
封裝元件10A、10B的一些實施例係繪示在圖2與圖3中說明。應理解的是,如圖2及圖3所示的封裝元件10A、10B係包括許多特徵,其特徵係相同於或是類似於對應圖1所揭露的封裝元件10的特徵。為了明確與簡易,係可省略其相同或類似的詳細說明,且相同或類似的參考(元件)編號表示相同或類似的元件。如圖2及圖3所示的封裝元件10A、10B與如圖1所示的封裝元件10之間的主要差異,係敘述如下。
請參考圖2,封裝元件10A係為一開窗型球柵陣列(window ball grid array,WBGA)封裝元件。在一些實施例中,封裝元件10A的基底112係包括一開口(opening)1128,係延伸穿經前表面1122與後表面1124。在一些實施例中,開口1128係大致地形成在基底112的中心處。在一些實施例中,功能表面122係以面朝下的手段(face-down manner)安裝,以允許功能表面122配置在前表面1122上以及配置在開口1128的一端上,以便主元件120的各結合墊124可經由開口1128而暴露,並透過穿經開口1128的各線路160,電性連接在後表面1124上之相對應的各電路圖案114。在一些實施例中,封裝元件10A還包括一底充填材料(under-filler)190,係形成在支撐組件110的後表面1124上,並填入開口1128以包圍各線路160。在一些實施例中,底充填材料190係可為透明或是不透
明。在一些實施例中,底充填材料190與密封件130係可具有相同材料。在一些實施例中,各調色粒子係可額外地提供在底充填材料190中,以使從支撐組件110所產生的熱係可持續地轉移到支撐組件110,並可改善封裝元件10A的散熱特性。在一些實施例中,導電封裝件140係大致地為一共形封裝體(conformal encapsulant)。
請參考圖3,封裝元件10B係為一覆晶尺度(flip-chip scale)封裝元件。在一些實施例中,主元件120的功能表面122係面對基底112,且主元件120的各結合墊124係以電性介面(electrical interface)162之方法電性連接設置在前表面1122上的各電路圖案114,而電性介面162係包含一可銲性合金(solderable alloy),例如錫銀銅(SnAgCu)合金、錫鉛(tin-lead,SnPb)合金,或是錫銻(tin-antimony,SnSb)合金。較佳者,電性介面162係具有一熔點(melting point),其係高於銲料凸塊150的熔點,以當各銲料凸塊150須經過一回銲製程(reflow process)時,至少大致地避免電性介面162的回銲(reflow)。
圖4為依據本揭露一些實施例的一種封裝元件10的製備方法30之流程示意圖。圖5至圖11為依據本揭露一些實施例該封裝元件於封裝元件10之製備方法30中的各中間階段之剖視示意圖。圖5至圖11所示的各階段係亦繪示圖4的流程圖中。在接下來的討論中,如圖5至圖11所示的各製備階段係參考如圖4中的製程步驟進行討論。理應理解的是,製備方法30係與一單一主元件120的封裝一同討論。然而,方法論係提供相同地多個體主元件120的封裝,其係可實現不同之多樣功能。
請參考圖5,在一些實施例中,依據如圖4中的一步驟302,係提供一支撐組件110。在一些實施例中,支撐組件110係包括一基底
112,係具有一接近平坦前表面1122與一接近平坦後表面1124,後表面1124係與前表面1122相對設置。在一些實施例中,複數個電路圖案114與複數個接地接點180係分別地設置在前表面1122與後表面1124上,其中各接地接點180係配置在支撐組件110的一周圍111。在一些實施例中,複數個直通穿孔116係穿透基底112,並電性連接各電路圖案114,且複數個接地通孔(grounding vias)182係穿透基底112並電性連接各接地接點180。在一些實施例中,各直通穿孔116與各接地通孔182係藉由執行一鑽孔步驟(drilling step)以及一電路步驟(plating step)的步驟所形成,鑽孔步驟係形成延伸經過前表面1122與後表面1124的複數個穿孔(through holes)184,而電鍍步驟係在各穿孔184中形成多個導體(conductors)186。
接著,依據在圖4中的一步驟304,一主元件120係安裝在支撐組件110上。在一些實施例中,主元件120係具有一下表面126,其係面對支撐組件110的前表面1122。在一些實施例中,主元件120係可為一記憶體晶粒(memory die)、一邏輯晶粒(logic die),或是一應用專用積體電路(application-specific integrated circuit,ASIC)晶粒。在一些實施例中,主元件120係可連接前表面1122,舉例來說,係可使用配置在下表面126上的一黏著劑170。在一些實施例中,黏著劑170係可為一晶粒貼合膜(die attach film,DAF)或是其他適合的黏著劑,例如膠黏劑(glue)或是環氧樹脂(epoxy)。
接下來,依據在圖4中之一步驟306,係形成一或多個線路160,以允許主元件120與支撐組件110的電性連接。據此,係形成一主元件200。在一些實施例中,主元件120具有一功能表面122以及一或多個結合墊124,功能表面122係相對下表面126設置,結合墊124係設置在功能
表面122上;每一線路160的一端係連接其中一結合墊124,每一線路160的另一端連接在前表面1122上的其中一直通穿孔116。在一些實施例中,各線路160係可為金、銅、鋁,或是其類似物。
請參考圖6A及圖6B,在一些實施例中,依據在圖4中的一步驟308,執行一模封製程(molding process)以在主元件120與各線路160上形成一密封件130。在一些實施例中,密封件130係完全地覆蓋主元件120、各線路160,以及前表面1122的一部分。在一些實施例中,支撐組件110的周圍111係穿經密封件130而暴露。在一些實施例中,各接地接點180係穿經密封件130而暴露。在一些實施例中,密封件130係可為一聚合物複合物(polymer composite)材料,例如環氧樹脂(epoxy resin)、聚丙烯酸酯(acrylate)、或是具有適當填充材料136的聚合物。在一些實施例中,密封件130係可包含一熱固性聚合物(thermoset polymer)材料。在一些實施例中,密封件130係為非導電性(non-conductive),並保護主元件200周圍環境避免遭受外部元件的影響。在一些實施例中,複數個調色粒子134係可額外地加入到密封件130中。在一些實施例中,為黑色的各調色粒子134係可持續地將主元件120所產生的熱轉移到支撐組件110。在一些實施例中,用於形成密封件130之適合的方法係可包括一點膠製程(dispensing process)、一移轉成型(transfer molding)製程、一壓模成型(compressive molding)製程、一液體封裝成型(liquid encapsulent molding)製程,或是其類似製程。在一些實施例中,密封件130係可以液體形態點膠(dispensed),以覆蓋主元件120與各線路160。接著,係執行一固化製程(curing process),以凝固密封件130。在一些實施例中,密封件130係可以一自由基固化製程(radical curing process)、一紫外線(ultraviolet,
UV)固化製程及/或一熱固化製程進行固化。在圖6A中,密封件130係具有一大致平坦頂表面132。在圖6B中,密封件130的頂表面132係為一大致圓表面(rounded surface)。
請參考圖7,在一些實施例中,依據圖4中的一步驟310,執行一封裝製程(encapsulation process),以形成包含複數個導電粒子146的一導電封裝件140,進而覆蓋密封件130。在一些實施例中,導電封裝件140係以液體形態點膠在第一模封腔室(first molding cavity)210中,且覆蓋有密封件130的主元件200係設置在一第二模封腔室212(second molding cavity)中,而第二模封腔室212係與主元件120向下朝向導電封裝件140的功能表面122一同設置。在一些實施例中,導電封裝件140係包括一樹脂結合劑(resin binder)144以及複數個導電粒子146,舉例來說,樹脂結合劑144為環氧樹脂(epoxy),各導電粒子146係提供穿經導電封裝件140的多個導電路徑(conductive paths),並佈設在樹脂結合劑144中。在一些實施例中,例如超聲波處理(ultrasonication)、球磨(ball milling)、高速剪切(high-speed shearing)、化學重組(chemical reforming)等方法,係可被用來均勻地將導電粒子146佈設在樹脂結合劑144中。在一些實施例中,係可加熱導電封裝件140至一升高溫度,其係足夠熔化樹脂結合劑144。較佳者,樹脂結合劑144係具有一熔點,其係小於密封件130的一熔點,當樹脂結合劑144經過加熱時,以避免密封件130熔化。在一些實施例中,樹脂結合劑144具有一熔化溫度(melting temperature),係接近175度C。
請參考圖8,係施加以箭頭A所表示的一適當壓力,以迫使覆蓋有密封件130的主元件200接觸導電封裝件140,其中係維持熱及壓
力,直到導電封裝件140固化為止。
請參考圖9,在經歷過封裝製程之後的導電封裝件140係為一固體的、均勻的導電封裝件140。在一些實施例中,導電封裝件140係包圍密封件130與穿經密封件130而暴露的各接地接點180。在一些實施例中,支撐組件110之周圍111沒有設置接地接點180的一部分,係穿經導電封裝件140而暴露。
請參考圖10,在一些實施例中,依據圖4中的一步驟312,複數個銲料凸塊150係安裝在支撐組件110上。在一些實施例中,銲料凸塊150係配置在位在後表面1124上之電路圖案114上。在一些實施例中,銲料凸塊150係以初始地將銲接熔劑(solder flux)(圖未示)設置在電路圖案114上進行安裝。銲接熔劑係可以刷(brushing)、噴(spraying)、模版印刷(Stenciling)或其他方法提供。銲接熔劑一般具有一酸性元件(acidic component)以及一黏著特性(adhesive quality),酸性元件係移除氧化阻障層(oxide barriers),而黏著特性係在製程期間幫助避免移動。一旦銲接熔劑在適當位置,銲料凸塊150係可完全地與銲接熔劑接觸,雖然係可應用任何適當的放置方法,係可以使用例如一取放操作(pick and place operation)的方式實現。一旦銲料凸塊150接觸銲接熔劑,係可執行一回銲製程,以回銲銲料凸塊150與銲接熔劑的材料,以完全地將銲料凸塊150結合到電路圖案114。
請參考圖11,依據圖4中的一步驟314,係選擇地執行一切割製程(dicing process),以移除支撐組件110經過導電封裝件14而暴露的周圍111。據此,係完整地形成封裝元件10。在一些實施例中,基底112具有一側壁1120,係與導電封裝件140的一側向表面(lateral surface)1402
共面(planar)。在一些實施例中,係可執行切割製程,舉例來說,係可以使用一切割刀片(dicing saw)、雷射,或是其他適合的裁切技術來達成。
綜上所述,具有封裝元件10、10A、10B的架構,用於將非預期電磁輻射接地的一電性通道係引入到銲料凸塊150中,並連接到接地接點180、接地通孔182以及包含具有高導電性之導電粒子的導電封裝件140。因此,當接地接點180電性連接接地電壓時,係可提供電磁干擾屏蔽。
本揭露之一實施例提供一種封裝元件。該封裝元件包括一支撐組件(supporting member)、一主元件(main component)、一密封件(sealant)以及一導電封裝件(conductive encapsulant)。該支撐組件具有複數個接地接點。該主元件安裝在該支撐組件上。該密封件覆蓋該主元件。該導電封裝件包圍該密封件以及穿經該密封件而暴露的該等接地接點。
本揭露之另一實施例提供一種封裝元件的製備方法。該製備方法包括下列步驟:提供一主元件(main device),包括一支撐組件以及一主元件,其中該主元件配置在該支撐組件上並電性連接該支撐組件,且該支撐組件包括包圍該主元件的複數個接地接點;執行一模封製程(molding process),以形成一密封件,進而覆蓋該主元件;以及執行一封裝製程(encapsulation process),以形成一導電封裝件,進而包圍該密封件與該等接地接點。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:封裝元件
110:支撐組件
111:周圍
112:基底
1122:前表面
1124:後表面
114:電路圖案
116:直通穿孔
120:主元件
122:功能表面
124:結合墊
126:下表面
130:密封件
132:頂表面
134:調色粒子
136:填充材料
140:導電封裝件
142:平坦上表面
144:樹脂結合劑
146:導電粒子
148:頂壁
149:周壁
150:銲料凸塊
160:線路
170:黏著劑
180:接地接點
182:接地通孔
T1:厚度
T2:厚度
Claims (9)
- 一種封裝元件,包括:一支撐組件,具有複數個接地接點,其中該支撐組件包括:一基底,其中該等接地接點設置在該基底的一前表面上與設置在該基底的一後表面上,該後表面相對該前表面設置;複數個接地通孔,穿透該基底,並將在該前表面上的該等接地接點電性連接到在該後表面上的該等接地接點;以及複數個銲料凸塊,連接到在該後表面上的該等接地接點;一主元件,安裝在該支撐組件上;一密封件,覆蓋該主元件,其中該密封件係包含聚亞醯胺基樹脂(polyimide-based resin)、聚酯基樹脂(polyester-based resin)或聚丙烯酸酯基聚合物樹脂(polyacrylate-based polymer resin);以及一導電封裝件,包圍該密封件以及穿經該密封件而暴露的該等接地接點,其中該導電封裝件包括:一樹脂結合劑,以及複數個導電粒子,分佈在該樹脂結合劑中;其中該密封件具有一平坦頂表面以及包含複數個調色粒子和一填充材料,該等調色粒子分佈在該密封件中,該填充材料包含二氧化鈦或是氧化鋁;其中當提供一接地電壓給該等銲料凸塊時,用於將非預期電磁輻射接地的一電性通道係引入到該等銲料凸塊、該等接地接點、該等接地通孔以及該導電封裝件中。
- 如請求項1所述之封裝元件,還包括至少一線路,從該主元件結合到 在該支撐元件上的複數個電路圖案,其中該等電路圖案設置在該前表面與該後表面上,且在該前表面上的該等電路圖案使用複數個直通穿孔電性連接在該後表面上的該等電路圖案,而該等直通穿孔延伸穿經該前表面與該後表面。
- 如請求項1所述之封裝元件,其中該導電封裝件具有一側表面,係與該基底的一側壁共面(coplanar)。
- 如請求項1所述之封裝元件,其中該樹脂結合劑具有一熔點,係低於該密封件的一熔點。
- 如請求項1所述之封裝元件,其中該導電封裝件具有一大致平坦上表面。
- 一種封裝元件的製備方法,包括:提供一主元件,包括一支撐組件以及一主元件,其中該主元件配置在該支撐組件上並電性連接該支撐組件,且該支撐組件包括包圍該主元件的複數個接地接點;將複數個銲料凸塊安裝在該等接地接點上,而該等接地接點係位在該支撐組件之一基底的一後表面上,其中該基底具有相對該後表面設置的一前表面,該等接地接點係設置在該前表面與該後表面上,且該支撐組件還包括複數個接地通孔,係穿透該基底,並將在該前表面上的該等接地接點電性連接到在該後表面上的該等接地接 點;執行一模封製程,以形成一密封件,進而覆蓋該主元件,其中該密封件係包含聚亞醯胺基樹脂(polyimide-based resin)、聚酯基樹脂(polyester-based resin)或聚丙烯酸酯基聚合物樹脂(polyacrylate-based polymer resin),及,其中該密封件具有一平坦頂表面以及包含複數個調色粒子和一填充材料,該等調色粒子分佈在該密封件中,該填充材料包含二氧化鈦或是氧化鋁;以及執行一封裝製程,在一樹脂結合劑中佈設複數個導電電子,以形成一導電封裝件,進而包圍該密封件與該等接地接點;其中當提供一接地電壓給該等銲料凸塊時,用於將非預期電磁輻射接地的一電性通道係引入到該等銲料凸塊、該等接地接點、該等接地通孔以及該導電封裝件中。
- 如請求項6所述之製備方法,該封裝膠體製程包括:將覆蓋有該密封件的該主元件放置在一第一模封腔室中;將該導電封裝件放置在一第二模封腔室中;提供一壓力以迫使覆蓋有該密封件的該主元件接觸到該導電封裝件;以及固化該導電封裝件。
- 如請求項6所述之製備方法,還包括在該壓力提供之前,熔化該導電封裝件。
- 如請求項6所述之製備方法,還包括在該主元件與該支撐組件之間沉積一黏著劑,以將該主元件固定在該支撐組件。
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