CN112992850A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN112992850A
CN112992850A CN202110191914.0A CN202110191914A CN112992850A CN 112992850 A CN112992850 A CN 112992850A CN 202110191914 A CN202110191914 A CN 202110191914A CN 112992850 A CN112992850 A CN 112992850A
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China
Prior art keywords
layer
conductive contact
insulating layer
forming
semiconductor die
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CN202110191914.0A
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English (en)
Inventor
许峰诚
洪瑞斌
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112992850A publication Critical patent/CN112992850A/zh
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Abstract

本发明提供了半导体封装件，包括具有有源表面的第一半导体管芯层、电连接至有源表面的导电接触件，导电接触件的侧壁由绝缘层围绕，以及连接至导电接触件的焊料凸块。晶种层位于导电接触件的侧壁和绝缘层之间。本发明提供了用于制造半导体封装件的方法，该方法包括提供载体，在载体上方形成绝缘层，将载体从绝缘层脱粘并且通过蚀刻操作从绝缘层暴露导电接触件。

Description

半导体封装件及其制造方法
技术领域
本发明的实施例涉及半导体封装件及其制造方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。半导体器件的制造涉及在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体层以及使用光刻和蚀刻工艺图案化各个材料层以在半导体衬底上形成电路组件和元件。
半导体工业通过不断减小最小部件尺寸持续地改进各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成至给定的区域。输入和输出(I/O)连接件的数量显着增加。开发利用更小的面积或更小的高度的更小的封装结构来封装半导体器件。例如，为了进一步增加电路密度，已经对三维(3D)IC进行了研究。
已经开发了新的封装技术来改进半导体器件的密度和功能。这些用于半导体器件的新型的封装技术面临着制造挑战。
发明内容
本发明的实施例提供了一种半导体封装件，包括：第一半导体管芯层，具有有源表面；导电接触件，电连接至所述有源表面，所述导电接触件的侧壁由绝缘层围绕；以及焊料凸块，连接至所述导电接触件，其中，晶种层位于所述导电接触件的所述侧壁和所述绝缘层之间。
本发明的实施例还提供了一种用于制造半导体封装件的方法，包括：提供载体；在所述载体上方形成绝缘层；在所述绝缘层上方形成第一半导体管芯层，包括：在所述绝缘层中形成浅沟槽；在所述浅沟槽中形成导电接触件；和在所述绝缘层上方放置第一半导体管芯；将所述载体从所述绝缘层脱粘；以及通过蚀刻操作从所述绝缘层暴露所述导电接触件。
本发明的又一实施例提供了一种用于制造半导体封装件的方法，包括：提供载体；在所述载体上方形成第一半导体管芯层，包括：在所述载体上方形成第一聚合物层；在所述第一聚合物层中形成浅沟槽；在所述浅沟槽中形成导电接触件；和在所述第一聚合物层上方放置第一半导体管芯；将所述载体从所述第一聚合物层脱粘；以及通过蚀刻操作从所述第一聚合物层暴露所述导电接触件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一些实施例的半导体封装件的截面图；
图2示出了根据本发明的一些实施例的半导体封装件的局部放大的截面图；
图3示出了根据本发明的一些实施例的半导体封装件的局部放大的截面图；
图4示出了根据本发明的一些实施例的半导体封装件的局部放大的截面图；
图5示出了根据本发明的一些实施例的半导体封装件的截面图；
图6示出了根据本发明的一些实施例的半导体封装件的截面图；
图7A至图7H示出了根据本发明的一些实施例的用于制造半导体封装件的方法的顺序的截面图；以及
图8A至图8H示出了根据本发明的一些实施例的用于制造半导体封装件的方法的顺序的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
尽管设定本发明的宽范围的数值范围和参数是近似值，但是尽可能精确地报告具体实例中设定的数值。然而，任何数值固有地包含某些必然误差，该误差由各自的测试测量中发现的标准偏差产生。同样，如此处使用的，术语“约”一般指在给定值或范围的10％、5％、1％或0.5％内。或者，术语“约”意味着在本领域中普通技术人员可以考虑到的可接受的平均标准误差内。除了在操作/工作的实例中，或除非另有明确规定，否则所有数值范围、数量、值和百分比(诸如此处公开的用于材料数量、持续时间、温度、操作条件、数量比例等的那些)应该理解为在所有情况下被术语“约”修改。因此，除非有相反规定，本发明和所附权利要求所记载的数值参数设定是可以根据需求改变的近似值。至少，应该至少根据被报告的有效数字的数目并且通过应用普通的四舍五入技术来解释每个数值参数。本发明中的范围可被表述为从一个端点至另一个端点或者位于两个端点之间。除非另有说明，本发明公开的所有范围均包含端点。
各个实施例均包括用于形成半导体器件封装件的方法和相应的结构。各个实施例将多个功能芯片集成在单个器件封装件中并且实现晶圆上芯片(CoW)级封装的芯片至晶圆(例如，已知良好管芯)。功能芯片可以使用接合层直接接合至其它功能芯片(例如，通过熔融结合和/或混合接合)，以减少形成焊料凸块(例如，微凸块)和底部填充物的需要。各个实施例可以进一步有利地提供具有更小的形状因子、增加的输入/输出密度和低通孔高宽比的系统级封装(SiP)的解决方案。因此，可以减少制造误差和成本。
本申请涉及一种半导体封装件及其制造方法，并且更具体地涉及一种具有增加的导电焊盘数量(例如，每个芯片的I/O数量)的恒定制造成本的半导体封装件及其制造方法。
迫切需要每个芯片的更高I/O数量的趋势。从聚合物层打开I/O接触件的常规的激光钻孔操作遭受低临界尺寸均匀性和高叠置偏移，使得聚合物层与围绕I/O凸块的模塑料之间分层。作为激光钻孔操作的损失，须保留I/O接触件的更大面积外壳，并且因此I/O凸块的间距不能缩小。通常，对于激光钻孔叠置问题，保留了20微米厚的圆周区域。
本发明的总体目的是提供一个或多个以下优势：(1)在恒定的成本下形成更小间距的I/O凸块；(2)能够制造小和大间距的I/O凸块；(3)由于良好的临界尺寸均匀性和更小的叠置偏移，需要更小面积的外壳，例如，小于7微米厚的圆周区域；(4)减小I/O凸块的临界尺寸；(5)提供更好的焊料I/O凸块的接头强度；(6)提供较低的背侧封装接头焊点高度。
本发明提供了在I/O凸块的形成之前，在聚合物层中具有浅沟槽的半导体封装件。浅沟槽可以具有锥形侧壁。晶种层位于浅沟槽的锥形侧壁和I/O凸块之间。
本发明也提供了半导体封装件的制造方法。该方法包括通过光刻操作在聚合物层中形成浅沟槽，在浅沟槽中形成I/O凸块，并且蚀刻聚合物层以暴露I/O凸块。
参照图1，图1是根据本发明的一些实施例的半导体封装件10的截面图。半导体封装件10包括第一半导体管芯层101和第二半导体管芯层102。第二半导体管芯层102还包括封装的管芯1021。例如，封装的管芯1021具有由模塑料密封的堆叠管芯并且设置在载体上方。堆叠管芯包括垂直堆叠的多个管芯并且引线接合至载体上的导电迹线。引线接合可以用于制造从芯片组件(诸如芯片电阻器或芯片电容器)至衬底的电连接。两个功能芯片堆叠在多个衬底层的顶部上。该芯片通过多个接合金线连接至衬底。也可以使用诸如铝线的其它形式的引线。功能芯片、金线和衬底形成了引线接合(WB)封装件。在一些实施例中，封装的管芯1021是存储器管芯，例如，DRAM或NAND闪存。模塑料可以是环氧树脂、聚酰亚胺、硅橡胶等或它们的组合。可以使用可接受的技术(诸如压缩模制)施加模塑料。如图1所示，第一半导体管芯层101包括有源表面101A和无源表面101B或背面。无源表面101B由模塑料密封并且绝缘层1012设置在无源表面101B上方。在一些实施例中，图1中未示出，绝缘层1012与钝化表面101B直接接触。
第一半导体管芯层101大致包括多个管芯121、123以及从管芯121、123的有源表面101A延伸的电连接件。在一些实施例中，管芯121、123是接合至再分布层(RDL)1011的芯片上硅(SOC)管芯倒装芯片。例如，电连接件将管芯121的有源表面101A连接至RDL1011，并且通过导电接触件1013进一步连接至焊料凸块103。在一些实施例中，焊料凸块103是可控塌陷芯片连接(C4)凸块。有源表面101A包括从管芯121、123的主体延伸的互连结构。互连结构可以包括层间介电(ILD)层和/或金属间介电(IMD)层，层间介电(ILD)层和/或金属间介电(IMD)层包含使用任何合适的方法形成的导电部件(例如，包括铜、铝、钨、它们的组合等的导线和通孔)。ILD和IMD可以包括设置在这种导电部件之间的低k介电材料，例如，低k介电材料具有小于约4.0或甚至2.0的k值。在一些实施例中，例如，ILD和IMD层可以由通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何合适的方法形成的磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等制成。互连结构电连接各个有源器件以形成管芯121、123内的功能电路，通过这种电路提供的功能可以包括逻辑结构、存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。本领域普通技术人员将明白以上提供的实例用于说明的目的以进一步解释各个实施例的应用并且不限制本发明。可以使用适用于给定应用的其它电路。
如图1所示，导电接触件1013是穿透密封管芯121、123的模塑料和绝缘层1012的绝缘通孔(TIV)。或者说，TIV的侧壁的部分由绝缘层1012围绕。在一些实施例中，晶种层105可以在TIV的侧壁的部分和绝缘层1012之间观察到。TIV和焊料凸块103之间的接头A的细节在本发明的图2至图4中示出。
在一些实施例中，管芯121、123可以是通过测试或探测操作确定的已知良好管芯(KGD)。使用拾取和放置工具附接KGD。基本的倒装芯片(FC)封装系统包括IC、互连系统和衬底。功能芯片通过多个焊料凸块连接至衬底，其中，焊料凸块形成了芯片和衬底之间的冶金互连。功能芯片、焊料凸块和衬底形成倒装芯片封装件。
如图1所示，半导体封装件10还包括分别通过RDL 1011和导电接触件1013电连接至第一半导体管芯层101和第二半导体管芯层102的球栅阵列(BGA)107。BGA封装技术通常是先进的半导体封装技术，其特征在于，将半导体芯片安装在衬底的正面上，并且诸如焊料球的多个导电元件以矩阵阵列(通常称为球栅阵列)布置在衬底的背面上。BGA允许将半导体封装件接合至并且电连接至外部PCB或其它电子器件。如图1所示，与第一半导体管芯层101的无源表面101B相比，BGA 107更接近有源表面101A。
参照图2，图2是根据本发明的一些实施例的半导体封装件10的局部放大的截面图A1。相同的标号注释表示相同或相似的元件并且为了简洁起见，此处不再重复。导电接触件1013包括主体1013B和台状件1013A。台状件1013A具有与顶面1013”连接的锥形侧壁1013’。如图2所示，台状件1013A的顶面1013”与绝缘层1012的顶面共面。或者说，台状件1013A的侧壁1013’由绝缘层1012和晶种层105完全地围绕，并且仅台状件1013A的顶面1013”与焊料凸块103接触。注意，连接至焊料凸块103的台状件1013A的表面积SA1(虚线所示)小于图3和图4中所示的那些，因此，与图3和图4中所示的那些相比，焊料凸块103可以在最终半导体封装件10中拥有更高的焊点。
图3示出了根据本发明的一些实施例的半导体封装件10的局部放大的截面图A2。导电接触件1013包括主体1013B和台状件1013A。台状件1013A具有与顶面1013”连接的锥形侧壁1013’。如图3所示，台状件1013A的顶面1013”高于绝缘层1012的顶面。在图3中，台状件1013A从绝缘层1012突出距离D1。在一些实施例中，D1可以在从约1μm至约7μm的范围内。或者说，台状件1013A的侧壁1013’由绝缘层1012部分地围绕并且由晶种层105部分地围绕，以及仅顶面1013”和侧壁1013’的部分与焊料凸块103接触。注意，连接至焊料凸块103的台状件1013A的表面积SA2(虚线所示)小于图4中所示的那个但是大于图2中所示的那个，因此，与图4所示的那个相比，焊料凸块103可以在最终半导体封装件10中拥有更高的焊点，并且与图2所示的那个相比，在最终半导体封装件10中拥有更低的焊点。台状件的表面积越大，焊料凸块103和台状件1013A之间的接合强度越大。
图4示出了根据本发明的一些实施例的半导体封装件10的局部放大的截面图A3。导电接触件1013包括主体1013B和台状件1013A。台状件1013A具有与顶面1013”连接的锥形侧壁1013’。如图4所示，台状件1013A的顶面1013”高于模塑料1013的顶面。在图4中，台状件1013A从模塑料1013突出距离D2。在一些实施例中，D2可以在从约5μm至约10μm的范围内。或者说，台状件1013A的侧壁1013’既不由在先前图中所示的绝缘层1012围绕也不由晶种层105围绕。顶面1013”和侧壁1013’与焊料凸块103接触。注意，连接至焊料凸块103的台状件1013A的表面积SA3(虚线所示)大于图2和图3中所示的那些，因此，与图2和图3中所示的那个相比，焊料凸块103可以在最终半导体封装件10中拥有更低的焊点。
图5示出了根据本发明的一些实施例的半导体封装件20的截面图。半导体封装件20包括具有有源表面201A和无源表面201B的第一半导体管芯层201。第一半导体管芯层201的有源表面201A连接至导电接触件2011，例如，RDL。导电接触件2011进一步连接至焊料凸块203。在一些实施例中，焊料凸块203是C4凸块。与第一半导体管芯层201的无源表面201B或背面相比，焊料凸块203更接近有源表面201A。
在一些实施例中，RDL包括多层，例如，第一通孔2011A/第一线2011B、第二通孔2012A/第二线2012B以及第三通孔2013A。然而，适合于特定设计的RDL的更多或更少的层均包括在本发明的范围内。RDL由绝缘层2012包围。注意，绝缘层2012可以在本领域普通技术人员已知的不同的制造操作中形成。在图5中，第一通孔2011A具有底面2011”和侧壁2011’。底面2011”从绝缘层2012暴露。在绝缘层2012和第一通孔2011A的侧壁2011’之间可以观察到晶种层205。除了第一通孔2011A和绝缘层2012之外，晶种层205也在第一线2011B和绝缘层2012之间延伸。
注意，连接至焊料凸块203的第一通孔2011A的表面积SA4小于图6所示的表面积SA5，因此，与图6的最终半导体封装件30中的那些相比，焊料凸块203可以在最终半导体封装件20中拥有更高的焊点。
图6示出了根据本发明的一些实施例的半导体封装件30的截面图。半导体封装件30包括具有有源表面301A和无源表面301B的第一半导体管芯层301。第一半导体管芯层301的有源表面301A连接至导电接触件3011，例如，RDL。导电接触件3011进一步连接至焊料凸块303。在一些实施例中，焊料凸块303是C4凸块。与第一半导体管芯层301的无源表面301B或背面相比，焊料凸块303更接近有源表面301A。
在一些实施例中，RDL包括多层，例如，第一通孔3011A/第一线3011B、第二通孔3012A/第二线3012B以及第三通孔3013A。然而，适合于特定设计的RDL的更多或更少的层均包括在本发明的范围内。RDL由绝缘层3012包围。在图6中，第一通孔3011A具有底面3011”和侧壁3011’。底面3011”从绝缘层3012暴露并且侧壁3011’部分地从绝缘层3012暴露。在绝缘层3012和第一通孔3011A的侧壁3011’的部分之间可以观察到晶种层305。除了第一通孔3011A和绝缘层3012之外，晶种层305也在第一线3011B和绝缘层3012之间延伸。
注意，连接至焊料凸块303的第一通孔3011A的表面积SA5大于图5所示的表面积SA4，因此，与图5的最终半导体封装件20中的那些相比，焊料凸块303可以在最终半导体封装件30中拥有更低的焊点。
图7A中图7H示出了根据本发明的一些实施例的用于制造半导体封装件10的方法的顺序的截面图。相同的标号注释表示相同或相似的元件并且为了简洁起见，此处不再重复。在图7A中，载体701提供有胶合层703。随后在胶合层703上方形成绝缘层1012或介电层。例如，绝缘层1012可以由通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何合适的方法形成的磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等制成。
诸如通过可接受的光刻技术在绝缘层1012上方沉积和图案化光刻胶705。实施蚀刻操作以在绝缘层1012中形成封端沟槽707图案。在一些实施例中，封端沟槽707是占据绝缘层1012的厚度的部分并且没有穿透绝缘层1012的凹槽。在一些实施例中，位于封端沟槽707下方的绝缘层1012的剩余厚度T1为约2微米。或者说，厚度T1和原始绝缘层1012的厚度之间的差为图2至图4所示的台状件1013A的高度。厚度T1确定为约2微米，因为如果厚于T1，则需要较长的背侧蚀刻时间并且如果薄于T1，则在封端沟槽707的形成期间可能引起胶合层的损坏。
在图7B中，例如，通过电镀操作在封端沟槽707中形成导电接触件1013。在图案化的光刻胶的开口中沉积晶种层。在绝缘层1012和封端沟槽707上方沉积的晶种层(未示出)可以是铜、钛等或它们的组合，并且可以通过溅射、其它PVD工艺等或它们的组合沉积。诸如铜、铝等或它们的组合的导电材料通过化学镀、电镀等沉积在封端沟槽707中。诸如通过灰化和/或冲洗工艺去除光刻胶705。
在图7C中，第一半导体管芯层101的管芯121、123放置在绝缘层1012上方。在一些实施例中，管芯121、123可以是通过测试或探测操作确定的已知良好管芯(KGD)。使用拾取和放置工具附接KGD。在一些实施例中，管芯121、123的无源表面101B或背面与绝缘层1012接触。有源表面101A面向与载体701相对的方向。在图7D中，在导电接触件1013和管芯121、123上方施加模塑料702。随后是平坦化操作以至少暴露管芯121、123的有源表面101A和导电接触件1012的端部以暴露用于随后的操作的金属化部分。
在图7E中，RDL 1011形成在模塑料702的平坦化的表面上方并且电连接至管芯121、123和导电接触件1013。在图7F中，进一步处理RDL 1011以形成具有BGA 107的电连接件。在一些实施例中，集成无源器件(IPD)也放置在BGA 107的相同的层级处并且与RDL1011连接。在图7G中，载体701从第一半导体管芯层101脱粘，具体地，载体701通过胶合层703的性质改变与绝缘层分离。脱粘可以包括将胶合层703暴露于诸如激光的UV光，或将粘合剂暴露于溶剂。例如，载体701可以包括玻璃、氧化硅、氧化铝、它们的组合。胶合层703可以是诸如UV胶的任何合适的粘合剂，当暴露于UV光时，失去其粘合性。
在载体701和胶合层703的分离之后，结果暴露绝缘层1012。回参照图7A，由于在形成封端沟槽707时保留绝缘层1012的厚度T1的事实，所以在上述讨论的脱粘操作之后，导电接触件1013不会立即暴露。实施随后和单独的蚀刻操作以消耗至少绝缘层1012的厚度T1以至少暴露如图2至图4所示的台状件1013A的顶面1013”。蚀刻操作可以是适合控制蚀刻深度程度的任何干蚀刻操作。例如，可以使用用于蚀刻的第一等离子体能量将等离子体蚀刻施加至绝缘层1012以暴露台状件1013A的顶面1013”并且获得图2中描述的结构。在其它实施例中，可以施加第二等离子体能量以暴露台状件1013A的顶面1013”和侧壁1013’的部分以获得图3中描述的结构。对于另一实施例，可以采用第三等离子体能量以暴露台状件1013A的顶面1013”和完整的侧壁1013’以获得图4中描述的结构。在一些实施例中，干蚀刻不仅去除了绝缘层1012的材料而且去除了在导电接触件1013的形成之前沉积的晶种层(未示出)的部分。使用干蚀刻而不是使用激光钻孔来暴露导电接触件可以使得导电接触件的临界尺寸更小、叠置控制更好、制造产量高以及导电接触件的数量与制造成本无关。干蚀刻(而不是一系列钻孔操作)在一个制造操作中利用了精良的蚀刻技术。
在图7H中，预形成第二半导体管芯层102以具有连接至第二半导体管芯层102的焊料凸块103，并且第二半导体管芯层102通过焊料凸块103连接至暴露的导电接触件1013。导电接触件1013和焊料凸块103之间的界面的细节可以参照本发明的图2、图3和图4。
参照图8A至图8H，图8A至图8H示出了根据本发明的一些实施例的用于制造半导体封装件30的方法的顺序的截面图。在图8A中，载体801提供有胶合层803。在图8B中，随后在胶合层803上方形成绝缘层3012或第一层间电介质(ILD)。例如，绝缘层3012可以由通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何合适的方法形成的磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等制成。如图8B所示，实施光刻操作以形成封端沟槽805。在一些实施例中，位于封端沟槽805下方的绝缘层3012的剩余厚度T1为约2微米。
在图8C中，在绝缘层3012上方沉积晶种层305并且进一步在晶种层305上方形成图案化的光刻胶807。诸如通过溅射或其它物理汽相沉积(PVD)工艺在绝缘层3012上沉积诸如铜、钛等的晶种层。在图8D中，通过电镀操作形成第一RDL，并且去除图案化的光刻胶807。第一RDL包括符合绝缘层3012的沟槽的第一通孔3011A以及位于绝缘层3012的顶面处的第一线3011B。注意，图案化的光刻胶807的去除可能也去除了下面的晶种层305。
在图8E中，在第一RDL上方形成了另一绝缘层3012。第二ILD沉积在第一RDL上方。第二ILD可以是聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等或它们的组合。可以通过涂覆工艺、层压工艺等或它们的组合沉积第二ILD。可以使用可接受的光刻技术形成穿过第二ILD层至第一RDL层的开口。可以使用与关于第一RDL讨论的相同或相似的工艺来形成随后的第二RDL。第二RDL包括符合第二ILD的开口的第二通孔3012A以及位于第二ILD的顶面处的第二线3012B。随后，在第二RDL上方形成另一绝缘层3012，具体地，在第二RLD上方沉积第三ILD并且在第三ILD的开口中形成第三通孔3013A。RDL的数量可以根据不同设计确定并且此处不是限制性的演示。
第一半导体管芯层301形成在远离载体801的RDL上方并且通过焊料凸块307电连接至所述RDL。第一半导体管芯层301的有源表面301A面向远离载体801的RDL的层。在图8F中，载体801从RDL 3011脱粘，具体地，载体801通过胶合层803的性质改变与绝缘层3012分离。脱粘可以包括将胶合层803暴露于诸如激光的UV光，或将粘合剂暴露于溶剂。例如，载体801可以包括玻璃、氧化硅、氧化铝、它们的组合。胶合层803可以是诸如UV胶的任何合适的粘合剂，当暴露于UV光时，失去其粘合性。
在载体801和胶合层803的分离之后，结果暴露绝缘层3012。回参照图8B，由于在形成封端沟槽805时保留绝缘层3012的厚度T1的事实，所以在上述讨论的脱粘操作之后，第一RDL的导电接触件或第一通孔3011不会立即暴露。实施随后和单独的蚀刻操作以消耗至少绝缘层3012的厚度T1以至少暴露如图2至图4所示的台状件1013A的顶面1013”。蚀刻操作可以是适合控制蚀刻深度程度的任何干蚀刻操作。例如，可以使用用于蚀刻的第一等离子体能量将等离子体蚀刻施加至绝缘层3012以暴露台状件1013A的顶面1013”并且获得图2中描述的结构。在其它实施例中，可以施加第二等离子体能量以暴露台状件1013A的顶面1013”和侧壁1013’的部分以获得图3中描述的结构。对于另一实施例，可以采用第三等离子体能量以暴露台状件1013A的顶面1013”和完整的侧壁1013’以获得图4中描述的结构。在一些实施例中，干蚀刻不仅去除了绝缘层3012的材料而且去除了在导电接触件或第一通孔3011的形成之前沉积的晶种层(未示出)的部分。使用干蚀刻而不是使用激光钻孔来暴露导电接触件可以使得导电接触件的临界尺寸更小、叠置控制更好、制造产量高以及导电接触件的数量与制造成本无关。干蚀刻(而不是一系列钻孔操作)在一个制造操作中利用了精良的蚀刻技术。
例如，如图8G所示，由于干蚀刻操作，导电接触件或第一通孔3011的顶面和侧壁的部分从绝缘层3012突出。第一通孔3011的表面积SA5为图3中先前讨论的并且可以参考。在图8H中，进一步将焊料凸块303安装至第一通孔3011的暴露的表面。焊料凸块303与第一通孔3011的表面积SA5接触。
本发明的一些实施例提供了半导体封装件。半导体封装件包括具有有源表面的第一半导体管芯层、电连接至有源表面的导电接触件，导电接触件的侧壁由绝缘层围绕；以及连接至导电接触件的焊料凸块。晶种层位于导电接触件的侧壁和绝缘层之间。
在上述半导体封装件中，其中，所述导电接触件还包括从所述绝缘层突出并且连接至所述焊料凸块的台状件。
在上述半导体封装件中，其中，所述导电接触件包括再分布层(RDL)的通孔。
在上述半导体封装件中，其中，所述导电接触件包括再分布层(RDL)的通孔，与所述第一半导体管芯层的无源表面相比，所述焊料凸块更接近所述有源表面。
在上述半导体封装件中，其中，所述导电接触件包括绝缘通孔(TIV)。
在上述半导体封装件中，其中，所述导电接触件包括绝缘通孔(TIV)，所述半导体封装件还包括第二半导体管芯层，通过位于所述第一半导体管芯层的无源表面上方的所述焊料凸块电连接至所述导电接触件。
在上述半导体封装件中，其中，所述导电接触件包括绝缘通孔(TIV)，还包括第二半导体管芯层，通过位于所述第一半导体管芯层的无源表面上方的所述焊料凸块电连接至所述导电接触件，其中，所述第二半导体管芯层包括动态随机存取存储器(DRAM)。
在上述半导体封装件中，其中，所述侧壁包括锥形。
在上述半导体封装件中，其中，所述第一半导体管芯层包括芯片上硅(SOC)管芯。
在上述半导体封装件中，还包括与所述第一半导体管芯层的无源表面相比，更接近所述有源表面的球栅阵列(BGA)。
在上述半导体封装件中，其中，所述导电接触件还包括从所述绝缘层突出并且连接至所述焊料凸块的台状件，从所述绝缘层突出的所述台状件的部分未由所述导电接触件的所述侧壁和所述绝缘层之间的所述晶种层围绕。
本发明的一些实施例提供了用于制造半导体封装件的方法。该方法包括提供载体，在载体上方形成绝缘层，在绝缘层上方形成第一半导体管芯层，将载体从绝缘层脱粘并且通过蚀刻操作从绝缘层暴露导电接触件。在绝缘层上方形成第一半导体管芯层还包括在绝缘层中形成浅沟槽，在浅沟槽中形成导电接触件，并且在绝缘层上方放置第一半导体管芯。
在上述方法中，其中，在所述浅沟槽中形成所述导电接触件还包括形成用于电镀操作的晶种层。
在上述方法中，其中，在所述绝缘层中形成所述浅沟槽包括实施光刻操作并且在所述绝缘层中形成封端沟槽，其中，所述绝缘层的最薄部分为2微米。
在上述方法中，其中，所述蚀刻操作包括去除所述晶种层的部分。
本发明的一些实施例提供了用于制造半导体封装件的方法。该方法包括提供载体，在载体上方形成第一半导体管芯层，将载体从第一聚合物层脱粘，并且通过蚀刻操作从第一聚合物层暴露导电接触件。在载体上方形成第一半导体管芯层包括在载体上方形成第一聚合物层，在第一聚合物层中形成浅沟槽，在浅沟槽中形成导电接触件，并且在第一聚合物层上方放置第一半导体管芯。
在上述方法中，其中，所述第一聚合物层和所述导电接触件是第一再分布层(RDL)的部分。
在上述方法中，其中，在所述浅沟槽中形成所述导电接触件还包括形成用于电镀操作的晶种层。
在上述方法中，还包括在所述第一再分布层上方形成第二再分布层。
在上述方法中，其中，所述蚀刻操作包括干蚀刻操作。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。
此外，本申请的范围不限于本申请中描述的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤的具体实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以使用现有的或今后开发的用于执行与本文描述的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤。因此，所附权利要求旨在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种半导体封装件，包括：
第一半导体管芯层，具有有源表面；
导电接触件，通过再分布层电连接至所述有源表面，所述导电接触件的侧壁由绝缘层围绕；以及
焊料凸块，连接至所述导电接触件，
其中，晶种层位于所述导电接触件的所述侧壁和所述绝缘层之间，其中，所述再分布层与所述绝缘层位于所述导电接触件的相对两侧，所述再分布层中的第一金属线的一部分与所述导电接触件纵向上重叠，所述第一金属线的另一部分与所述有源表面纵向上重叠。
2.根据权利要求1所述的半导体封装件，其中，所述导电接触件还包括从所述绝缘层突出并且连接至所述焊料凸块的台状件。
3.根据权利要求1所述的半导体封装件，其中，所述导电接触件包括绝缘通孔(TIV)。
4.根据权利要求3所述的半导体封装件，还包括第二半导体管芯层，通过位于所述第一半导体管芯层的无源表面上方的所述焊料凸块电连接至所述导电接触件。
5.根据权利要求4所述的半导体封装件，其中，所述第二半导体管芯层包括动态随机存取存储器(DRAM)。
6.根据权利要求1所述的半导体封装件，其中，所述侧壁包括锥形。
7.根据权利要求1所述的半导体封装件，其中，所述第一半导体管芯层包括芯片上硅(SOC)管芯。
8.一种半导体封装件，包括：
第一半导体管芯层，具有有源表面；
导电接触件，通过RDL电连接至所述有源表面，所述导电接触件的侧壁由绝缘层围绕；以及
焊料凸块，连接至所述导电接触件，
其中，晶种层位于所述导电接触件的所述侧壁和所述绝缘层之间，
其中，所述导电接触件包括再分布层(RDL)的第一通孔，
所述第一通孔与所述有源表面位于所述第一半导体管芯层的同一侧，并且所述第一通孔与所述有源表面在纵向上重叠。
9.一种用于制造半导体封装件的方法，包括：
提供载体；
在所述载体上方形成绝缘层；
在所述绝缘层上方形成第一半导体管芯层，包括：
在所述绝缘层中形成浅沟槽；
在所述浅沟槽中形成导电接触件；和
在所述绝缘层上方放置第一半导体管芯，在所述第一半导体管芯上方形成再分布层；
将所述载体从所述绝缘层脱粘；以及
通过蚀刻操作从所述绝缘层暴露所述导电接触件，其中，在所述浅沟槽中形成所述导电接触件还包括形成用于电镀操作的晶种层，
其中，所述再分布层中的第一金属线的一部分与所述导电接触件纵向上重叠，所述第一金属线的另一部分与所述第一半导体管芯层的有源表面纵向上重叠。
10.一种用于制造半导体封装件的方法，包括：
提供载体；
在所述载体上方形成第一半导体管芯层，包括：
在所述载体上方形成第一聚合物层；
在所述第一聚合物层中形成浅沟槽；
在所述浅沟槽中形成导电接触件；和
在所述第一聚合物层上方放置第一半导体管芯；
将所述载体从所述第一聚合物层脱粘；以及
通过蚀刻操作从所述第一聚合物层暴露所述导电接触件，其中，在所述浅沟槽中形成所述导电接触件还包括形成用于电镀操作的晶种层，
其中，所述第一聚合物层和所述导电接触件是第一再分布层(RDL)的部分，
所述导电接触件与所述聚合物层的有源表面位于所述第一半导体管芯层的同一侧，并且所述导电接触件与所述有源表面在纵向上重叠。
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