CN1484308A - 开口式多芯片堆叠封装体 - Google Patents

开口式多芯片堆叠封装体 Download PDF

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CN1484308A
CN1484308A CNA021431981A CN02143198A CN1484308A CN 1484308 A CN1484308 A CN 1484308A CN A021431981 A CNA021431981 A CN A021431981A CN 02143198 A CN02143198 A CN 02143198A CN 1484308 A CN1484308 A CN 1484308A
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chip
substrate
packaging body
opening
open type
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Л
谢文乐
黄富裕
黄宁
陈慧萍
吕淑婉
吴拓松
蔡智宇
陈美华
吕佳玲
王郁茹
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HUATAI ELECTRONICS CO Ltd
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HUATAI ELECTRONICS CO Ltd
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

一种开口式多芯片堆叠封装体，包含：一基板，其具有第一面及第二面，该基板上设有一穿透的开口；该基板包括有两层电路布线；一第一芯片，设于该基板第一面的开口上方且焊接于该开口外围区域的基板第一面上的电路布线上；一第二芯片，该芯片与该第一芯片相叠粘合，并将该第二芯片以金线作电气接合至基板第一面的电路布线的位置上；一第三芯片，该芯片设于该基板第二面的开口下方，且与第一芯片中心部位焊接，并以填胶充填于第一芯片与第三芯片及第一芯片与基板第一面之间区域；一封装体，包覆于该基板第一面上方以及该第二芯片与基板接合的金线外围。本发明既可增加封装体的I/O密度及功能，又可压低成本并可以降低整个封装体高度。

Description

开口式多芯片堆叠封装体
[技术领域]
本发明是关于一种开口式多芯片堆叠封装体，其是应用开口式基板的设计，结合覆晶构装(Flip Chip Package)技术，与打线接合技术(Wire Bonding)将至少三层芯片层叠设置在一起。
[背景技术]
一般而言，在习知的多芯片封装技术之中常见如图1A所示的结构，是于一基板1’的正面上贴一第一芯片2’，并以打线接合技术，由第一芯片2’拉一金线21’至基板1’上与之电气接合，另以一较小的第二芯片3’贴于第一芯片2’顶面上，并同样以金线31’与基板1’第一面11’接合；而基板1’第一面11’是利用多层的电路将信号传递到第二层12’的锡球5’上，最后再以一封装材料覆盖两芯片及其金线(21’、31’)，成为一封装体4’；另有一习知技术是如图1B，是于一基板1’中心设一开口13’，并以一第一芯片2’的凸块21’接合于基板1’第一面11’的开口13’外围区域，并以一第二芯片3’的凸块31’焊接于第一芯片2’的下方的中心区域，并予以封胶成一封装体4’。
上述的习知多芯片构装技术并不同时具备高I/O密度的高功能与低成本的需求，原因为上述的结构体为传统的打线接合技术或纯覆晶接合技术，一则无法达成提高I/O密度的目的，一则若增加密度时，无法降低成本。
[发明内容]
本发明的目的是提供一种开口式多芯片堆叠封装体，既可增加封装体的I/O密度及功能，又可有效地压低成本并可以降低整个封装体高度，还可沿用旧有的打金线技术及设备。
为了达到上述目的，本发明提供一种开口式多芯片堆叠封装体，其特征在于：包含：
一基板，该基板具有第一面及第二面，该基板上至少设有一穿透的开口；该基板上至少设有两层电路布线；
至少一第一芯片，该芯片设于该基板第一面的开口上方，且通过多数个凸块焊接于该开口外围区域的基板第一面上以与电路布线电气连接；
至少一第二芯片，设于该第一芯片上方且与该第一芯片相叠粘合，该第二芯片以金线与基板第一面的电路布线电气连接；
至少一第三芯片，该第三芯片设于该基板第二面的开口下方，第三芯片尺寸小于第一芯片，且以多数个凸块与第一芯片中心部位电气连接，并以填胶充填于第一芯片与第三芯片之间及第一芯片与基板第一面之间；
一封装体，该封装体包覆于该基板第一面上方以及该第二芯片与基板连接的金线外围。
所述的开口式多芯片堆叠封装体，其特征在于：该基板的第一面的开口位置外围可设一大于该开口的凹槽，且该第一芯片接合于该基板的凹槽面上。
综上所述，本发明开口式多芯片堆叠封装体是应用开口式基板的设计，结合了覆晶构装(Flip Chip Package)技术与廉价的打线接合技术(Wire Bonding)将至少三层芯片层叠结合设置在一起，既可增加封装体的I/O密度及功能，又可有效地压低成本并可以降低整个封装体高度。本发明可沿用旧有的打金线技术及设备，而不必全部改用新设备，以降低生产成本。
兹将上述的构造，配合附图及较佳实施例说明如下：
[附图说明]
图1A、B是习知多芯片堆叠封装结构示意图。
图2是本发明的开口式多芯片堆叠封装的一较佳实施例的剖面示意图。
图3是本发明的另一实施例的剖面示意图。
[具体实施方式]
首先请参阅图2，其图示为本发明的较佳实施例，本发明的开口式多芯片堆叠封装体，包含有：
一基板1，该基板1具有第一面11及第二面12，基板1上至少设有一穿透的开口13，另为使第一面11的电路信号得以传递至第二面12，该基板1上至少设有两层电路布线，以传输电气信号；
一第一芯片2，该芯片设于基板1第一面11之开口13上方位置处，且藉由覆晶接合技术将多数个凸块21焊接于开口13外围区域的基板1第一面11上的电路布线上以作电气连接；
一第二芯片3，该芯片与上述第一芯片2相叠粘合，并将第二芯片3以金线31作电气接合至基板1第一面11的电路布线的位置上以作电气连接；
一第三芯片4，该芯片设于基板第二面之开口下方位置，其芯片尺寸小于第一芯片2，且可藉由多数个凸块41与第一芯片2中心部位焊接作电气接合，并以填胶7充填于第一芯片2与第三芯片4及第一芯片2与基板1第一面11之间的区域；
一封装体5，是于基板1第一面11上方，并包覆第二芯片3与基板1接合的金线31外围。
另请参照图3的本发明另一实施例，该基板1的第一面11的开口13外围处设一更大的凹槽14，并将第一芯片2的凸块21焊接于凹槽14的表面上。

Claims (2)

1、一种开口式多芯片堆叠封装体，其特征在于：包含：
一基板，该基板具有第一面及第二面，该基板上至少设有一穿透的开口；该基板上至少设有两层电路布线；
至少一第一芯片，该芯片设于该基板第一面的开口上方，且通过多数个凸块焊接于该开口外围区域的基板第一面上以与电路布线电气连接；
至少一第二芯片，设于该第一芯片上方且与该第一芯片相叠粘合，该第二芯片以金线与基板第一面的电路布线电气连接；
至少一第三芯片，该第三芯片设于该基板第二面的开口下方，第三芯片尺寸小于第一芯片，且以多数个凸块与第一芯片中心部位电气连接，并以填胶充填于第一芯片与第三芯片之间及第一芯片与基板第一面之间；
一封装体，该封装体包覆于该基板第一面上方以及该第二芯片与基板连接的金线外围。
2、如权利要求1所述的开口式多芯片堆叠封装体，其特征在于：该基板的第一面的开口位置外围设一大于该开口的凹槽，且该第一芯片接合于该基板的凹槽面上。
CNA021431981A 2002-09-17 2002-09-17 开口式多芯片堆叠封装体 Pending CN1484308A (zh)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100448002C (zh) * 2005-10-09 2008-12-31 采钰科技股份有限公司 堆叠式芯片的制法
CN100530636C (zh) * 2007-11-09 2009-08-19 中国科学院上海微系统与信息技术研究所 三维多芯片封装模块和制作方法
CN101872757B (zh) * 2009-04-24 2012-05-23 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
CN102468277A (zh) * 2010-11-11 2012-05-23 三星半导体(中国)研究开发有限公司 多芯片层叠封装结构及其制造方法
WO2012155858A1 (en) * 2011-05-19 2012-11-22 Versitech Ltd. Chip stacking
CN103187404A (zh) * 2011-12-31 2013-07-03 刘胜 半导体芯片堆叠封装结构及其工艺
CN103582946A (zh) * 2011-05-03 2014-02-12 泰塞拉公司 具有到封装表面的线键合的封装堆叠组件
CN104538381A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法
WO2018098647A1 (zh) * 2016-11-30 2018-06-07 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100448002C (zh) * 2005-10-09 2008-12-31 采钰科技股份有限公司 堆叠式芯片的制法
CN100530636C (zh) * 2007-11-09 2009-08-19 中国科学院上海微系统与信息技术研究所 三维多芯片封装模块和制作方法
CN101872757B (zh) * 2009-04-24 2012-05-23 南茂科技股份有限公司 凹穴芯片封装结构及使用其的层叠封装结构
CN102468277A (zh) * 2010-11-11 2012-05-23 三星半导体(中国)研究开发有限公司 多芯片层叠封装结构及其制造方法
CN103582946A (zh) * 2011-05-03 2014-02-12 泰塞拉公司 具有到封装表面的线键合的封装堆叠组件
CN103582946B (zh) * 2011-05-03 2017-06-06 泰塞拉公司 具有到封装表面的线键合的封装堆叠组件
WO2012155858A1 (en) * 2011-05-19 2012-11-22 Versitech Ltd. Chip stacking
CN103187404A (zh) * 2011-12-31 2013-07-03 刘胜 半导体芯片堆叠封装结构及其工艺
CN104538381A (zh) * 2014-12-30 2015-04-22 华天科技（西安）有限公司 一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法
WO2018098647A1 (zh) * 2016-11-30 2018-06-07 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法
CN110088884A (zh) * 2016-11-30 2019-08-02 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法
US10615151B2 (en) 2016-11-30 2020-04-07 Shenzhen Xiuyuan Electronic Technology Co., Ltd Integrated circuit multichip stacked packaging structure and method

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