CN1505149A - 多芯片集成电路的立体封装装置 - Google Patents

多芯片集成电路的立体封装装置 Download PDF

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CN1505149A
CN1505149A CNA021548463A CN02154846A CN1505149A CN 1505149 A CN1505149 A CN 1505149A CN A021548463 A CNA021548463 A CN A021548463A CN 02154846 A CN02154846 A CN 02154846A CN 1505149 A CN1505149 A CN 1505149A
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黄富裕
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HUATAI ELECTRONICS CO Ltd
Orient Semiconductor Electronics Ltd
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HUATAI ELECTRONICS CO Ltd
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Abstract

一种多芯片集成电路的立体封装装置，包含：一基板，其板面上预留有与芯片作接合的位置，且该基板上至少设有一开孔，打线接合用的金线穿设过该开孔，至少一第一芯片，该第一芯片先与该基板以芯片接合剂接合后，并与该基板作打线接合，至少一第二芯片，该第二芯片与该基板作覆晶接合，该第二芯片和该基板的接合位置位于该基板和该第一芯片的接合位置的另侧，该金线一端是与该基板的焊垫连接，另一端穿过该开孔而与该第一芯片上的脚垫接通，一封装体，是由该第二芯片的填胶延伸包覆住该基板的开孔、该金线，并与该第一芯片的芯片接合剂连结而成。本发明可增加封装体的I/O密度及功能，并有效地降低封装成本。

Description

多芯片集成电路的立体封装装置
[技术领域]
本发明是关于一种封装装置，特别是关于一种多芯片集成电路的立体封装装置。
[背景技术]
一般而言，在习知的多芯片集成电路的立体封装技术之中常见如图1A或图2A所示的结构，其主要的结构特征是于一基板1a’、1b’，上，或将第一芯片11a’与第二芯片12a’互相叠设，或是将第一芯片11b’与第二芯片12b’互相叠设。如图1B所示，则是将第一芯片21a’与第二芯片22a’两芯片并列，如图2B所示是将第一芯片21b’与第二芯片22b’两芯片并列。如图1C、2C所示，是将第一芯片31a’、31b’与第二芯片32a’、32b’两芯片分别接合于基板3a’、3b’的正、反两面上，并以芯片上脚垫结构(中央脚垫结构或周边脚垫结构)的不同，而设有不同形态的金线13a’、14a’、23a’、24a’、33a’、34a’以及13b’、14b’、23b’、24b’、33b’、34b’作为引线。
上述的习知立体构装技术并不易应用于高I/O密度与高功能需求的封装件，原因为上述的结构体多为传统的打线接合技术所组合，在其金线的数目上有其设计及施工上的局限，在某些要求高功能性的封装件上，相对地该I/O脚位的密度亦相对地提高，上述的习知技术即无法适用。
[发明内容]
本发明的目的是在于提供一种多芯片集成电路的立体封装装置，利用基板上设计的开孔，结合可提高I/O脚位的覆晶接合技术来满足上述的高密度I/O脚位、高功能的封装件的需要。
本发明的次要目的是提供一种多芯片集成电路的立体封装装置，可沿用旧有的打金线技术及设备，而不必全部改用全新的机台，维持既有的低成本构装要件。
为了达到上述目的，本发明提供一种多芯片集成电路的立体封装装置，包含：
一基板，
至少一第一芯片，该第一芯片与该基板以芯片接合剂接合，并与该基板以金线作打线接合，
至少一第二芯片，该第二芯片与该基板作覆晶接合，该第二芯片和该基板的接合位置位于该基板和该第一芯片的接合位置的另一侧，其特征在于：
该基板上至少设有一开孔，该打线接合的金线由该基板与连接第二芯片同侧的该基板的焊垫穿过该基板的开孔而与该第一芯片上的脚垫相接，
一封装体，是由该第二芯片的填胶延伸包覆住该基板的开孔及该第一芯片与该基板接合的金线与脚垫周围，并与该第一芯片的芯片接合剂连结成一体。
所述的多芯片集成电路的立体封装装置，其特征在于：该基板的开孔位置可以是在该第二芯片与该基板接合区域的中心位置，且该第一芯片与该基板作打线接合的电性连接的电路面上的脚垫为中央脚垫结构。
所述的多芯片集成电路的立体封装装置，其特征在于：于接合该第一芯片同侧外围的该基板上设有球栅阵列的锡球。
所述的多芯片集成电路的立体封装装置，其特征在于：该基板的开孔也可以是位于该基板与该第二芯片接合区域外围的外侧位置，且该第一芯片与该基板作打线接合的电性连接的电路面上的脚垫为周边脚垫结构。
所述的多芯片集成电路的立体封装装置，其特征在于：于接合该第二芯片同侧、开孔外围的基板上设有球栅阵列的锡球。
所述的多芯片集成电路的立体封装装置，其特征在于：一第三芯片的非电路面以芯片接合剂接合于该第一芯片的非电路面上，并由该第三芯片的电路面上的脚垫与基板作打线接合，再以芯片封装剂将第三芯片与第一芯片包覆封装。
由上述可知，本发明的多芯片集成电路的立体封装装置结合芯片的廉价打线接合技术与高密度覆晶接合技术于一体，即可增加封装体的I/O密度及功能，又可有效地降低封装成本。
[附图说明]
图1A、1B及1C是三种习知多芯片集成电路立体封装结构示意图。
图2A、2B及2C是另三种习知多芯片集成电路立体封装结构示意图。
图3A是本发明的第一实施例的剖面示意图。
图3B是本发明的第二实施例的剖面示意图。
图3C是本发明的第三实施例的剖面示意图。
[具体实施方式]
兹将上述的构造，配合附图及较佳实施例述明如下：
首先请参阅图3A，其图示为本发明的第一实施例，其包含有：
一基板1a，其板面上预留有与芯片作接合的位置，且基板1a上至少设有一开孔11a，可供打线接合时金线22a穿过，其开孔11a位置是在第二芯片3a与基板1a接合区域的中心位置，且位于接合第一芯片2a同侧外围的基板上设有球栅阵列的锡球13a。
一第一芯片2a，该芯片先与基板1a以芯片接合剂6接合后，并与基板1a作打线接合，且该接合的电性连接的电路面上的脚垫21a为中央脚垫结构，且其第一芯片2a接合的位置恰与第二芯片3a与基板1a接合的位置相反，而其打线接合的金线22a的一端是与第二芯片3a同侧的基板1a的焊垫12a连接，另一端穿过基板1a的开孔11a而与第一芯片2a上的脚垫21a接通。
一第二芯片3a，该芯片与上述基板1a作覆晶接合，其接合位置恰为基板1a与第一芯片2a接合位置的另一侧。
一封装体7，是由第二芯片3a的填胶5延伸包覆住基板1a的开孔11a、第一芯片2a与基板1a接合的金线22a与脚垫21a周围，并与第一芯片2a的芯片接合剂6连结而成一封装体7。
续请参照图3B所示，其图示中揭露本发明的第二实施例，其包含有：
一基板1b，其板面上预留有与芯片作接合的位置以供芯片接合，且基板1b上至少设有一开孔11b，可供打线接合时金线22b穿过，其开孔11b位置是位于基板1b与第二芯片3b接合区域外围的外侧位置上，而于接合第二芯片3b同侧的开孔11b外围的基板1b上设有球栅阵列的锡球13b。
一第一芯片2b，该芯片先与基板1b以芯片接合剂6接合后，并与基板1b作打线接合，且该接合的电性连接的电路面上的脚垫21b为周边脚垫结构，且其第一芯片2b接合的位置恰与第二芯片3b与基板1b接合的位置相反，而其打线接合的金线22b的一端是与第二芯片3b同侧的基板1b的焊垫12b连接，另一端穿过基板1b的开孔11b而与第一芯片2b上的脚垫21b接通。
一第二芯片3b，该芯片与上述基板1b作覆晶接合，其接合位置恰为基板1b与第一芯片2b接合位置的异侧。
一封装体7，是由第二芯片3b的填胶5延伸包覆住基板1b的开孔11b、第一芯片2b与基板1b接合的金线22b与脚垫21b周围，并与第一芯片2b的芯片接合剂6连结而成一封装体7。
由第二实施例中还可延伸出第三实施例，如图3C中所示，于第一芯片2c的非电路面上再与一第三芯片4c的非电路面以芯片接合剂接合，并由第三芯片4c的电路面上的脚垫41c与基板1c作打线接合，最后再以芯片封装剂8将第三芯片4c与第一芯片2c包覆封装。

Claims (6)

1、一种多芯片集成电路的立体封装装置，包含：
一基板，
至少一第一芯片，该第一芯片与该基板以芯片接合剂接合，并与该基板以金线作打线接合，
至少一第二芯片，该第二芯片与该基板作覆晶接合，该第二芯片和该基板的接合位置位于该基板和该第一芯片的接合位置的另一侧，其特征在于：
该基板上至少设有一开孔，该打线接合的金线由该基板与连接第二芯片同侧的该基板的焊垫穿过该基板的开孔而与该第一芯片上的脚垫相接，
一封装体，是由该第二芯片的填胶延伸包覆住该基板的开孔及该第一芯片与该基板接合的金线与脚垫周围，并与该第一芯片的芯片接合剂连结成一体。
2、如权利要求1所述的多芯片集成电路的立体封装装置，其特征在于：该基板的开孔位置是在该第二芯片与该基板接合区域的中心位置，且该第一芯片与该基板作打线接合的电性连接的电路面上的脚垫为中央脚垫结构。
3、如权利要求2所述的多芯片集成电路的立体封装装置，其特征在于：于接合该第一芯片同侧外围的该基板上设有球栅阵列的锡球。
4、如权利要求1所述的多芯片集成电路的立体封装装置，其特征在于：该基板的开孔是位于该基板与该第二芯片接合区域外围的外侧位置，且该第一芯片与该基板作打线接合的电性连接的电路面上的脚垫为周边脚垫结构。
5、如权利要求4所述的多芯片集成电路的立体封装装置，其特征在于：于接合该第二芯片同侧、开孔外围的基板上设有球栅阵列的锡球。
6、如权利要求5所述的多芯片集成电路的立体封装装置，其特征在于：一第三芯片的非电路面以芯片接合剂接合于该第一芯片的非电路面上，并由该第三芯片的电路面上的脚垫与基板作打线接合，并以芯片封装剂将第三芯片与第一芯片包覆封装。
CNA021548463A 2002-12-02 2002-12-02 多芯片集成电路的立体封装装置 Pending CN1505149A (zh)

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Cited By (7)

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CN100411123C (zh) * 2005-11-25 2008-08-13 全懋精密科技股份有限公司 半导体芯片埋入基板的结构及制法
CN100499116C (zh) * 2007-03-21 2009-06-10 威盛电子股份有限公司 芯片封装体
CN100530636C (zh) * 2007-11-09 2009-08-19 中国科学院上海微系统与信息技术研究所 三维多芯片封装模块和制作方法
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装
CN102290399A (zh) * 2010-06-17 2011-12-21 国碁电子(中山)有限公司 堆叠式芯片封装结构及方法
CN103066033A (zh) * 2007-08-24 2013-04-24 株式会社半导体能源研究所 半导体装置
CN106449440A (zh) * 2016-10-20 2017-02-22 江苏长电科技股份有限公司 一种具有电磁屏蔽功能的封装结构的制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411123C (zh) * 2005-11-25 2008-08-13 全懋精密科技股份有限公司 半导体芯片埋入基板的结构及制法
CN100499116C (zh) * 2007-03-21 2009-06-10 威盛电子股份有限公司 芯片封装体
CN103066033A (zh) * 2007-08-24 2013-04-24 株式会社半导体能源研究所 半导体装置
CN103066033B (zh) * 2007-08-24 2016-07-06 株式会社半导体能源研究所 半导体装置
CN100530636C (zh) * 2007-11-09 2009-08-19 中国科学院上海微系统与信息技术研究所 三维多芯片封装模块和制作方法
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装
CN102290399A (zh) * 2010-06-17 2011-12-21 国碁电子(中山)有限公司 堆叠式芯片封装结构及方法
CN102290399B (zh) * 2010-06-17 2013-08-28 国碁电子(中山)有限公司 堆叠式芯片封装结构及方法
CN106449440A (zh) * 2016-10-20 2017-02-22 江苏长电科技股份有限公司 一种具有电磁屏蔽功能的封装结构的制造方法
CN106449440B (zh) * 2016-10-20 2019-02-01 江苏长电科技股份有限公司 一种具有电磁屏蔽功能的封装结构的制造方法

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