CN104538381A - 一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法 - Google Patents

一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法 Download PDF

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CN104538381A
CN104538381A CN201410843716.8A CN201410843716A CN104538381A CN 104538381 A CN104538381 A CN 104538381A CN 201410843716 A CN201410843716 A CN 201410843716A CN 104538381 A CN104538381 A CN 104538381A
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substrate
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陈文钊
于大全
陈兴隆
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

本发明公开了一种采用贴膜实现倒装芯片裸露的封装结构，所述封装结构主要由逻辑芯片、逻辑芯片焊球、感应芯片焊球、感应芯片、基板、塑封体组成；所述逻辑芯片有逻辑芯片焊球，感应芯片有感应芯片焊球，基板有开槽，基板开槽的长度略大于感应芯片的长度，所述逻辑芯片的逻辑芯片焊球与基板相连，所述感应芯片位于基板的开槽内，其感应芯片焊球与逻辑芯片连接；所述塑封体包围逻辑芯片、逻辑芯片焊球、感应芯片焊球以及感应芯片和基板的上表面。该发明通过贴膜实现了塑封，通过揭膜实现了芯片裸露，提高了感应效果，有效的保护感应芯片并且防止溢料。

Description

一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法
技术领域
本发明涉及集成电路封装领域，具体是一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法。
背景技术
随着移动设备指纹识别芯片的广泛应用，指纹芯片封装领域采用传统WB技术面临感应区域无法裸露，如果实现感应芯片裸露，需要针对每一种产品投资特定模具，且投资额巨大。由于WB有线弧，很难实现感应芯片和封装体表面在同一表面，影响装配完成后的感应效果。现有技术提出一种在感应芯片边缘制作台阶，将芯片表面焊盘通过导电层引至该台阶处，然后再进行打线，该方式避免了焊线对感应区域与封装体外界的距离的影响，但是，在硅表面制作台阶工艺较为复杂，同时，对传感芯片本身的刻蚀形成台阶、减薄、金属布线等操作容易造成芯片损坏，或者产生微裂纹等缺陷使得产品的可靠性下降。
发明内容
针对上述现有技术存在的问题，本发明提供了一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法，通过贴膜实现了塑封，通过揭膜实现了芯片裸露，提高了感应效果，有效的保护感应芯片并且防止溢料。
一种采用贴膜实现倒装芯片裸露的封装结构，所述封装结构主要由逻辑芯片、逻辑芯片焊球、感应芯片焊球、感应芯片、基板、塑封体组成；所述逻辑芯片有逻辑芯片焊球，感应芯片有感应芯片焊球，基板有开槽，基板开槽的长度略大于感应芯片的长度，所述逻辑芯片的逻辑芯片焊球与基板相连，所述感应芯片位于基板的开槽内，其感应芯片焊球与逻辑芯片连接；所述塑封体包围逻辑芯片、逻辑芯片焊球、感应芯片焊球以及感应芯片和基板的上表面。
所述感应芯片的下表面和基板的下表面在同一平面上。
一种采用贴膜实现倒装芯片裸露的封装结构的制备方法，其具体按照以下步骤进行：
步骤一：逻辑芯片上连接逻辑芯片焊球；
步骤二：感应芯片上连接感应芯片焊球；
步骤三：基板上开槽，开槽的长度略大于感应芯片的长度；
步骤四：逻辑芯片通过逻辑芯片焊球与基板相连；
步骤五：感应芯片位于基板的开槽内，其感应芯片焊球与逻辑芯片连接；
步骤六：在基板和感应芯片下表面贴胶膜；
步骤七：塑封体包围逻辑芯片、逻辑芯片焊球、感应芯片焊球以及感应芯片和基板的上表面；
步骤八：揭胶膜，封装成品。
附图说明
图1为在逻辑芯片上植球图；
图2为在感应芯片上植球图；
图3为在基板上加工开槽图；
图4为逻辑芯片贴装图；
图5为感应芯片贴装图；
图6为基板背面贴膜图；
图7为塑封图；
图8为除膜封装成品图。
图中，1为逻辑芯片，2为逻辑芯片焊球，3为感应芯片焊球，4为感应芯片，5为基板，6为胶膜，7为塑封体。
具体实施方式
下面参考附图来对本发明作进一步说明。
如图8所示，一种采用贴膜实现倒装芯片裸露的封装结构，所述封装结构主要由逻辑芯片1、逻辑芯片焊球2、感应芯片焊球3、感应芯片4、基板5、塑封体7组成；所述逻辑芯片1有逻辑芯片焊球2，感应芯片4有感应芯片焊球3，基板5有开槽，基板5开槽的长度略大于感应芯片4的长度，所述逻辑芯片1的逻辑芯片焊球2与基板5相连，所述感应芯片4位于基板5的开槽内，其感应芯片焊球3与逻辑芯片1连接；所述塑封体7包围逻辑芯片1、逻辑芯片焊球2、感应芯片焊球3以及感应芯片4和基板5的上表面。
所述感应芯片4的下表面和基板5的下表面在同一平面上。
一种采用贴膜实现倒装芯片裸露的封装结构的制备方法，其具体按照以下步骤进行：
步骤一：逻辑芯片1上连接逻辑芯片焊球2，如图1所示；
步骤二：感应芯片4上连接感应芯片焊球3，如图2所示；
步骤三：基板5上开槽，开槽的长度略大于感应芯片4的长度，如图3所示；
步骤四：逻辑芯片1通过逻辑芯片焊球2与基板5相连，如图4所示；
步骤五：感应芯片4位于基板5的开槽内，其感应芯片焊球3与逻辑芯片1连接，如图5所示；
步骤六：在基板5和感应芯片4下表面贴胶膜6，如图6所示；
步骤七：塑封体7包围逻辑芯片1、逻辑芯片焊球2、感应芯片焊球3以及感应芯片4和基板5的上表面，如图7所示；
步骤八：揭胶膜6，封装成品，如图8所示。
本发明采用倒装芯片堆叠封装技术及TSV工艺(要使感应芯片感应区朝下，就要在感应芯片背面植球，所以先通过TSV做通孔，图中没有画出TSV通孔和RDL层)对指纹识别芯片进行封装，实现了感应芯片与逻辑芯片及存储芯片堆叠，有效的减小了封装尺寸，提高产品的可靠性。同时使感应芯片裸露，提高了感应效果。采用基板背面贴膜技术，有效的保护感应芯片并且防止溢料，通过普通塑封模具实现一次塑封，有效减少工艺环节及设备投资。

Claims (3)

1.一种采用贴膜实现倒装芯片裸露的封装结构，其特征在于，所述封装结构主要由逻辑芯片(1)、逻辑芯片焊球(2)、感应芯片焊球(3)、感应芯片(4)、基板(5)、塑封体(7)组成；所述逻辑芯片(1)有逻辑芯片焊球(2)，感应芯片(4)有感应芯片焊球(3)，基板(5)有开槽，基板(5)开槽的长度略大于感应芯片(4)的长度，所述逻辑芯片(1)的逻辑芯片焊球(2)与基板(5)相连，所述感应芯片(4)位于基板(5)的开槽内，其感应芯片焊球(3)与逻辑芯片(1)连接；所述塑封体(7)包围逻辑芯片(1)、逻辑芯片焊球(2)、感应芯片焊球(3)以及感应芯片(4)和基板(5)的上表面。
2.根据权利要求1所述的一种采用贴膜实现倒装芯片裸露的封装结构，其特征在于，所述感应芯片(4)的下表面和基板(5)的下表面在同一平面上。
3.一种采用贴膜实现倒装芯片裸露的封装结构的制备方法，其特征在于，其具体按照以下步骤进行：
步骤一：逻辑芯片(1)上连接逻辑芯片焊球(2)；
步骤二：感应芯片(4)上连接感应芯片焊球(3)；
步骤三：基板(5)上开槽，开槽的长度略大于感应芯片(4)的长度；
步骤四：逻辑芯片(1)通过逻辑芯片焊球(2)与基板(5)相连；
步骤五：感应芯片(4)位于基板(5)的开槽内，其感应芯片焊球(3)与逻辑芯片(1)连接；
步骤六：在基板(5)和感应芯片(4)下表面贴胶膜(6)；
步骤七：塑封体(7)包围逻辑芯片(1)、逻辑芯片焊球(2)、感应芯片焊球(3)以及感应芯片(4)和基板(5)的上表面；
步骤八：揭胶膜(6)，封装成品。
CN201410843716.8A 2014-12-30 2014-12-30 一种采用贴膜实现倒装芯片裸露的封装结构及其制备方法 Pending CN104538381A (zh)

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Application publication date: 20150422