TWI664756B - 用於ｍｒａｍ裝置之磁屏蔽封裝結構及其製造方法 - Google Patents

用於ｍｒａｍ裝置之磁屏蔽封裝結構及其製造方法 Download PDF

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TWI664756B
TWI664756B TW106137919A TW106137919A TWI664756B TW I664756 B TWI664756 B TW I664756B TW 106137919 A TW106137919 A TW 106137919A TW 106137919 A TW106137919 A TW 106137919A TW I664756 B TWI664756 B TW I664756B
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metal layer
metal
pair
semiconductor die
item
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TW201916420A (zh
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Shan Gao
山 高
Boo Yang Jung
鄭富陽
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Globalfoundries Singapore Pte. Ltd.
新加坡商格羅方德半導體私人有限公司
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Abstract

提供將MRAM結構的所有六面磁屏蔽於薄打線或薄覆晶接合封裝中的方法及所產生之裝置。具體實施例包括：形成嵌在一PCB基板之上半部、下半部之間的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔；將一半導體晶粒貼合至該PCB基板在該對金屬填充通孔之間的該上半部；通過該對金屬填充通孔使該半導體晶粒電氣連接至該PCB基板；將該PCB基板之該上半部在該對金屬填充通孔外的一部份向下移除到該第一金屬層；以及形成一第二金屬層於該半導體晶粒的相對四側上面及上，該第二金屬層座落於該第一金屬層上。

Description

用於MRAM裝置之磁屏蔽封裝結構及其製造方法
本揭示內容係有關用於半導體封裝的設計及製造方法。本揭示內容特別適用於積體電路(IC)中的磁性隨機存取記憶體(magnetic random access memory；簡稱MRAM)結構。
例如MRAM晶片的IC晶片通常囊封於保護封裝中以防止來自雜散干擾(stray)或外部施加電磁場的誤差以及防止在後續加工期間的受損。為了得到更好的保護，MRAM結構(打線接合式及覆晶式兩者)需要用保護層六面屏蔽，不過，習知的打線接合屏蔽法會導致高封裝厚度及較低的效率，因為(i)屏蔽材料沒有形成閉環(closed loop)，尤其是垂直型MRAM結構；(ii)打線接合焊盤(pad)區常常太大；以及(iii)如果印刷電路板(PCB)基板中的基板焊盤開口區太小的話，對打線接合來說是種製程挑戰。覆晶式MRAM封裝會引起額外問題，因為(i)相較於打線接合，覆晶式MRAM有較寬的底部屏蔽開口，因此會有較差 的磁屏蔽效率；以及(ii)底部屏蔽的個別開口促進金屬凸塊與屏蔽金屬間之電氣短路的高風險且在底部屏蔽上的微細間距開口方面構成限制。
第1圖是習知打線接合式MRAM封裝的橫截面圖，保護屏蔽層101及103各自形成於MRAM結構105之一部份的下面及上面，且隨後形成環氧模制化合物(EMC)層107於屏蔽層101及103、MRAM結構105及配線109上面。如上述，這種設計有問題，因為保護層101及103沒有六面囊封MRAM結構105。結果，MRAM結構105暴露於雜散干擾或外部施加電磁場以及後續的加工步驟。請參考第2圖，相較於傳統打線接合封裝(conventional wire bonding package)200，已知MRAM打線接合封裝202在形成保護層203及205於PCB基板207上面以保護MRAM結構209時顯示MRAM打線接合焊盤區的累積(用箭頭201表示)。此外，MRAM結構209與保護層203及205之間的預定距離增加封裝厚度。
因此，亟須一種方法能夠將MRAM結構的六面磁屏蔽而不犧牲封裝厚度。
本揭示內容的一方面為一種以薄封裝輪廓將MRAM結構之六面予以磁屏蔽的方法。
本揭示內容的另一方面為一種以薄封裝輪廓將MRAM結構之六面予以磁屏蔽的裝置。
本揭示內容的其他方面及特徵會在以下說 明中提出以及部份在本技藝一般技術人員審查以下內容或學習本揭示內容的實施後會明白。按照隨附申請專利範圍的特別提示，可實現及得到本揭示內容的優點。
根據本揭示內容，有些技術效果部份可用一種方法達成，其包括：形成嵌在一PCB基板之上半部、下半部之間的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔(metal filled via)；將一半導體晶粒貼合至該PCB基板在該對金屬填充通孔之間的該上半部；通過該對金屬填充通孔使該半導體晶粒電氣連接至該PCB基板；將該PCB基板之該上半部在該對金屬填充通孔外的一部份向下移除到該第一金屬層；以及形成一第二金屬層於該半導體晶粒的相對四側上面及上，該第二金屬層座落於該第一金屬層上。
本揭示內容的數個方面包括：形成由一鎳(Ni)-鐵(Fe)合金組成的該第一及該第二金屬層。另一方面包括：形成厚度有50微米(μm)至1000μm的該第一及該第二金屬層。其他數個方面包括：在該第一金屬層中形成側向分離的一對通孔；形成一介電層於該對通孔中且於第一金屬層的頂面及底面上面；移除該介電層穿過該對通孔的部份；以及在形成嵌在該PCB基板之上半部、下半部之間的該第一金屬層之前，用一金屬填滿該對通孔，而形成該對金屬填充通孔。又數個方面包括：藉由用配線接合該半導體晶粒，使該半導體晶粒電氣連接至該PCB基板。其他數個方面包括：藉由用數個凸塊下金屬(under-bump metallurgy，UBM)焊盤接合該半導體晶粒，使該半導體晶粒電氣連接至該PCB基板。又數個方面包括：該半導體晶粒用該等UBM焊盤電氣連接至該PCB基板，該方法更包括：在連接該半導體晶粒之前，在該等UBM焊盤與該PCB基板之該上半部之間形成一金屬層。另一方面包括：用以下方式形成該第二金屬層於該半導體晶粒上面：在該第二金屬層與該半導體晶粒之間形成有100μm至1,000μm的一間隙。其他數個方面包括：用以下方式形成該第二金屬層於該半導體晶粒上面：形成該第二金屬層於該半導體晶粒上。又數個方面包括：該半導體晶粒包括一MRAM結構。
本揭示內容的另一方面為一種裝置，其包括：嵌在一PCB基板之上半部、下半部之間的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔；在各通孔之側壁上以及在該第一金屬層之頂面及底面上面的一介電層；在該對金屬填充通孔之間貼合至該PCB基板之該上半部的一半導體晶粒；以及在該半導體晶粒之相對四側上面及上的一第二金屬層，該第二金屬層通過該PCB基板之該頂部座落於該第一金屬層上。
該裝置的數個方面包括：該第一及該第二金屬層包括Ni-Fe合金。另一方面包括：該第一及該第二金屬層有50μm至1000μm的厚度。其他方面包括：該第二金屬層在該半導體晶粒上面有100μm至1,000μm。又一方面包括：該第二金屬層在該半導體晶粒上。其他方面包括：該對金屬填充通孔包括銅。更一方面包括：該半導 體晶粒包括一MRAM結構。
本揭示內容的另一方面為一種方法，其包括：形成嵌在一PCB基板之上半部、下半部之間厚度有50μm至1000μm的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔；將一MRAM結構在該對金屬填充通孔之間貼合至該PCB基板之該上半部；藉由用數條配線或數個UBM焊盤接合該MRAM結構，使該MRAM結構通過該對金屬填充通孔電氣連接至該PCB基板；將該PCB基板之該上半部在該對金屬填充通孔外的一部份向下移除到該第一金屬層；以及在該MRAM結構的相對四側上面及上形成厚度有50μm至1000μm的一第二金屬層，該第二金屬層座落於該第一金屬層上。
本揭示內容的數個方面包括：形成由一Ni-Fe合金組成的該第一及該第二金屬層。又一方面包括：在該第一金屬層中形成側向分離的一對通孔；形成一介電層於該對通孔中以及於第一金屬層的頂面及底面上面；移除該介電層穿過該對通孔的部份；以及在形成該第一金屬層之前，用一金屬填充該對通孔，而形成該對金屬填充通孔。
熟諳此藝者由以下詳細說明可明白本揭示內容的其他方面及技術效果，其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。應瞭解，本揭示內容能夠做出其他及不同的具體實施例，以及在各種明顯的方面，能夠修改數個細節而不脫離本揭示 內容。因此，附圖及說明內容本質上應被視為圖解說明用而不是用來限定。
101、103‧‧‧保護屏蔽層、屏蔽層、保護層
105‧‧‧MRAM結構
107‧‧‧環氧模制化合物(EMC)層
109‧‧‧配線
200‧‧‧傳統打線接合封裝
201‧‧‧MRAM打線接合焊盤區
202‧‧‧已知MRAM打線接合封裝
203、205‧‧‧保護層
207、311‧‧‧PCB基板
209‧‧‧MRAM結構
301、309、501、801‧‧‧金屬層
303、305‧‧‧通孔、金屬填充通孔
307‧‧‧介電層
311a‧‧‧上半部
311b‧‧‧下半部
313‧‧‧開口
401、705‧‧‧半導體晶粒
403‧‧‧配線
405‧‧‧EMC層
701‧‧‧UBM焊盤
703‧‧‧底部填料
在此用附圖舉例說明而不是限定本揭示內容，圖中類似的元件用相同的元件符號表示。
第1圖及第2圖圖示用以將MRAM結構磁屏蔽於打線接合式MRAM封裝中的製程挑戰；第3圖至第5圖的橫截面圖根據一示範具體實施例示意圖示用以將MRAM結構的六面磁屏蔽於薄打線接合封裝中的加工流程；以及第6圖至第8圖的橫截面圖根據一示範具體實施例示意圖示用以將MRAM結構的六面磁屏蔽於薄覆晶封裝中的加工流程。
為了解釋，在以下的說明中，提出許多特定細節供徹底瞭解示範具體實施例。不過，顯然在沒有該等特定細節下或用等價配置仍可實施示範具體實施例。在其他情況下，眾所周知的結構及裝置用方塊圖圖示以免不必要地混淆示範具體實施例。此外，除非另有說明，在本專利說明書及申請專利範圍中表示成分、反應條件等等之數量、比例及數值性質的所有數字應被理解為在所有情況下可用措辭“約”來修飾。
本揭示內容針對且解決在形成磁屏蔽封裝結構於MRAM裝置上面後伴隨而來之高封裝厚度及低效 率的當前問題。尤其是，這個問題的解決係藉由在MRAM結構的六面上形成金屬屏蔽，而且底部金屬屏蔽嵌在PCB基板中，以及用穿過底部屏蔽金屬的通孔電氣連接於基板。
根據本揭示內容之數個具體實施例的方法包括：形成嵌在一PCB基板之上半部、下半部之間的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔。半導體晶粒在該對金屬填充通孔之間貼合至PCB基板的上半部，且半導體晶粒通過該對金屬填充通孔而電氣連接至PCB基板。PCB基板上半部在該對金屬填充通孔外的一部份被移除向下到第一金屬層，以及在該半導體晶粒的相對四側上面及上形成一第二金屬層，該第二金屬層座落於該第一金屬層上。
此外，熟諳此藝者由以下詳細說明可明白本揭示內容的其他方面、特徵及技術效果，其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。本揭示內容能夠做出其他及不同的具體實施例，而且能夠修改其在各種不同方面的數個細節。因此，附圖及說明內容本質上應被視為圖解說明用而不是用來限定。
第3圖至第5圖的橫截面圖根據一示範具體實施例示意圖示用以將MRAM結構的所有六面磁屏蔽於薄打線接合封裝中的加工流程。請參考第3圖，金屬層301，例如，由Ni-Fe合金形成，例如，厚度有50μm至1000μm。然後，形成穿過金屬層301的通孔303及305。 接下來，藉由首先於通孔303及305中以及於金屬層301上面及下面形成介電層307，然後蝕刻介電層307穿過通孔303及305(為了圖解說明而未圖示)，沿著通孔303及305的側壁且於金屬層301上面及下面形成例如由聚合物組成的介電層307。然後，通孔303及305填滿金屬層309，例如，銅。接下來，有上半部311a及下半部311b的PCB基板311各自形成於金屬層301的頂面及底面上面，且使金屬填充通孔303及305各自連接PCB基板311的上半部及下半部。隨後，圖案化PCB基板311a的上半部(用開口313表示)。
請參考第4圖，例如MRAM結構的半導體晶粒401在金屬填充通孔303及305之間貼合至PCB基板311的上半部311a。藉由用連接至金屬填充通孔303及305的配線403接合半導體晶粒401，使半導體晶粒401電氣連接至PCB基板311。隨後，EMC層405形成於半導體晶粒401及配線403上面。如第5圖所示，PCB基板311之上半部311a在該對金屬填充通孔303及305外的部份被蝕刻向下到金屬層301。接下來，在半導體晶粒401及EMC層405的相對四側上面及上形成由例如Ni-Fe合金組成的金屬層501，厚度有50μm至1000μm，例如，100μm至1,000μm，且坐落於金屬層301上。
第6圖至第8圖的橫截面圖根據一示範具體實施例示意圖示用以將MRAM結構的所有六面磁屏蔽於薄覆晶封裝中的加工流程。第6圖的初始裝置與第3圖 的裝置相同且使用相同的製程步驟形成。請參考第7圖，金屬層(為了圖解說明而未圖示)形成於PCB基板311之上半部311a的數個部份上。然後，在PCB基板311之上半部311a上的金屬層上，形成UBM焊盤701。隨後，形成底部填料(underfill)703於UBM焊盤701上面。接下來，使例如MRAM結構的半導體晶粒705與UBM焊盤701接合，然後使半導體晶粒705電氣連接至PCB基板311。如第8圖所示，將PCB基板311之上半部311a在該對金屬填充通孔303及305外的部份向下蝕刻到金屬層301。然後，在半導體晶粒705的相對四側上面及上形成例如由Ni-Fe合金組成的金屬層801，厚度有50μm至1000μm，且座落於金屬層301上。在此情形下，金屬層801形成於半導體晶粒705上，不過，吾等預期，也可形成於上面例如有100μm至1,000微米。
本揭示內容的具體實施例可實現數種技術效果，例如相對於習知MRAM封裝結構，有較高的屏蔽效率，較小的封裝厚度及有較小開口的保護金屬層。此外，有鑑於沒有用於MRAM封裝技術的已知覆晶解決方案，本發明方法提供一種適用於打線接合封裝及覆晶封裝兩者的MRAM封裝技術。此外，將金屬層嵌在PCB基板中可排除貼合底部金屬層的製程，從而簡化封裝製程。根據本揭示內容之具體實施例所形成的裝置可用於各種工業應用，例如，微處理器、智慧型手機、行動電話、手機、機上盒、DVD燒錄機及播放機、汽車導航、列表機及周邊設備，網 絡及電信設備，遊戲系統及數位相機。本揭示內容在產業上可用於包括MRAM的任何各種半導體裝置。
在以上說明中，特別用數個示範具體實施例描述本揭示內容。不過，顯然仍可做出各種修改及改變而不脫離本揭示內容更寬廣的精神及範疇，如申請專利範圍所述。因此，本專利說明書及附圖應被視為圖解說明用而非限定。應瞭解，本揭示內容能夠使用各種其他組合及具體實施例且在如本文所述的本發明概念範疇內能夠做出任何改變或修改。

Claims (20)

  1. 一種方法，包含：形成嵌在一印刷電路板(PCB)基板之上半部、下半部之間的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔；將一半導體晶粒貼合至該PCB基板在該對金屬填充通孔之間的該上半部；通過該對金屬填充通孔使該半導體晶粒電氣連接至該PCB基板；將該PCB基板之該上半部在該對金屬填充通孔外的一部份移除向下到該第一金屬層；以及形成一第二金屬層於該半導體晶粒的相對四側上面及上，該第二金屬層座落於該第一金屬層上。
  2. 如申請專利範圍第1項所述之方法，包含：形成由一鎳(Ni)-鐵(Fe)合金組成的該第一及該第二金屬層。
  3. 如申請專利範圍第1項所述之方法，包含：形成厚度有50微米(μm)至1000μm的該第一及該第二金屬層。
  4. 如申請專利範圍第1項所述之方法，更包含：在該第一金屬層中形成側向分離的一對通孔；形成一介電層於該對通孔中且於該第一金屬層的頂面及底面上面；移除該介電層穿過該對通孔的部份；以及在形成嵌在該PCB基板之該上半部、該下半部之間的該第一金屬層之前，用一金屬填滿該對通孔，而形成該對金屬填充通孔。
  5. 如申請專利範圍第1項所述之方法，包含用以下方式使該半導體晶粒電氣連接至該PCB基板：用配線接合該半導體晶粒。
  6. 如申請專利範圍第1項所述之方法，包含用以下方式使該半導體晶粒電氣連接至該PCB基板：用數個凸塊下金屬(UBM)焊盤接合該半導體晶粒。
  7. 如申請專利範圍第6項所述之方法，其中，該半導體晶粒用該等UBM焊盤電氣連接至該PCB基板，該方法更包含：在連接該半導體晶粒之前，在該等UBM焊盤與該PCB基板之該上半部之間形成一金屬層。
  8. 如申請專利範圍第1項所述之方法，包含用以下方式形成該第二金屬層於該半導體晶粒上面：在該第二金屬層與該半導體晶粒之間形成有100μm至1,000μm的一間隙。
  9. 如申請專利範圍第1項所述之方法，包含用以下方式形成該第二金屬層於該半導體晶粒上面：形成該第二金屬層於該半導體晶粒上。
  10. 如申請專利範圍第1項所述之方法，其中，該半導體晶粒包含一磁性隨機存取記憶體(MRAM)結構。
  11. 一種裝置，包含：第一金屬層，嵌在一印刷電路板(PCB)基板之上半部、下半部之間，該第一金屬層有側向分離的一對金屬填充通孔；介電層，在各通孔之側壁上且在該第一金屬層之頂面及底面上面；半導體晶粒，在該對金屬填充通孔之間貼合至該PCB基板之該上半部；以及第二金屬層，在該半導體晶粒之相對四側上面及上，該第二金屬層通過該PCB基板之該頂部而座落於該第一金屬層上。
  12. 如申請專利範圍第11項所述之裝置，其中，該第一及該第二金屬層包含鎳(Ni)-鐵(Fe)合金。
  13. 如申請專利範圍第11項所述之裝置，其中，該第一及該第二金屬層有50微米(μm)至1000μm的厚度。
  14. 如申請專利範圍第11項所述之裝置，其中，該第二金屬層在該半導體晶粒上面有100μm至1,000μm。
  15. 如申請專利範圍第11項所述之裝置，其中，該第二金屬層在該半導體晶粒上。
  16. 如申請專利範圍第11項所述之裝置，其中，該對金屬填充通孔包含銅(Cu)。
  17. 如申請專利範圍第11項所述之裝置，其中，該半導體晶粒包含一磁性隨機存取記憶體(MRAM)結構。
  18. 一種方法，包含：形成嵌在一印刷電路板(PCB)基板之上半部、下半部之間厚度有50微米(μm)至1000μm的一第一金屬層，該第一金屬層有側向分離的一對金屬填充通孔；將一MRAM結構在該對金屬填充通孔之間貼合至該PCB基板之該上半部；藉由用數條配線或數個凸塊下金屬(UBM)焊盤接合該MRAM結構，使該MRAM結構通過該對金屬填充通孔而電氣連接至該PCB基板；將該PCB基板之該上半部在該對金屬填充通孔外的一部份向下移除到該第一金屬層；以及在該MRAM結構的相對四側上面及上形成厚度有50μm至1000μm的一第二金屬層，該第二金屬層座落於該第一金屬層上。
  19. 如申請專利範圍第18項所述之方法，包含：形成由一鎳(Ni)-鐵(Fe)合金組成的該第一及該第二金屬層。
  20. 如申請專利範圍第18項所述之方法，更包含：在該第一金屬層中形成側向分離的一對通孔；形成一介電層於該對通孔中且於第一金屬層的頂面及底面上面；移除該介電層穿過該對通孔的部份；以及在形成該第一金屬層之前，用一金屬填充該對通孔，而形成該對金屬填充通孔。
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