CN109559998A - 用于mram装置的磁屏蔽封装结构及其制造方法 - Google Patents

用于mram装置的磁屏蔽封装结构及其制造方法 Download PDF

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CN109559998A
CN109559998A CN201811023657.4A CN201811023657A CN109559998A CN 109559998 A CN109559998 A CN 109559998A CN 201811023657 A CN201811023657 A CN 201811023657A CN 109559998 A CN109559998 A CN 109559998A
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metal layer
metal
semiconductor grain
pcb substrate
hole
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CN109559998B (zh
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高山
郑富阳
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GlobalFoundries Singapore Pte Ltd
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Abstract

本发明涉及用于MRAM装置的磁屏蔽封装结构及其制造方法，提供将MRAM结构的所有六面磁屏蔽于薄打线或薄覆晶接合封装中的方法及所产生的装置。具体实施例包括：形成嵌在一PCB衬底的上半部、下半部之间的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔；将一半导体晶粒贴合至该PCB衬底在该对金属填充通孔之间的该上半部；通过该对金属填充通孔使该半导体晶粒电气连接至该PCB衬底；将该PCB衬底的该上半部在该对金属填充通孔外的一部分向下移除到该第一金属层；以及形成一第二金属层于该半导体晶粒的相对四侧上面及上，该第二金属层座落于该第一金属层上。

Description

用于MRAM装置的磁屏蔽封装结构及其制造方法
技术领域
本揭示内容是有关用于半导体封装的设计及制造方法。本揭示内容特别适用于集成电路(IC)中的磁性随机存取内存(magnetic random access memory；简称MRAM)结构。
背景技术
例如MRAM芯片的IC芯片通常囊封于保护封装中以防止来自杂散干扰(stray)或外部施加电磁场的误差以及防止在后续加工期间的受损。为了得到更好的保护，MRAM结构(打线接合式及覆晶式两者)需要用保护层六面屏蔽，不过，现有的打线接合屏蔽法会导致高封装厚度及较低的效率，因为(i)屏蔽材料没有形成死循环(closed loop)，尤其是垂直型MRAM结构；(ii)打线接合焊盘(pad)区常常太大；以及(iii)如果印刷电路板(PCB)衬底中的衬底焊盘开口区太小的话，对打线接合来说是种制程挑战。覆晶式MRAM封装会引起额外问题，因为(i)相比于打线接合，覆晶式MRAM有较宽的底部屏蔽开口，因此会有较差的磁屏蔽效率；以及(i i)底部屏蔽的个别开口促进金属凸块与屏蔽金属间的电气短路的高风险且在底部屏蔽上的微细间距开口方面构成限制。
图1是现有打线接合式MRAM封装的横截面图，保护屏蔽层101及103各自形成于MRAM结构105的一部分的下面及上面，且随后形成环氧模制化合物(EMC)层107于屏蔽层101及103、MRAM结构105及配线109上面。如上述，这种设计有问题，因为保护层101及103没有六面囊封MRAM结构105。结果，MRAM结构105暴露于杂散干扰或外部施加电磁场以及后续的加工步骤。请参考图2，相比于传统打线接合封装(conventional wire bonding package)200，已知MRAM打线接合封装202在形成保护层203及205于PCB衬底207上面以保护MRAM结构209时显示MRAM打线接合焊盘区的累积(用箭头201表示)。此外，MRAM结构209与保护层203及205之间的预定距离增加封装厚度。
因此，亟须一种方法能够将MRAM结构的六面磁屏蔽而不牺牲封装厚度。
发明内容
本揭示内容的一方面为一种以薄封装轮廓将MRAM结构的六面予以磁屏蔽的方法。
本揭示内容的另一方面为一种以薄封装轮廓将MRAM结构的六面予以磁屏蔽的装置。
本揭示内容的其他方面及特征会在以下说明中提出以及部分在本领域一般技术人员审查以下内容或学习本揭示内容的实施后会明白。按照随附权利要求书的特别提示，可实现及得到本揭示内容的优点。
根据本揭示内容，有些技术效果部分可用一种方法达成，其包括：形成嵌在一PCB衬底的上半部、下半部之间的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔(metal filled via)；将一半导体晶粒贴合至该PCB衬底在该对金属填充通孔之间的该上半部；通过该对金属填充通孔使该半导体晶粒电气连接至该PCB衬底；将该PCB衬底的该上半部在该对金属填充通孔外的一部分向下移除到该第一金属层；以及形成一第二金属层于该半导体晶粒的相对四侧上面及上，该第二金属层座落于该第一金属层上。
本揭示内容的数个方面包括：形成由一镍(Ni)-铁(Fe)合金组成的该第一及该第二金属层。另一方面包括：形成厚度有50微米(μm)至1000μm的该第一及该第二金属层。其他数个方面包括：在该第一金属层中形成侧向分离的一对通孔；形成一介电层于该对通孔中且于第一金属层的顶面及底面上面；移除该介电层穿过该对通孔的部分；以及在形成嵌在该PCB衬底的上半部、下半部之间的该第一金属层之前，用一金属填满该对通孔，而形成该对金属填充通孔。又数个方面包括：通过用配线接合该半导体晶粒，使该半导体晶粒电气连接至该PCB衬底。其他数个方面包括：通过用数个凸块下金属(under-bumpmetallurgy，UBM)焊盘接合该半导体晶粒，使该半导体晶粒电气连接至该PCB衬底。又数个方面包括：该半导体晶粒用该UBM焊盘电气连接至该PCB衬底，该方法更包括：在连接该半导体晶粒之前，在该UBM焊盘与该PCB衬底的该上半部之间形成一金属层。另一方面包括：用以下方式形成该第二金属层于该半导体晶粒上面：在该第二金属层与该半导体晶粒之间形成有100μm至1,000μm的一间隙。其他数个方面包括：用以下方式形成该第二金属层于该半导体晶粒上面：形成该第二金属层于该半导体晶粒上。又数个方面包括：该半导体晶粒包括一MRAM结构。
本揭示内容的另一方面为一种装置，其包括：嵌在一PCB衬底的上半部、下半部之间的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔；在各通孔的侧壁上以及在该第一金属层的顶面及底面上面的一介电层；在该对金属填充通孔之间贴合至该PCB衬底的该上半部的一半导体晶粒；以及在该半导体晶粒的相对四侧上面及上的一第二金属层，该第二金属层通过该PCB衬底的该顶部座落于该第一金属层上。
该装置的数个方面包括：该第一及该第二金属层包括Ni-Fe合金。另一方面包括：该第一及该第二金属层有50μm至1000μm的厚度。其他方面包括：该第二金属层在该半导体晶粒上面有100μm至1,000μm。又一方面包括：该第二金属层在该半导体晶粒上。其他方面包括：该对金属填充通孔包括铜。更一方面包括：该半导体晶粒包括一MRAM结构。
本揭示内容的另一方面为一种方法，其包括：形成嵌在一PCB衬底的上半部、下半部之间厚度有50μm至1000μm的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔；将一MRAM结构在该对金属填充通孔之间贴合至该PCB衬底的该上半部；通过用数条配线或数个UBM焊盘接合该MRAM结构，使该MRAM结构通过该对金属填充通孔电气连接至该PCB衬底；将该PCB衬底的该上半部在该对金属填充通孔外的一部分向下移除到该第一金属层；以及在该MRAM结构的相对四侧上面及上形成厚度有50μm至1000μm的一第二金属层，该第二金属层座落于该第一金属层上。
本揭示内容的数个方面包括：形成由一Ni-Fe合金组成的该第一及该第二金属层。又一方面包括：在该第一金属层中形成侧向分离的一对通孔；形成一介电层于该对通孔中以及于第一金属层的顶面及底面上面；移除该介电层穿过该对通孔的部分；以及在形成该第一金属层之前，用一金属填充该对通孔，而形成该对金属填充通孔。
所属领域技术人员由以下详细说明可明白本揭示内容的其他方面及技术效果，其中仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。应了解，本揭示内容能够做出其他及不同的具体实施例，以及在各种明显的方面，能够修改数个细节而不脱离本揭示内容。因此，附图及说明内容本质上应被视为图解说明用而不是用来限定。
附图说明
在此用附图举例说明而不是限定本揭示内容，图中类似的组件用相同的组件符号表示。
图1及图2图标用以将MRAM结构磁屏蔽于打线接合式MRAM封装中的制程挑战；
图3至图5的横截面图根据一示范具体实施例示意图标用以将MRAM结构的六面磁屏蔽于薄打线接合封装中的加工流程；以及
图6至图8的横截面图根据一示范具体实施例示意图标用以将MRAM结构的六面磁屏蔽于薄覆晶封装中的加工流程。
具体实施方式
为了解释，在以下的说明中，提出许多特定细节供彻底了解示范具体实施例。不过，显然在没有该特定细节下或用等价配置仍可实施示范具体实施例。在其他情况下，众所周知的结构及装置用方块图图标以免不必要地混淆示范具体实施例。此外，除非另有说明，在本专利说明书及权利要求书中表示成分、反应条件等等的数量、比例及数值性质的所有数字应被理解为在所有情况下可用措辞“约”来修饰。
本揭示内容针对且解决在形成磁屏蔽封装结构于MRAM装置上面后伴随而来的高封装厚度及低效率的当前问题。尤其是，这个问题的解决是通过在MRAM结构的六面上形成金属屏蔽，而且底部金属屏蔽嵌在PCB衬底中，以及用穿过底部屏蔽金属的通孔电气连接于衬底。
根据本揭示内容的数个具体实施例的方法包括：形成嵌在一PCB衬底的上半部、下半部之间的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔。半导体晶粒在该对金属填充通孔之间贴合至PCB衬底的上半部，且半导体晶粒通过该对金属填充通孔而电气连接至PCB衬底。PCB衬底上半部在该对金属填充通孔外的一部分被移除向下到第一金属层，以及在该半导体晶粒的相对四侧上面及上形成一第二金属层，该第二金属层座落于该第一金属层上。
此外，所属领域技术人员由以下详细说明可明白本揭示内容的其他方面、特征及技术效果，其中仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。本揭示内容能够做出其他及不同的具体实施例，而且能够修改其在各种不同方面的数个细节。因此，附图及说明内容本质上应被视为图解说明用而不是用来限定。
图3至图5的横截面图根据一示范具体实施例示意图标用以将MRAM结构的所有六面磁屏蔽于薄打线接合封装中的加工流程。请参考图3，金属层301，例如，由Ni-Fe合金形成，例如，厚度有50μm至1000μm。然后，形成穿过金属层301的通孔303及305。接下来，通过首先于通孔303及305中以及于金属层301上面及下面形成介电层307，然后蚀刻介电层307穿过通孔303及305(为了图解说明而未图示)，沿着通孔303及305的侧壁且于金属层301上面及下面形成例如由聚合物组成的介电层307。然后，通孔303及305填满金属层309，例如，铜。接下来，有上半部311a及下半部311b的PCB衬底311各自形成于金属层301的顶面及底面上面，且使金属填充通孔303及305各自连接PCB衬底311的上半部及下半部。随后，图案化PCB衬底311a的上半部(用开口313表示)。
请参考图4，例如MRAM结构的半导体晶粒401在金属填充通孔303及305之间贴合至PCB衬底311的上半部311a。通过用连接至金属填充通孔303及305的配线403接合半导体晶粒401，使半导体晶粒401电气连接至PCB衬底311。随后，EMC层405形成于半导体晶粒401及配线403上面。如图5所示，PCB衬底311的上半部311a在该对金属填充通孔303及305外的部分被蚀刻向下到金属层301。接下来，在半导体晶粒401及EMC层405的相对四侧上面及上形成由例如Ni-Fe合金组成的金属层501，厚度有50μm至1000μm，例如，100μm至1,000μm，且坐落于金属层301上。
图6至图8的横截面图根据一示范具体实施例示意图标用以将MRAM结构的所有六面磁屏蔽于薄覆晶封装中的加工流程。第6图的初始装置与图3的装置相同且使用相同的制程步骤形成。请参考图7，金属层(为了图解说明而未图示)形成于PCB衬底311的上半部311a的数个部分上。然后，在PCB衬底311的上半部311a上的金属层上，形成UBM焊盘701。随后，形成底部填料(underfill)703于UBM焊盘701上面。接下来，使例如MRAM结构的半导体晶粒705与UBM焊盘701接合，然后使半导体晶粒705电气连接至PCB衬底311。如图8所示，将PCB衬底311的上半部311a在该对金属填充通孔303及305外的部分向下蚀刻到金属层301。然后，在半导体晶粒705的相对四侧上面及上形成例如由Ni-Fe合金组成的金属层801，厚度有50μm至1000μm，且座落于金属层301上。在此情形下，金属层801形成于半导体晶粒705上，不过，吾等预期，也可形成于上面例如有100μm至1,000微米。
本揭示内容的具体实施例可实现数种技术效果，例如相对于现有MRAM封装结构，有较高的屏蔽效率，较小的封装厚度及有较小开口的保护金属层。此外，有鉴于没有用于MRAM封装技术的已知覆晶解决方案，本发明方法提供一种适用于打线接合封装及覆晶封装两者的MRAM封装技术。此外，将金属层嵌在PCB衬底中可排除贴合底部金属层的制程，从而简化封装制程。根据本揭示内容的具体实施例所形成的装置可用于各种工业应用，例如，微处理器、智能型手机、移动电话、手机、机顶盒、DVD刻录机及播放器、汽车导航、列表机及接口设备，网络及电信设备，游戏系统及数字相机。本揭示内容在产业上可用于包括MRAM的任何各种半导体装置。
在以上说明中，特别用数个示范具体实施例描述本揭示内容。不过，显然仍可做出各种修改及改变而不脱离本揭示内容更宽广的精神及范畴，如权利要求书所述。因此，本专利说明书及附图应被视为图解说明用而非限定。应了解，本揭示内容能够使用各种其他组合及具体实施例且在如本文所述的本发明概念范畴内能够做出任何改变或修改。

Claims (20)

1.一种方法，包含：
形成嵌在一印刷电路板(PCB)衬底的上半部、下半部之间的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔；
将一半导体晶粒贴合至该PCB衬底在该对金属填充通孔之间的该上半部；
通过该对金属填充通孔使该半导体晶粒电气连接至该PCB衬底；
将该PCB衬底的该上半部在该对金属填充通孔外的一部分移除向下到该第一金属层；以及
形成一第二金属层于该半导体晶粒的相对四侧上面及上，该第二金属层座落于该第一金属层上。
2.如权利要求1所述的方法，包含：形成由一镍(Ni)-铁(Fe)合金组成的该第一及该第二金属层。
3.如权利要求1所述的方法，包含：形成厚度有50微米(μm)至1000μm的该第一及该第二金属层。
4.如权利要求1所述的方法，进一步包含：
在该第一金属层中形成侧向分离的一对通孔；
形成一介电层于该对通孔中且于该第一金属层的顶面及底面上面；
移除该介电层穿过该对通孔的部分；以及
在形成嵌在该PCB衬底的该上半部、该下半部之间的该第一金属层之前，用一金属填满该对通孔，而形成该对金属填充通孔。
5.如权利要求1所述的方法，包含用以下方式使该半导体晶粒电气连接至该PCB衬底：
用配线接合该半导体晶粒。
6.如权利要求1所述的方法，包含用以下方式使该半导体晶粒电气连接至该PCB衬底：
用数个凸块下金属(UBM)焊盘接合该半导体晶粒。
7.如权利要求6所述的方法，其中，该半导体晶粒用该UBM焊盘电气连接至该PCB衬底，该方法进一步包含：
在连接该半导体晶粒之前，在该UBM焊盘与该PCB衬底的该上半部之间形成一金属层。
8.如权利要求1所述的方法，包含用以下方式形成该第二金属层于该半导体晶粒上面：
在该第二金属层与该半导体晶粒之间形成有100μm至1,000μm的一间隙。
9.如权利要求1所述的方法，包含用以下方式形成该第二金属层于该半导体晶粒上面：
形成该第二金属层于该半导体晶粒上。
10.如权利要求1所述的方法，其中，该半导体晶粒包含一磁性随机存取内存(MRAM)结构。
11.一种装置，包含：
第一金属层，嵌在一印刷电路板(PCB)衬底的上半部、下半部之间，该第一金属层有侧向分离的一对金属填充通孔；
介电层，在各通孔的侧壁上且在该第一金属层的顶面及底面上面；
半导体晶粒，在该对金属填充通孔之间贴合至该PCB衬底的该上半部；以及
第二金属层，在该半导体晶粒的相对四侧上面及上，该第二金属层通过该PCB衬底的该顶部而座落于该第一金属层上。
12.如权利要求11所述的装置，其中，该第一及该第二金属层包含镍(Ni)-铁(Fe)合金。
13.如权利要求11所述的装置，其中，该第一及该第二金属层有50微米(μm)至1000μm的厚度。
14.如权利要求11所述的装置，其中，该第二金属层在该半导体晶粒上面有100μm至1,000μm。
15.如权利要求11所述的装置，其中，该第二金属层在该半导体晶粒上。
16.如权利要求11所述的装置，其中，该对金属填充通孔包含铜(Cu)。
17.如权利要求11所述的装置，其中，该半导体晶粒包含一磁性随机存取内存(MRAM)结构。
18.一种方法，包含：
形成嵌在一印刷电路板(PCB)衬底的上半部、下半部之间厚度有50微米(μm)至1000μm的一第一金属层，该第一金属层有侧向分离的一对金属填充通孔；
将一MRAM结构在该对金属填充通孔之间贴合至该PCB衬底的该上半部；
通过用数条配线或数个凸块下金属(UBM)焊盘接合该MRAM结构，使该MRAM结构通过该对金属填充通孔而电气连接至该PCB衬底；
将该PCB衬底的该上半部在该对金属填充通孔外的一部分向下移除到该第一金属层；以及
在该MRAM结构的相对四侧上面及上形成厚度有50μm至1000μm的一第二金属层，该第二金属层座落于该第一金属层上。
19.如权利要求18所述的方法，包含：形成由一镍(Ni)-铁(Fe)合金组成的该第一及该第二金属层。
20.如权利要求18所述的方法，进一步包含：
在该第一金属层中形成侧向分离的一对通孔；
形成一介电层于该对通孔中且于第一金属层的顶面及底面上面；
移除该介电层穿过该对通孔的部分；以及
在形成该第一金属层之前，用一金属填充该对通孔，而形成该对金属填充通孔。
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