CN108335987A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN108335987A
CN108335987A CN201710153204.2A CN201710153204A CN108335987A CN 108335987 A CN108335987 A CN 108335987A CN 201710153204 A CN201710153204 A CN 201710153204A CN 108335987 A CN108335987 A CN 108335987A
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semiconductor element
semiconductor
lateral projections
semiconductor packages
projection cube
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CN201710153204.2A
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CN108335987B (zh
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林柏均
朱金龙
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本申请公开一种半导体封装及其制造方法，其中半导体封装包含一半导体元件，该半导体元件具有一上表面与一侧，其中该上表面与该侧形成该半导体元件的一角部。该半导体封装亦包含一横向凸块结构位于该侧上并且实现该半导体元件的一横向信号路径。该半导体封装另包含一垂直凸块结构位于该上表面上并且实现该半导体元件的一垂直信号路径。

Description

半导体封装及其制造方法
技术领域
本公开涉及一种半导体封装及其制造方法，特别关于一种具有在两个横向相邻元件之间实现横向信号路径的横向凸块结构的半导体封装及其制造方法。
背景技术
半导体元件对于许多现代应用而言是重要的。随着电子技术的进展，半导体元件的尺寸越来越小，而功能越来越大且整合的电路量越来越多。由于半导体元件的尺度微小化，芯片上覆置芯片(chip-on-chip)技术目前广泛用于制造半导体元件。在此半导体封装的生产中，实施了许多制造步骤。
因此，微型化规模的半导体元件的制造变得越来越复杂。制造半导体元件的复杂度增加可能造成缺陷，例如电互连不良、产生裂纹、或是组件脱层。据此，半导体元件的结构与制造的修饰有许多挑战。
上文的”现有技术”说明仅是提供背景技术，并未承认上文的”现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的”现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的实施例提供一种半导体封装，包括具有一上表面与一侧的一半导体元件，其中该上表面与该侧形成该半导体元件的一角部；以及一横向凸块结构，位于该侧上且实现该半导体元件的一横向信号路径。
在本公开的一些实施例中，该半导体封装另包括一垂直凸块结构，位于该上表面上且实现该半导体元件的一垂直信号路径，其中该垂直凸块结构与该横向凸块结构分离。
在本公开的一些实施例中，该横向凸块结构自该侧横向延伸。
在本公开的一些实施例中，该垂直凸块结构自该上表面垂直延伸。
在本公开的一些实施例中，该半导体封装另包括一接垫，位于该侧与该横向凸块结构之间。
本公开的另一实施提供一种半导体封装，包括：一第一半导体元件，具有一第一上表面与一第一侧，其中该第一上表面与该第一侧形成该第一半导体元件的一第一角部；一第二半导体元件，横向相邻于该第一半导体元件，其中该第二半导体元件包括一第二上表面与一第二侧，并且该第二上表面与该第二侧形成该第二半导体元件的一第二角部；以及一横向凸块结构，自该第一侧延伸至该第二侧并且于该第一半导体元件与该第二半导体元件的间实现一横向信号路径。
在本公开的一些实施例中，该半导体封装另包括：一封装件，环绕该第一半导体元件与该第二半导体元件，其中该封装件的一中间部位于该第一半导体元件与该第二半导体元件之间；其中该横向凸块结构横向延伸跨过该中间部。
在本公开的一些实施例中，该半导体封装另包括位于该第一上表面上的一第一凸块结构，其中该第一垂直凸块结构与该横向凸块结构分离。
在本公开的一些实施例中，该半导体封装另包括位于该第二上表面上的一第二凸块结构，其中该第二垂直凸块结构与该横向凸块结构分离。
在本公开的一些实施例中，该横向凸块结构垂直延伸跨过该第一上表面与该第二上表面。
在本公开的一些实施例中，该半导体封装另包括一接垫，位于该第一侧与该横向凸块结构之间。
本公开的另一实施提供一种半导体封装的制造方法，包括：提供一半导体元件，具有一本体区以及与该本体区相邻的一边缘区；在该边缘区中形成一凹部，其中该凹部暴露该本体区的一侧；以及在该凹部中形成一横向凸块结构，其中该横向凸块结构形成于该侧上并且实现该半导体元件的一横向信号路径。
在本公开的一些实施例中，半导体封装的制造方法包括：在该半导体元件的一上表面上形成一遮罩，其中该遮罩具有暴露该边缘区的一部分的一开孔；以及进行一蚀刻制程，以移除该开孔暴露的该边缘区的一部分，形成该凹部。
在本公开的一些实施例中，半导体封装的制造方法包括：在该凹部中形成一凸块材料；移除该遮罩；以及进行一热制程以形成该横向凸块结构。
在本公开的一些实施例中，半导体封装的制造方法另包括在该热制程之前，进行一蚀刻制程以增加该凹部的一深度。
在本公开的一些实施例中，半导体封装的制造方法另包括在该热制程之后，自该半导体元件的一底表面进行一研磨制程，以移除该半导体元件的该边缘区。
在本公开的一些实施例中，半导体封装的制造方法包括在该半导体元件的一上表面上形成一遮罩，其中该遮罩具有一开口，暴露该本体区的一部分。
在本公开的一些实施例中，半导体封装的制造方法另包括：在该开口中形成一凸块材料；移除该遮罩；以及进行一热制程以于该本体区上形成一垂直凸块结构。
在本公开的一些实施例中，半导体封装的制造方法另包括在该半导体元件的一上表面上形成一垂直凸块结构，实现该半导体元件的一垂直信号路径。
在本公开的一些实施例中，半导体封装的制造方法是整合形成该垂直凸块结构与该横向凸块结构。
本公开的实施例提供一种具有一横向凸块结构的半导体封装，在未使用一重布线结构下，于两个横向相邻的半导体元件之间实现该横向信号路径。因此，本公开的半导体封装的高度小于具有一重布线结构的半导体封装的高度。换言之，本公开的半导体封装可符合半导体封装的尺度微小化需求(小尺寸架构)。此外，未使用重布线结构为半导体封装制造成本降低的主要因素。
该横向凸块结构自该半导体元件的该侧的横向延伸可接触一横向相邻元件的一对应导体；如此，在未使用对应于该重布线层的一重布线结构下，实现该半导体元件与该横向相邻元件之间的一横向信号路径。
上文已相当广泛地概述本公开的技术特征及优点，俾使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的构思构思和范围。
附图说明
参阅详细说明与权利要求结合考量附图时，可得以更全面了解本申请案的公开内容，附图中相同的元件符号是指相同的元件。
图1为剖面示意图，例示本公开的比较实施例的半导体封装。
图2为剖面示意图，例示本公开实施例的半导体封装。
图3为剖面示意图，例示本公开实施例的半导体封装。
图4为剖面示意图，例示本公开实施例的半导体封装。
图5为流程图，例示本公开实施例的半导体封装的制造方法。
图6至图10为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。
图11至图15为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。
图16至图21为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。
附图标记说明：
10 半导体封装
11 重布线层
11A 传导线
11B 传导线
11C 传导线
13A 半导体芯片
13B 半导体芯片
15 封装件
17 传导凸块
100A 半导体封装
100B 半导体封装
100D 半导体封装
101 半导体基板
103A 电互连
103B 电互连
103C 电互连
105A 传导接垫
105B 传导接垫
105C 传导接垫
107A 传导接垫
109 遮罩
110A 半导体元件
110B 半导体元件
110C 半导体元件
111 上表面
113 侧
113A 侧
113B 侧
114 角部
115 蚀刻剂
117 凸块材料
121A 横向凸块结构
121B 横向凸块结构
121C 横向凸块结构
121D 横向凸块结构
123A 垂直凸块结构
130A 第一半导体元件
130B 第二半导体元件
131A 垂直凸块结构
131B 垂直凸块结构
133A 侧
133B 侧
140 封装件
141 中间部
1032A 垂直传导接垫
1032B 垂直传导接垫
1032C 垂直传导接垫
1034A 传导插塞
1034B 传导插塞
1034C 传导插塞
1053A 凹部
1053B 凹部
1053C 凹部
1091 开孔
1093 开口
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、”实施例”、”例示实施例”、”其他实施例”、”另一实施例”等是指本公开所描述的的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用”在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
本公开涉及一种具有在两个横向相邻元件的间实现横向信号路径的横向凸块结构的半导体封装及其制造方法。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细的对其进行说明外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
图1为剖面示意图，例示本公开的比较实施例的半导体封装。半导体封装10包含重布线层11、位于重布线层11上的半导体芯片13A与半导体芯片13B、囊封重布线层11上的半导体芯片13A与半导体芯片13B的封装件15、以及位于重布线层11上的多个传导凸块17。在一些实施例中，所述传导凸块17位于重布线层11的上侧，而半导体芯片13A与半导体芯片13B位于重布线层11的下侧。
在一些实施例中，通过重布线层11中的传导线11A与所述传导凸块17的一实现半导体芯片13A的垂直信号路径，通过重布线层11中的传导线11B与所述传导凸块17的一实现半导体芯片13B的垂直信号路径，以及于未使用所述传导凸块17下，通过重布线层11中的传导线11C实现半导体芯片13A与半导体芯片13B的间的横向信号路径。
图2为剖面示意图，例示本公开实施例的半导体封装100A。在一些实施例中，半导体封装100A包括具有上表面111与一侧113的半导体元件110A、位于该侧113上的横向凸块结构121A、以及位于该上表面111上方的垂直凸块结构123A。在一些实施例中，该上表面111与该侧113形成半导体元件110A的角部114。在一些实施例中，第一侧113实质垂直于第一上表面111。
在一些实施例中，横向凸块结构121A沿着横向(附图中的X方向)自半导体元件110A的侧113横向延伸，并且实现半导体元件110A的横向信号路径。在一些实施例中，垂直凸块结构123A沿着垂直方向(附图中的Z方向)自半导体元件110A的上表面111垂直延伸，并且实现半导体元件110A的垂直信号路径。在一些实施例中，垂直凸块结构123A与横向凸块结构121A分离。
在一些实施例中，半导体封装100A包括半导体基板101与电互连103A；半导体基板101可为硅基板、绝缘体上覆半导体(semiconductor-on-insulator，SOI)基板、或包括半导体材料的任何架构；以及电互连103A包括介电材料与由例如Ti、Al、Ni、镍钒(NiV)、Cu或Cu合金所制成的传导组件。在一些实施例中，半导体封装100A包含集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、以及类似物，经配置以进行一或多个功能，其中为了清楚说明，本说明中未示出的该IC与半导体组件。
在一些实施例中，半导体封装100A的电互连103A包括横向传导接垫105A，以及横向凸块结构121A位于横向传导接垫105A上。在一些实施例中，半导体封装100A的电互连103A包括传导接垫107A，并且垂直凸块结构123A位于传导接垫107A上。在一些实施例中，横向传导接垫105A与传导接垫107A由铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)或其他导电材料制成。
在一些实施例中，横向凸块结构121A自半导体元件110A的该侧113A的横向延伸可接触横向相邻元件的对应导体，在未使用对应于图1所示的重布线层11的重布线结构下，实现半导体元件110A与横向相邻元件之间的横向信号路径。
图3为剖面示意图，例示本公开实施例的半导体封装100B。图3所示的半导体封装100B与图2所示的半导体封装100A实质相同，差别在于横向传导接垫与横向凸块结构的位置。在图2中，半导体元件110A的横向传导接垫105A包埋于侧113的左部上，而在图3中，半导体元件110B的传导接垫105B通过电互连103B的传导组件而实现且位于侧113的右部上。在一些实施例中，半导体元件110B的横向凸块结构121B垂直延伸跨过上表面111，如图3所示。
图4为剖面示意图，例示本公开实施例的半导体封装100D。在一些实施例中，半导体封装100D包括：第一半导体元件130A；横向相邻于第一半导体元件130A的第二半导体元件130B；囊封第一半导体元件130A与第二半导体元件130B的封装件140；以及在第一半导体元件130A与第二半导体元件130B之间实现横向信号路径的横向凸块结构121D。在一些实施例中，第一半导体元件130A与第二半导体元件130B可为图2所示的半导体元件110A或图3所示的半导体元件110B。
在一些实施例中，横向凸块结构121D自第一半导体元件130A的一侧133A横向延伸至第二半导体元件130B的一侧133B，并且该侧133A面对该侧133B。在一些实施例中，封装件140的中间部141位于第一半导体元件130A与第二半导体元件130B之间，以及横向凸块结构121D横向延伸跨过封装件140的中间部141。
在一些实施例中，第一半导体元件130A与第二半导体元件130B为单一晶圆的两个相邻芯片。在一些实施例中，第一半导体元件130A与第二半导体元件130B为不同晶圆的两个不同芯片。在一些实施例中，第一封装100D另包括实现第一半导体元件130A的垂直信号路径的垂直凸块结构131A，以及实现第二半导体元件130B的垂直信号路径的垂直凸块结构131B。
在一些实施例中，在未使用对应于图1所示的重布线层11的重布线结构下，横向凸块结构121D实现第一半导体元件130A与第二半导体元件130B之间的横向信号路径。因此，图4的半导体封装100D的高度小于图1的半导体封装10的高度。换言之，图4的半导体封装100D可符合半导体封装的尺度微小化需求(小尺寸架构)。此外，未使用对应于图1所示的重布线层11的重布线结构为图4的半导体封装100D制造成本降低的主要因素。
图5为流程图，例示本公开实施例的半导体封装的制造方法。在一些实施例中，可由图5的方法300制造半导体封装。方法300包含一些操作，并且描述与说明不被视为操作顺序的限制。方法300包含一些步骤(301、303与305)。
图6至图10为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。在步骤301中，提供半导体元件110A，如图6所示。在一些实施例中，半导体元件110A包括半导体基板101以及在半导体基板101上的电互连103A。
在一些实施例中，半导体元件110A具有本体区(bulk region)103以及与本体区103相邻的边缘区105，一些垂直传导接垫1032A形成于本体区103中且电连接至电互连103A的传导插塞1034A，以及横向传导接垫105A形成于与边缘区105相邻的本体区103中并且电连接至电互连103A。在一些实施例中，在本体区103中，形成集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、以及类似物。
在步骤303中，在半导体元件110A的边缘区105中，形成凹部1053A，如图7所示。凹部1053A的制造包含在半导体元件110A的上表面上形成遮罩109，其中遮罩109具有暴露边缘区105的一部分的开孔(aperture)1091，以及暴露本体区103的一部分的多个开口1093。而后，以蚀刻剂115进行蚀刻制程，例如干蚀刻，以移除开孔1091暴露的边缘区105的一部分，以形成凹部1053A。在一些实施例中，凹部1053A暴露横向传导接垫105A，以及所述开口1093暴露垂直传导接垫1032A。
在步骤305中，在凹部1053A中形成横向凸块结构121A，如图8至10所示。在图8中，凸块材料117形成于凹部1053A中及所述开口1093中的垂直传导接垫1032A上。在一些实施例中，凸块材料117包含无铅焊料，包含锡、铜与银、或”SAC”组合物，以及以及具有共同熔点且在电性应用中形成传导焊料连接的其他共熔物(eutectics)。
在图9中，例如，以蚀刻剂119通过蚀刻制程，移除遮罩109，以及移除边缘区105的一部分。而后，进行热处理制程，例如红外线(IR)回焊制程，以整合地(integrally)于半导体元件110A的侧113上形成横向凸块结构105A以及于半导体元件110A的垂直传导接垫1032A上形成垂直凸块结构123A。
在图10中，自半导体元件110A的底表面进行研磨制程以移除底部102，因而在热制程之后，完全移除半导体元件110A的边缘区105。因此，横向传导接垫105A上的横向凸块结构121A可接触相邻元件的接垫，并且实现半导体元件110A与相邻元件的横向信号路径，而垂直传导接垫1032A上的垂直凸块结构123A实现半导体元件110A的垂直信号路径。
图11至图15为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。在步骤301中，提供半导体元件110B，如图11所示。在一些实施例中，半导体元件110B包括半导体基板101以及在半导体基板101上的电互连103B。
在一些实施例中，半导体元件110B具有本体区103以及与本体区103相邻的边缘区105，并且一些垂直传导接垫1032B形成于本体区103中且电连接至电互连103B的传导插塞1034B；此外，通过与边缘区105相邻的本体区103中的电互连103B的传导组件，实现横向传导接垫105B。在一些实施例中，在本体区103中，形成集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、以及类似物。
在步骤303中，在半导体元件110B的边缘区105中，形成凹部1053B，如图12所示。凹部1053B的制造包含形成遮罩109于半导体元件110B的上表面111上，其中遮罩109具有暴露边缘区105的一部分的开孔1091以及暴露本体区103的一部分的多个开口1093。而后，以蚀刻剂115进行蚀刻制程，例如干蚀刻，以移除开孔1091暴露的边缘区105的一部分，形成凹部1053B。在一些实施例中，凹部1053B暴露横向传导接垫105B，以及所述开口1093暴露垂直传导接垫1032B。
在步骤305中，在凹部1053B中形成横向凸块结构121B，如图13至15所示。在图13中，凸块材料117形成于凹部1053B中与所述开口113中的垂直传导接垫1032B上。在一些实施例中，凸块材料117包含无铅焊料，包含锡、铜与银、或”SAC”组合物，以及以及具有共同熔点且在电性应用中形成传导焊料连接的其他共熔物(eutectics)。
在图14中，例如，以蚀刻剂119通过蚀刻制程，移除遮罩109，而后移除边缘区105的一部分。而后，进行热处理制程，例如红外线(IR)回焊制程，以整合地于半导体元件110B的侧113上形成横向凸块结构121B以及于半导体元件110B的垂直传导接垫1032B上形成垂直凸块结构123A。
在图15中，自半导体元件110B的底表面进行研磨制程以移除底部102，因而在热制程之后，完全移除半导体元件110B的边缘区105。因此，横向传导接垫105B上的横向凸块结构121B可接触相邻元件的接垫，并且实现半导体元件110B与相邻元件的横向信号路径，而垂直传导接垫1032B上的垂直凸块结构123A实现半导体元件110B的垂直信号路径。
图16至图20为示意图，例示本公开实施例通过图5的方法制造半导体封装的制程。在步骤301中，提供半导体元件110C，如图16所示。在一些实施例中，半导体元件110C包括半导体基板101以及在半导体基板101上的电互连103C。
在一些实施例中，半导体元件110C具有本体区103以及与本体区103相邻的边缘区105，并且一些垂直传导接垫1032C形成于本体区103中且电连接至电互连103C的传导插塞1034C；此外，横向传导接垫105C形成于与边缘区105相邻的本体区103中，并且电连接至电互连103C的传导插塞1034C。在一些实施例中，在本体区103中，形成集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、以及类似物。
在步骤303中，在半导体元件110C的边缘区105中，形成凹部1053C，如图17所示。凹部1053C的制造包含形成遮罩109于半导体元件110C的上表面111上，其中遮罩109具有暴露边缘区105的一部分的开孔1091以及暴露本体区103的一部分的多个开口1093。而后，以蚀刻剂115进行蚀刻制程，例如干蚀刻，以移除开孔1091暴露的边缘区105的一部分，形成凹部1053C。在一些实施例中，凹部1053C暴露横向传导接垫105C，以及所述开口1093暴露垂直传导接垫1032C。
在步骤305中，在凹部1053C中形成横向凸块结构121C，如图18至20所示。在图18中，凸块材料117形成于凹部1053C中与所述开口113中的垂直传导接垫1032C上。在一些实施例中，凸块材料117包含无铅焊料，包含锡、铜与银、或”SAC”组合物，以及以及具有共同熔点且在电性应用中形成传导焊料连接的其他共熔物(eutectics)。
在图19中，例如，以蚀刻剂119通过蚀刻制程，移除遮罩109，而后移除边缘区105的一部分。而后，进行热处理制程，例如红外线(IR)回焊制程，以整合地于半导体元件110C的侧113上形成横向凸块结构121C以及于半导体元件110C的垂直传导接垫1032C上形成垂直凸块结构123A。
在图20中，自半导体元件110C的底表面进行研磨制程以移除底部102，因而在热制程之后，完全移除半导体元件110C的边缘区105。因此，横向传导接垫105C上的横向凸块结构121C可接触相邻元件的接垫，并且实现半导体元件110C与相邻元件的横向信号路径，而垂直传导接垫1032C上的垂直凸块结构123A实现半导体元件110C的垂直信号路径。
参阅图21，在一些实施例中，完成图20所示的半导体元件110C之后，两个半导体元件110C横向配置且彼此相邻，而后形成封装件140以囊封该两个半导体元件110C。在其他的实施例中，两个半导体元件可为图15的半导体元件110B或是图10的半导体元件110A。而后，进行热处理制程，例如红外线(IR)回焊制程，形成横向凸块结构121D，在该两半导体元件110C之间实现横向信号路径。在一些实施例中，横向凸块结构121D横向延伸跨过封装件100的中间部141，在两个横向相邻的半导体元件110C之间实现横向信号路径。
在未使用对应于重布线层的重布线结构下，横向凸块结构自半导体元件的该侧的横向延伸可接触横向相邻元件的对应导体，以于该半导体元件与该横向相邻元件之间实现横向信号路径。
本公开的实施例提供一种具有横向凸块结构的半导体封装，在未使用重布线结构下，于两个相邻半导体元件之间实现横向信号路径。因此，本公开的半导体封装的高度小于具有重布线结构的半导体封装的高度。换言之，本公开的半导体封装可符合半导体封装的尺度微小化需求(小尺寸架构)。此外，未使用重布线结构为半导体封装制造成本降低的主要因素。
本公开的一实施例提供一种半导体封装，包含具有上表面与一侧的半导体元件，其中该上表面与该侧形成该半导体元件的角部。该半导体封装亦包含横向凸块结构，位于该侧上且实现该半导体元件的横向信号路径。该半导体封装另包含垂直凸块结构，位于该上表面上且实现该半导体元件的垂直信号路径。
本公开的另一实施例提供一种半导体封装，包含第一半导体元件、与该第一半导体元件横向相邻的第二半导体元件、以及自该第一侧延伸至该第二侧且于该第一半导体元件与该第二半导体元件之间实现横向信号路径的横向凸块结构。该第一半导体元件具有第一上表面与第一侧，其中该第一上表面与该第一侧形成该第一半导体元件的第一角部。该第二半导体元件具有第二上表面与第二侧，并且该第二上表面与该第二侧形成该第二半导体元件的第二角部。该半导体封装另包含位于该第一上表面上的第一垂直凸块结构以及位于该第二上表面上的第二垂直凸块结构。
本公开的另一实施例提供一种半导体封装的制造方法，包含：提供半导体元件，具有本体区以及与该本体区相邻的边缘区；在该边缘区中形成凹部，其中该凹部暴露该本体区的一侧；以及在该凹部中形成横向凸块结构，其中该横向凸块结构形成于该侧上并且实现该半导体元件的横向信号路径。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请案的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，这些制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请案的权利要求内。

Claims (20)

1.一种半导体封装，包括：
一半导体元件，具有一上表面与一侧，其中该上表面与该侧形成该半导体元件的一角部；以及
一横向凸块结构，位于该侧上并且实现该半导体元件的一横向信号路径。
2.如权利要求1所述的半导体封装，另包括一垂直凸块结构，位于该上表面上并且实现该半导体元件的一垂直信号路径，其中该垂直凸块结构与该横向凸块结构分离。
3.如权利要求1所述的半导体封装，其中该横向凸块结构自该侧横向延伸。
4.如权利要求1所述的半导体封装，其中该垂直凸块结构自该上表面垂直延伸。
5.如权利要求1所述的半导体封装，另包括一接垫，位于该侧与该横向凸块结构之间。
6.一种半导体封装，包括：
一第一半导体元件，具有一第一上表面与一第一侧，其中该第一上表面与该第一侧形成该第一半导体元件的一第一角部；
一第二半导体元件，横向相邻于该第一半导体元件，其中该第二半导体元件包括一第二上表面与一第二侧，并且该第二上表面与该第二侧形成该第二半导体元件的一第二角部；以及
一横向凸块结构，自该第一侧延伸至该第二侧并且于该第一半导体元件与该第二半导体元件之间实现一横向信号路径。
7.如权利要求6所述的半导体封装，另包括：
一封装件，环绕该第一半导体元件与该第二半导体元件，其中该封装件的一中间部位于该第一半导体元件与该第二半导体元件之间；
其中该横向凸块结构横向延伸跨过该中间部。
8.如权利要求6所述的半导体封装，另包括一第一垂直凸块结构，位于该第一上表面上，其中该第一垂直凸块结构与该横向凸块结构分离。
9.如权利要求6所述的半导体封装，另包括一第二垂直凸块结构，位于该第二上表面上，其中该第二垂直凸块结构与该横向凸块结构分离。
10.如权利要求6所述的半导体封装，其中该横向凸块结构垂直延伸跨过该第一上表面与该第二上表面。
11.如权利要求6所述的半导体封装，另包括一接垫，位于该第一侧与该横向凸块结构之间。
12.一种半导体封装的制造方法，包括：
提供一半导体元件，具有一本体区以及与该本体区相邻的一边缘区；
形成一凹部于该边缘区中，其中该凹部暴露该本体区的一侧；以及
形成一横向凸块结构于该凹部中，其中该横向凸块结构形成于该侧上并且实现该半导体元件的一横向信号路径。
13.如权利要求12所述的制造方法，包括：
形成一遮罩于该半导体元件的一上表面上，其中该遮罩具有一开孔，暴露该边缘区的一部分；以及
进行一蚀刻制程，以移除该开孔暴露的该边缘区的一部分，形成该凹部。
14.如权利要求13所述的制造方法，另包括：
形成一凸块材料于该凹部中；
移除该遮罩；以及
进行一热制程，以形成该横向凸块结构。
15.如权利要求14所述的制造方法，另包括：
在该热制程之前，进行一蚀刻制程，以增加该凹部的一深度。
16.如权利要求14所述的制造方法，另包括：
在该热制程之后，自该半导体元件的一底表面，进行一研磨制程，以移除该半导体元件的该边缘区。
17.如权利要求12所述的制造方法，另包括：
形成一遮罩于该半导体元件的一上表面上，其中该遮罩具有一开口，暴露该本体区的一部分。
18.如权利要求17所述的制造方法，另包括：
形成一凸块材料于该开口中；
移除该遮罩；以及
进行一热制程，以形成一垂直凸块结构于该本体区上。
19.如权利要求12所述的制造方法，另包括：
形成一垂直凸块结构于该半导体元件的一上表面上，其中该垂直凸块结构实现该半导体元件的一垂直信号路径。
20.如权利要求19所述的制造方法，其中该垂直凸块结构与该横向凸块结构是整合成形。
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