CN107342269A - 一种半导体封装方法及封装结构 - Google Patents
一种半导体封装方法及封装结构 Download PDFInfo
- Publication number
- CN107342269A CN107342269A CN201710531849.5A CN201710531849A CN107342269A CN 107342269 A CN107342269 A CN 107342269A CN 201710531849 A CN201710531849 A CN 201710531849A CN 107342269 A CN107342269 A CN 107342269A
- Authority
- CN
- China
- Prior art keywords
- slide glass
- chip
- connecting pole
- metal connecting
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 239000011521 glass Substances 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 67
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 238000012545 processing Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000012528 membrane Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明公开了一种半导体封装方法及封装结构,其中所述方法包括:在载片的第一表面上形成凹槽;凹槽的位置与芯片的焊盘位置相对应;在凹槽中设置金属连接柱;将芯片贴装在载片的第一表面上;对载片的第一表面进行封装,形成封装层;对载片的第二表面进行减薄至露出金属连接柱;在载片的第二表面加工第一绝缘层;在第一绝缘层上形成与金属连接柱连通的通孔;在载片的第二表面上加工线路层;线路层通过通孔与金属连接柱连接;在载片的第二表面加工第二绝缘层;在第二绝缘层上加工与线路层连通的开口,并在开口处设置焊球。本方法无需拆除载片或载片与芯片之间的胶膜以露出芯片的焊盘,载片不会形成翘曲,使得芯片封装结构可以做得较为轻薄。
Description
技术领域
本发明涉及半导体封装技术领域,具体涉及一种半导体封装方法及封装结构。
背景技术
随着半导体相关技术的发展,一方面芯片的功能越来越强大,引脚数量越来越多;另一方面为适应移动终端等设备小型化的需要,芯片的尺寸越来越小,使得芯片引脚间距便越来越小,不便于线路板布线。
扇出型封装工艺能够在芯片封装时根据需要增大与芯片引脚相连的焊点之间的间距,从而便于布线。现有的扇出型封装方法,先将芯片正面(即芯片上设置有焊盘的一面)朝下贴附于载板上,然后将芯片封装在封装层中,然后将板体进行180度翻转,拆除载板、载板与芯片间的胶膜以露出芯片正面的焊盘,进而在芯片正面设置连接焊盘的引线,在引线末端设置芯片封装结构的焊点。
然而,由于芯片贴附于载板上时焊盘朝向载板,因此为露出焊盘必须拆除载板与胶膜。为此,芯片封装结构必须做得足够厚(主要是封装层必须足够厚),否则载板拆除后的封装层容易形成较大的翘曲,导致后续的重布线工艺难以进行。
发明内容
有鉴于此,本发明实施例提供了一种半导体封装方法及封装结构,以制备轻薄化的扇出型半导体封装结构。
本发明第一方面提供了一种半导体封装方法,包括:在载片的第一表面上形成凹槽;所述凹槽的位置与芯片的焊盘位置相对应;在所述凹槽中设置金属连接柱;将芯片贴装在所述载片的第一表面上,所述金属连接柱与所述芯片的焊盘的连接;对载片的第一表面进行封装,形成覆盖所述芯片的封装层;对所述载片的第二表面进行减薄至露出所述金属连接柱;在所述载片的第二表面加工第一绝缘层;在所述第一绝缘层上形成与所述金属连接柱连通的通孔;在所述载片的第二表面上加工线路层;所述线路层通过所述通孔与所述金属连接柱连接;在所述载片的第二表面加工第二绝缘层;在所述第二绝缘层上加工与所述线路层连通的开口,并在所述开口处设置焊球。
可选地,所述线路层上与同一芯片连接的至少一条导线向背离所述芯片中心的方向延伸。
可选地,所述通孔的横截面积小于所述金属连接柱的横截面积。
可选地,所述在所述凹槽中形成金属连接柱的步骤包括:在所述载片第一表面形成金属层;对所述金属层进行刻蚀,在所述凹槽位置形成金属连接柱。
可选地,所述在将芯片贴装在所述载片的第一表面上的步骤之前,还包括:在所述金属连接柱的上表面设置焊料。
可选地,所述凹槽的深度为10μm至50μm,和/或所述凹槽的直径为50μm至100μm。
可选地,所述载片包括玻璃载片、亚克力板、树脂载片、陶瓷载片或单晶硅晶圆中的任意一者。
可选地,所述在所述开口处设置焊球的步骤之后,还包括:对板体进行切割,得到单个芯片的封装结构。
本发明第二方面提供了采用第一方面或者第一方面任意一种可选实施方式所制备的半导体封装结构。
本发明实施例所提供的半导体封装方法及封装结构,先在载片的第一表面形成凹槽,在凹槽中设置金属连接柱,再将芯片贴装在载片的第一表面,对载片的第一表面进行封装形成封装层,然后对载片的第二表面进行减薄至露出金属连接柱,在载片第二表面加工第一绝缘层并在第一绝缘层上形成与金属连接柱连通的通孔,在载片第二表面依次加工线路层、第二绝缘层,并在绝缘层上加工开口,在开口处设置焊球。由于在芯片是贴装于载片上的金属连接柱上,因此芯片的焊盘可以直接与金属连接柱连接,从而本方法无需拆除载片或载片与芯片之间的胶膜以露出芯片的焊盘,载片不会形成翘曲,使得芯片封装结构可以做得较为轻薄,还降低了工艺成本。
附图说明
通过参考附图会更加清楚的理解本发明的特征和优点,附图是示意性的而不应理解为对本发明进行任何限制,在附图中:
图1示出了在载片上形成凹槽的示意图;
图2示出了在凹槽中设置金属连接柱的示意图;
图3示出了在金属连接柱上设置焊料的示意图;
图4示出了贴装芯片的示意图;
图5示出了形成封装层的示意图;
图6示出了对载片的第二表面进行减薄的示意图;
图7示出了在载片第二表面加工第一绝缘层的示意图;
图8示出了在第一绝缘层上形成通孔的示意图;
图9示出了在载片第二表面加工线路层的示意图;
图10示出了在载片第二表面加工第二绝缘层的示意图;
图11示出了在第二绝缘层上加工开口的示意图;
图12示出了在第二绝缘层开口处设置焊球的示意图;
图13示出了切割后所的单个芯片的封装结构的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供了一种半导体封装方法适用于一般芯片的封装,还适用于晶圆级芯片的封装。晶圆级芯片是指对在单晶硅晶圆上制备集成电路形成多个芯片,对整片晶圆进行封装测试后,再切割所得到的单个产品芯片。
该半导体封装方法包括如下步骤:
S10:在载片的第一表面上形成凹槽。凹槽的位置与芯片的焊盘位置相对应。
如图1所示,1为载片。载片上凹槽的位置根据芯片的焊盘位置来确定。可选地,当所封装的芯片为晶圆级芯片时,凹槽的深度为10μm至50μm,凹槽的直径为50μm至100μm。
载片可以为玻璃载片、亚克力板、树脂载片、陶瓷载片或单晶硅晶圆(或者单晶硅载片)中的任意一者。
S20:在凹槽中设置金属连接柱。
如图2所示,在载片1中设置金属连接柱2。金属连接柱2的第一表面(即图2中所示的上表面)可以与载片1的第一表面齐平,也可以高于载片1的第一表面。
在凹槽1中设置金属连接柱2的方法可以为:先在载片1的第一表面形成金属层,然后对金属层进行刻蚀,留下凹槽1位置处的金属层,此时可以形成表面高于载片1第一表面的金属连接柱2。
对于晶圆级芯片进行封装时,由于芯片尺寸的数量级较小,在对金属层进行刻蚀时,为防止误差导致凹槽内的金属也被刻蚀掉,刻蚀所用掩膜在凹槽位置处的面积(或直径)大于凹槽的横截面积(或直径)。
S30:将芯片贴装在载片的第一表面上,金属连接柱与芯片的焊盘的连接。
如图4所示,4为芯片。芯片4靠近金属连接柱2的一面设置有焊盘,接芯片4贴装到载片1的第一表面上时,金属连接柱2与芯片的焊盘位置相对应并电连接。
金属连接柱2与芯片4的焊盘可以形成永久键合而连接。可选地,为使金属连接柱2与芯片4的焊盘连接更为紧密、电连接关系更可靠,可以先在金属连接柱2的上表面设置焊料3,再将芯片4贴装到金属连接柱2上。
S40:对载片的第一表面进行封装,形成覆盖芯片的封装层。
如图5所示,5为封装层。封装层5的第一表面高于芯片4的上表面。
S50:对载片的第二表面进行减薄至露出金属连接柱。
如图6所示,将载片1的厚度减薄至露出金属连接柱2。在实际执行这一步骤前,可以将步骤S40后所获得的载片翻转180度,从而便于减薄及后续处理操作。翻转后的上表面则为第二表面。
S60:在载片的第二表面加工第一绝缘层。
如图7所示,在载片1的第二表面加工第一绝缘层6。
S70:在第一绝缘层上形成与金属连接柱连通的通孔。
如图8所示。在第一绝缘层6上形成与金属连接柱2连通的通孔的方法可以是对第一绝缘层6进行刻蚀,去除金属连接柱2位置处的绝缘层,即可形成图8所示的通孔。
对于晶圆级芯片进行封装时,由于芯片尺寸的数量级较小,在对第一绝缘层进行刻蚀时,为防止误差导致通孔的位置与金属连接柱的位置错位,进而导致通孔与金属连接柱不连通,在对第一绝缘层进行刻蚀时,掩膜上第二连接柱位置处孔的面积大于金属连接柱的横截面积,由此可以使得通孔的横截面积小于金属连接柱的横截面积。
S80:在载片的第二表面上加工线路层。线路层通过通孔与金属连接柱连接,并且与同一芯片连接的至少一条导线向背离芯片中心的方向延伸。
如图9所示,7为线路层。线路层7上的线路与金属连接柱2连接。
可选地,线路层7上与同一芯片4连接的至少一条导线向背离该芯片4中心的方向延伸,如图9所示,从而可以使得所制备的半导体封装结构的引脚间距大于芯片自身的引脚间距,即实现扇出型封装。
S90:在载片的第二表面加工第二绝缘层。
如图10所示,8为第二绝缘层。
S100:在第二绝缘层上加工与线路层连通的开口,并在开口处设置焊球。
如图11所示,在第二绝缘层8上加工与线路层7连通的开口,可以是对第二绝缘层8进行刻蚀,去除线路层上部分导线上方的绝缘层。
如图12所示,9为焊球,且焊球9设置于开口处。
S110:对板体进行切割,得到单个芯片的封装结构。
该步骤之前,还可以先对板体第一表面进行减薄,即对封装层5进行减薄。在切割之前再减薄封装层,可以防止在以上步骤中板体过薄从而易弯曲导致加工工艺位置不准确,尤其是对于晶圆级芯片的封装。
图13示出了单个芯片的封装结构,其中,1为载片,2为金属连接柱,3为焊料,4为芯片,5为封装层,6为第一绝缘层,7为线路层,8为第二绝缘层,9为焊球。
需要补充说明的是,(1)本说明书附图中仅仅示出了芯片第一个引脚扇出封装的示意图,另一个引脚可以采用互不采用扇出封装(图中未示出另一引脚的封装情形);(2)本发明实施例仅给出了一层扇出(即线路层只有一层)的示意图,本方法也可以采用多层扇出(即设置多层线路层),两层线路层之间设置绝缘层。
上述半导体封装方法及封装结构,先在载片的第一表面形成凹槽,在凹槽中设置金属连接柱,再将芯片贴装在载片的第一表面,对载片的第一表面进行封装形成封装层,然后对载片的第二表面进行减薄至露出金属连接柱,在载片第二表面加工第一绝缘层并在第一绝缘层上形成与金属连接柱连通的通孔,在载片第二表面依次加工线路层、第二绝缘层,并在绝缘层上加工开口,在开口处设置焊球。由于在芯片是贴装于载片上的金属连接柱上,因此芯片的焊盘可以直接与金属连接柱连接,从而本方法无需拆除载片或载片与芯片之间的胶膜以露出芯片的焊盘,载片不会形成翘曲,使得芯片封装结构可以做得较为轻薄,还降低了工艺成本。
虽然结合附图描述了本发明的实施例,但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型,这样的修改和变型均落入由所附权利要求所限定的范围之内。
Claims (9)
1.一种半导体封装方法,其特征在于,包括:
在载片的第一表面上形成凹槽;所述凹槽的位置与芯片的焊盘位置相对应;
在所述凹槽中设置金属连接柱;
将芯片贴装在所述载片的第一表面上,所述金属连接柱与所述芯片的焊盘的连接;
对载片的第一表面进行封装,形成覆盖所述芯片的封装层;
对所述载片的第二表面进行减薄至露出所述金属连接柱;
在所述载片的第二表面加工第一绝缘层;
在所述第一绝缘层上形成与所述金属连接柱连通的通孔;
在所述载片的第二表面上加工线路层;所述线路层通过所述通孔与所述金属连接柱连接;
在所述载片的第二表面加工第二绝缘层;
在所述第二绝缘层上加工与所述线路层连通的开口,并在所述开口处设置焊球。
2.根据权利要求1所述的半导体封装方法,其特征在于,所述线路层上与同一芯片连接的至少一条导线向背离所述芯片中心的方向延伸。
3.根据权利要求1所述的半导体封装方法,其特征在于,所述通孔的横截面积小于所述金属连接柱的横截面积。
4.根据权利要求1所述的半导体封装方法,其特征在于,所述在所述凹槽中形成金属连接柱的步骤包括:
在所述载片第一表面形成金属层;
对所述金属层进行刻蚀,在所述凹槽位置形成金属连接柱。
5.根据权利要求1所述的半导体封装方法,其特征在于,所述在将芯片贴装在所述载片的第一表面上的步骤之前,还包括:在所述金属连接柱的上表面设置焊料。
6.根据权利要求1所述的半导体封装方法,其特征在于,所述凹槽的深度为10μm至50μm,和/或所述凹槽的直径为50μm至100μm。
7.根据权利要求1所述的半导体封装方法,其特征在于,所述载片包括玻璃载片、亚克力板、树脂载片、陶瓷载片或单晶硅晶圆中的任意一者。
8.根据权利要求1所述的半导体封装方法,其特征在于,所述在所述开口处设置焊球的步骤之后,还包括:对板体进行切割,得到单个芯片的封装结构。
9.一种采用权利要求1至8任一项所述的半导体封装方法所制备的半导体封装结构。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710531849.5A CN107342269A (zh) | 2017-06-30 | 2017-06-30 | 一种半导体封装方法及封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710531849.5A CN107342269A (zh) | 2017-06-30 | 2017-06-30 | 一种半导体封装方法及封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107342269A true CN107342269A (zh) | 2017-11-10 |
Family
ID=60219364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710531849.5A Pending CN107342269A (zh) | 2017-06-30 | 2017-06-30 | 一种半导体封装方法及封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107342269A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109332767A (zh) * | 2018-11-08 | 2019-02-15 | 四川九洲电器集团有限责任公司 | 分层式激光封焊拆除方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543927A (zh) * | 2010-12-14 | 2012-07-04 | 欣兴电子股份有限公司 | 嵌埋穿孔中介层的封装基板及其制造方法 |
CN202721116U (zh) * | 2012-06-11 | 2013-02-06 | 四川立泰电子有限公司 | 一种基于铝散热片的绝缘to220ab功率器件 |
US20150137384A1 (en) * | 2013-11-19 | 2015-05-21 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
-
2017
- 2017-06-30 CN CN201710531849.5A patent/CN107342269A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543927A (zh) * | 2010-12-14 | 2012-07-04 | 欣兴电子股份有限公司 | 嵌埋穿孔中介层的封装基板及其制造方法 |
CN202721116U (zh) * | 2012-06-11 | 2013-02-06 | 四川立泰电子有限公司 | 一种基于铝散热片的绝缘to220ab功率器件 |
US20150137384A1 (en) * | 2013-11-19 | 2015-05-21 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109332767A (zh) * | 2018-11-08 | 2019-02-15 | 四川九洲电器集团有限责任公司 | 分层式激光封焊拆除方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9318459B2 (en) | Through via package | |
US8669140B1 (en) | Method of forming stacked die package using redistributed chip packaging | |
US7723831B2 (en) | Semiconductor package having die with recess and discrete component embedded within the recess | |
US8053898B2 (en) | Connection for off-chip electrostatic discharge protection | |
KR100938970B1 (ko) | 반도체 장치 및 그 제조 방법 | |
WO2008063742A2 (en) | Method of packaging a semiconductor device and a prefabricated connector | |
JP3660918B2 (ja) | 半導体装置及びその製造方法 | |
TW201128755A (en) | Chip package | |
CN104617036A (zh) | 晶圆级芯片尺寸封装中通孔互连的制作方法 | |
KR20050037430A (ko) | 반도체 패키지 디바이스와 그의 형성 및 테스트 방법 | |
KR20190099731A (ko) | 보강용 탑 다이를 포함하는 반도체 패키지 제조 방법 | |
CN111128914A (zh) | 一种低翘曲的多芯片封装结构及其制造方法 | |
CN104495741A (zh) | 表面传感芯片封装结构及制作方法 | |
CN106601634A (zh) | 芯片封装工艺以及芯片封装结构 | |
US9935071B1 (en) | Semiconductor package with lateral bump structure | |
US7638862B2 (en) | Die attach paddle for mounting integrated circuit die | |
CN204508799U (zh) | 表面传感芯片封装结构 | |
CN107342269A (zh) | 一种半导体封装方法及封装结构 | |
US9373526B2 (en) | Chip package and method for forming the same | |
JP2000260933A (ja) | 半導体装置の製造方法 | |
CN209418490U (zh) | 一种扇出型封装结构 | |
CN106601635A (zh) | 芯片封装工艺以及芯片封装结构 | |
TWI559470B (zh) | 無基板的半導體封裝結構及其製造方法 | |
KR20080061987A (ko) | 스택 패키지 제조 방법 | |
US10074581B2 (en) | Chip package having a patterned conducting plate and a conducting pad with a recess |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171110 |