TWI545715B - 三維積體電路封裝體 - Google Patents
三維積體電路封裝體 Download PDFInfo
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- TWI545715B TWI545715B TW104124863A TW104124863A TWI545715B TW I545715 B TWI545715 B TW I545715B TW 104124863 A TW104124863 A TW 104124863A TW 104124863 A TW104124863 A TW 104124863A TW I545715 B TWI545715 B TW I545715B
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- 235000012431 wafers Nutrition 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 12
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- 239000000523 sample Substances 0.000 description 25
- 238000012360 testing method Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 239000010410 layer Substances 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
本發明係有關於一種封裝技術,特別是有關於一種三維積體電路封裝體及其製造方法。
三維積體電路(Three-Dimensional Integrated Circuits,3DICs)常用於消除二維(Two-Dimensional,2D)電路的障礙。三維積體電路內堆疊兩個或數個封裝部件,其中封裝部件包括中介層、封裝基板、印刷電路板(Printed Circuit Boards,PCBs)及類似的部件。在某些封裝部件(例如裝置晶片及/或中介層)內可形成矽通孔電極(Through-Silicon Vias,TSVs)。
三維積體電路因為各種問題可能造成製造良率的損失,例如用於接合兩封裝部件的連接器可能會破裂,也可能從對應的封裝部件脫層。當三維積體電路包括晶圓,晶圓內可能有更嚴重的翹曲,且可能造成製造過程的困難。
本發明係提供一種三維積體電路封裝的製造方法,包括一第一封裝部件接合第二封裝部件的第一表面上,從第二封裝部件的第二表面探針測試第一封裝部件及第二封裝
部件,其中透過探針穿透第二封裝部件的第二表面上的複數連接器進行探針測試的步驟,且其中連接器連接至第一封裝部件;以及在探針測試的步驟後,在第二封裝部件的第一表面上接合第三封裝部件。
本發明係提供另一種三維積體電路封裝的製造方法,包括在中介晶圓的第一表面上接合第一複數晶片,以形成複數封裝體,其中中介晶圓包括複數中介層,且其中每一封裝體包括接合中介層之其中一者的第一複數晶片之其中一者;從中介晶圓的第二表面探針測試封裝體,以辨識複數良好的封裝體及複數瑕疵的封裝體,其中探針測試的步驟是對中介晶圓的第二表面上的複數連接器進行全面性探針測試,且其中連接器連接至第一複數晶片;在探針測試的步驟後,進行晶片切割製程,以彼此分離封裝體;以及在良好的封裝體上接合第二複數晶片,其中瑕疵的封裝體不接合任何的第二複數晶片。
本發明係提供一種三維積體電路封裝體,包括一第一封裝部件;一第二封裝部件,接合第一封裝部件的第一表面;一第一底膠區,位於第一封裝部件及第二封裝部件之間;一第三封裝部件,接合第一封裝部件的第一表面;以及一第二底膠區,位於第一封裝部件及第三封裝部件之間,其中第一底膠區及第二底膠區互相連接以形成連續的底膠區,且在第一底膠區及第二底膠區之間形成一可視的界面。
10‧‧‧基板
10B‧‧‧基板背表面
12‧‧‧前側內連結構
16‧‧‧重佈線
18‧‧‧介電層
20‧‧‧基板通孔電極
22‧‧‧中介層
24、24A、24B、38‧‧‧連接器
26、56‧‧‧晶片/封裝部件
26A‧‧‧晶片上表面
27、53、57‧‧‧底膠區
30、32‧‧‧薄膜
30A‧‧‧薄膜上表面
33、59‧‧‧載板
36‧‧‧背側內連結構
40‧‧‧箭頭
42‧‧‧封裝體
43‧‧‧切割線
52、100‧‧‧封裝部件
58‧‧‧界面
60‧‧‧黏膠
100A‧‧‧前表面
100B‧‧‧背表面
T1‧‧‧薄膜厚度
第1至9圖係繪示出本發明實施例之三維積體電路封裝體
製造階段的剖面示意圖。
第10至17圖係繪示出本發明另一實施例之三維積體電路封裝體製造階段的剖面示意圖。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。
以下提供一種新穎的三維積體電路封裝及其製造方法,並以一實施例說明製造階段及討論各種實施例。圖式及說明中使用相同的標號來表示相同或相似的部件。
請參照第1圖,提供一封裝部件100,其包括基板10。在某些實施例中,封裝部件100是中介晶圓,包括複數中介層22。封裝部件100大致上可沒有積體電路裝置,包括主動裝置(例如電晶體)。再者,封裝部件100可包括或可不包括被動裝置(例如電容、電阻、電感、變容二極體及/或類似的元件)。另外,封裝部件100可為包括主動裝置(例如電晶體)於其中的裝置晶圓。
基板10可由一半導體材料所組成,例如矽。另外,基板10可由一介電材料所組成。在基板10的前側形成前側內連結構12,其包括一或數個介電層18及介電層內的金屬線及介層連接窗(via)16。以下敘述中,第1圖中封裝部件100朝上的一側稱為前側及表面100A稱為前表面100A,封裝部件100朝下的一側稱為背側及表面100B稱為背表面100B。金屬線及介層連接窗
16另稱為前側重佈線(redistribution lines,RDLs)。再者,在基板10內形成基板通孔電極(through-substrate vias,TSVS)20且延伸至一既定深度。基板通孔電極20電性連接前側重佈線16。
在封裝部件100的前表面100A形成前側連接器24,且透過重佈線16電性連接基板通孔電極20。在某些實施例中,連接器24包括焊球。在另一實施例中,連接器24包括金屬接墊、金屬柱、具有覆蓋焊料蓋層的金屬柱或類似的部件。
請參照第2圖,封裝部件26接合於封裝部件100的前側,且接合於連接器24A(其為部分的連接器24)。在某些實施例中,封裝部件26為晶片,而以下稱為晶片26,不過也可為其他類型。晶片26可為包括積體電路裝置(例如電晶體、電容、電感、電阻(未繪示)及類似的元件)的裝置晶片。另外,晶片26可為包括裝置晶片及其他封裝部件(例如中介層、封裝基板及類似的元件)於其中的封裝體。晶片26及連接器24A之間的接合可為焊料接合或直接金屬對金屬(例如銅對銅)接合。複數底膠區27充填入晶片26與封裝部件100之間的間隙並固化,且彼此間可互相分離。
連接器24也包括連接器24B,其中連接器24A及連接器24B可具有相同結構,例如相同尺寸、相同分層及相同材料。無封裝部件接合於連接器24B,因此暴露出連接器24B且不被底膠區覆蓋。
請參照第3圖,在晶片26及封裝部件100塗佈薄膜30,薄膜30的上表面可高於或切齊於晶片26的上表面26A。薄膜30更填充入晶片26之間的間隙。薄膜30可包括一高分子,其
於後續去除後不會破壞連接器24B、晶片26及封裝材料100。在某些實施例中,透過旋轉塗佈製程塗佈薄膜30。另外,薄膜30為疊層。薄膜30的厚度T1可大於20微米且可大約在20微米至800微米的範圍。薄膜30的上表面30A大致上可為平面。
請參照第4圖,透過薄膜32在載板33上裝設封裝部件100,薄膜32也可包括一高分子。在某些實施例中,薄膜32可為紫外線(Ultra-Violet,UV)膠,或由其他高分子材料所組成。薄膜32可由能蝕刻去除的材料所組成。載板33可為玻璃載板,不過也可以使用其他類型的載板。
請參照第5圖,從封裝部件100的背側進行晶圓背側研磨製程,使基板10變薄直到暴露出基板通孔電極20。可進行蝕刻製程以進一步減少基板10的表面,使基板通孔電極20突出基板10剩餘部份的背表面10B。接著,形成背側內連結構36以連接基板通孔電極20(繪示於第6圖)。在不同實施例中,背側內連結構36可具有與前側內連結構12相似的結構,且可包括一或數層重佈線(未繪示)。之後形成連接器38且電性耦接背側內連結構36。透過背側內連結構36及基板通孔電極20,連接器38可電性耦接晶片26及連接器24。連接器38可為含焊料的連接器,也可包括焊球、具有焊料蓋層的金屬柱、金屬柱、金屬接墊或其他類型的金屬凸塊(由金、銀、鎳、鎢、鋁及/或其合金所形成)。以下敘述中,結合封裝部件100內的中介層22(未標記於第6圖,請參照第1圖)及對應的晶片26稱為封裝體42。因此,形成複數封裝體42(繪示於第6圖)。
第6圖亦繪示出透過連接器38對封裝部件100及晶
片26的探針測試,其中箭頭40表示探針測試使用的探針針頭。可以理解的是接合封裝部件100的晶片26可為已知良好的晶片。然而,可能產生額外的瑕疵,例如產生於晶片26及連接器38之間的電性路徑內。此外,在接合過程中晶片26也可能損壞。某些封裝體42可能通過探針測試且標記為良好的封裝體,而某些其他的封裝體42可能未通過探針測試,也因此標記為瑕疵的封裝體。因此,透過探針測試可辨識良好的封裝體42及瑕疵的封裝體42。
之後剝除載板33,例如透過紫外線照射薄膜32使其失去黏性。第7圖係繪示出得到的結構。可透過蝕刻製程去除薄膜32,也去除薄膜30。在某些實施例中,薄膜32可剝除,如此可暴露出連接器24B。切割膠帶44黏附連接器38位於封裝部件100的相同側面,且用以剝除載板33。接著,沿切割線43進行切割以使封裝體42彼此分離。得到的每一個封裝體42包括一中介層22及一或數個晶片26。
請參照第8圖,得到的良好封裝體42可透過連接器38接合另一封裝部件52(例如封裝基板)。之後在封裝體42及封裝部件52之間可塗佈底膠區53。
請重新參照第6圖,探針測試的步驟中,辨識出瑕疵的封裝體42並丟棄。因此,無瑕疵的封裝體42接合至封裝部件52。可以理解的是瑕疵的封裝體42是在封裝完成前的初期階段中檢測出,如此可防止後續的封裝部件(例如封裝基板、晶片等)接合於瑕疵的封裝體,因此消除了因為瑕疵的封裝體造成進一步的良率損失。
第9圖係繪示出在良好的封裝體42上接合封裝部件56,其可為裝置晶片,且因此以下另稱為晶片56,不過可為其他類型的封裝部件(例如一封裝體)。晶片56接合連接器24B。接合之後,晶片56可電性耦接基板通孔電極20及連接器38。在某些實施例中,晶片26及晶片56是相同類型,且具有相同結構。在另一實施例中,晶片26及晶片56是不同類型,且具有不同結構。之後充填底膠區57並固化。當晶片26及晶片56互相靠近,底膠區57及底膠區27可互相連接以形成連續的底膠區。可以理解的是底膠區57及底膠區27在不同時間點充填,因此,不論底膠區57及底膠區27由相同材料所組成或包括不同材料,當底膠區57及底膠區27互相接觸,底膠區57及底膠區27之間可形成可視的界面58。另外,底膠區57及底膠區27可互相不連接。
第10至15圖係繪示出另一實施例之封裝體製造階段的剖面示意圖,除非特別標明,否則這些實施例的標號表示與第1至9圖相同或相似的部件。例如,對應的詳細說明可參照第1至9圖的實施例,不論形成方法及元件材料不再重述。請參照第10圖,提供一封裝部件100,且可透過黏膠60(在一實施例中其可為紫外線膠)貼附於載板59。也可預先形成背側內連結構36及連接器38,且可透過基板通孔電極20及重佈線16電性耦接連接器24。載板59可為玻璃載板。
接著,如第11圖所示,在封裝部件100前側的連接器24A接合晶片26,之後充填底膠區27並固化。充填底膠區27後,可暴露出維持未接合任何封裝部件的連接器24B。第12圖
中,塗佈薄膜30以覆蓋晶片26及封裝部件100,其也可接觸連接器24B。
請參照第13圖,在薄膜30上塗佈薄膜32,且透過薄膜32在載板33上裝設封裝部件100。薄膜32可包括一高分子,之後剝除載板59及去除黏膠60。因此,暴露出連接器38。接著,第14圖係繪示出進行晶片探針測試的步驟(如箭頭40所標示)以檢測瑕疵的封裝體42,每一封裝體42包括中介層22的其中之一者及晶片26的其中之一者。透過晶片探針測試的步驟,可辨識且標示出良好的封裝體42及瑕疵的封裝體42。
之後剝除載板33,也去除薄膜30及薄膜32,例如,分別透過蝕刻製程及剝除的步驟。第15圖係繪示出得到的結構,此階段中暴露出連接器24B且未接合任何封裝部件。切割膠帶44黏附連接器38位於封裝部件100的相同側面,且用以剝除載板33。接著,沿切割線43進行切割以使封裝體42彼此分離。得到的每一個封裝體42包括中介層22的其中之一者及晶片26的其中之一者。第16圖係繪示出良好的封裝體42可透過連接器38接合另一封裝部件52(例如封裝基板),且丟棄瑕疵的封裝體42。之後在封裝體42及封裝部件52之間可塗佈底膠區53。
請參照第17圖,封裝部件56接合連接器24B,其可為裝置晶片、封裝體或類似的部件。之後充填底膠區57並固化。可以理解的是底膠區57及底膠區27在不同時間點充填,因此,不論底膠區57及底膠區27是否由相同材料所組成或包括不同材料,當底膠區57及底膠區27互相接觸,底膠區57及底膠區27之間可形成可視的界面58。
本發明實施例中,待接合於封裝部件100同一側的裝置晶片區分為第一組及第二組,第一組裝置晶片先接合於封裝部件100以形成封裝體。進行晶片探針測試的步驟,以從包括第一組裝置晶片的封裝體中檢測出良好的封裝體及瑕疵的封裝體。第二組裝置晶片接合於良好的封裝體,而瑕疵的封裝體則不再進行封裝。因此,可省下其他因接合於瑕疵的封裝體而浪費掉的裝置晶片及封裝基板。
配合本發明實施例之一種三維積體電路封裝的製造方法,包括第一封裝部件接合第二封裝部件的第一表面上,從第二封裝部件的第二表面探針測試第一封裝部件及第二封裝部件,其中透過探針穿透第二封裝部件的第二表面上的複數連接器進行探針測試的步驟,且連接器連接至第一封裝部件。探針測試的步驟後,在第二封裝部件的第一表面上接合第三封裝部件。
配合本發明另一實施例之一種三維積體電路封裝的製造方法,包括在中介晶圓的第一表面上接合第一複數晶片,以形成複數封裝體,其中中介晶圓包括複數中介層,且其中每一封裝體包括接合中介層之其中一者的第一複數晶片之其中一者。從中介晶圓的第二表面探針測試封裝體,以辨識複數良好的封裝體及複數瑕疵的封裝體,其中探針測試的步驟是對中介晶圓的第二表面上的複數連接器進行全面性探針測試,且其中連接器連接至第一複數晶片。在探針測試的步驟後,進行晶片切割製程,以彼此分離封裝體,以及在良好的封裝體上接合第二複數晶片,其中瑕疵的封裝體不接合任何的第
二複數晶片。
配合本發明其他實施例之一種三維積體電路封裝,包括一第一封裝部件;一第二封裝部件,接合第一封裝部件的第一表面;一第一底膠區,位於第一封裝部件及第二封裝部件之間;一第三封裝部件,接合第一封裝部件的第一表面;以及一第二底膠區,位於第一封裝部件及第三封裝部件之間,其中第一底膠區及第二底膠區互相連接以形成連續的底膠區,且在第一底膠區及第二底膠區之間形成一可視的界面。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
22‧‧‧中介層
24、24A、24B、38‧‧‧連接器
26、56‧‧‧晶片/封裝部件
27、57‧‧‧底膠區
42‧‧‧封裝體
52‧‧‧封裝部件
53‧‧‧底膠區
58‧‧‧界面
Claims (9)
- 一種三維積體電路封裝體,包括:一第一封裝部件;一第二封裝部件,接合該第一封裝部件的一第一表面;一第一底膠區,位於該第一封裝部件及該第二封裝部件之間;一第三封裝部件,接合該第一封裝部件的該第一表面;以及一第二底膠區,位於該第一封裝部件及該第三封裝部件之間,其中該第一底膠區及該第二底膠區互相連接以形成連續的底膠區,且其中在該第一底膠區及該第二底膠區之間形成一可視的界面,且該第二底膠區覆蓋一部分的該第一底膠區。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該第一封裝部件包括一中介層,且其中該第二封裝部件及該第三封裝部件包括接合該中介層的複數裝置晶片。
- 如申請專利範圍第2項所述之三維積體電路封裝體,更包括一封裝基板,接合該第一封裝部件的一第二表面,其中該封裝基板位於該中介層中相對該第二封裝部件及該第三封裝部件的一側。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中一部分的該第一底膠區延伸至該第二底膠區與該第一封裝部件之間。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該 可視的界面傾斜於該第一封裝部件的該第一表面。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該第一底膠區未延伸至該第二封裝部件的一側壁上。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該第二底膠區未延伸至該第三封裝部件的一側壁上。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該第一底膠區及該第二底膠區包括相同的材料。
- 如申請專利範圍第1項所述之三維積體電路封裝體,其中該第一底膠區及該第二底膠區包括不同的材料。
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Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US8936966B2 (en) * | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR102077153B1 (ko) * | 2013-06-21 | 2020-02-14 | 삼성전자주식회사 | 관통전극을 갖는 반도체 패키지 및 그 제조방법 |
US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
CN105448873A (zh) * | 2014-08-29 | 2016-03-30 | 展讯通信(上海)有限公司 | 一种集成优化的芯片结构 |
TWI566305B (zh) * | 2014-10-29 | 2017-01-11 | 巨擘科技股份有限公司 | 製造三維積體電路的方法 |
DE102015008503A1 (de) * | 2015-07-03 | 2017-01-05 | TE Connectivity Sensors Germany GmbH | Elektrisches Bauteil und Herstellungsverfahren zum Herstellen eines solchen elektrischen Bauteils |
US10373893B2 (en) | 2017-06-30 | 2019-08-06 | Intel Corporation | Embedded bridge with through-silicon vias |
US11075133B2 (en) | 2018-06-29 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill structure for semiconductor packages and methods of forming the same |
CN110660752A (zh) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | 半导体装置封装体及其制造方法 |
CN111377391B (zh) * | 2018-12-27 | 2023-08-25 | 中芯集成电路(宁波)有限公司上海分公司 | Mems封装结构及其制作方法 |
CN111377394B (zh) * | 2018-12-27 | 2023-08-25 | 中芯集成电路(宁波)有限公司上海分公司 | Mems封装结构及其制作方法 |
CN111377392B (zh) * | 2018-12-27 | 2023-08-25 | 中芯集成电路(宁波)有限公司上海分公司 | Mems封装结构及其制作方法 |
US11990448B2 (en) | 2020-09-18 | 2024-05-21 | Intel Corporation | Direct bonding in microelectronic assemblies |
US11837586B2 (en) * | 2021-02-26 | 2023-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming thereof |
US20220367413A1 (en) * | 2021-05-13 | 2022-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packages With Multiple Types of Underfill and Method Forming The Same |
US11978729B2 (en) * | 2021-07-08 | 2024-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device package having warpage control and method of forming the same |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4811082A (en) | 1986-11-12 | 1989-03-07 | International Business Machines Corporation | High performance integrated circuit packaging structure |
US4990462A (en) | 1989-04-12 | 1991-02-05 | Advanced Micro Devices, Inc. | Method for coplanar integration of semiconductor ic devices |
US5075253A (en) | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US5380681A (en) | 1994-03-21 | 1995-01-10 | United Microelectronics Corporation | Three-dimensional multichip package and methods of fabricating |
US6002177A (en) | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US6213376B1 (en) | 1998-06-17 | 2001-04-10 | International Business Machines Corp. | Stacked chip process carrier |
US6281042B1 (en) | 1998-08-31 | 2001-08-28 | Micron Technology, Inc. | Structure and method for a high performance electronic packaging assembly |
US6271059B1 (en) | 1999-01-04 | 2001-08-07 | International Business Machines Corporation | Chip interconnection structure using stub terminals |
US6461895B1 (en) | 1999-01-05 | 2002-10-08 | Intel Corporation | Process for making active interposer for high performance packaging applications |
US6229216B1 (en) | 1999-01-11 | 2001-05-08 | Intel Corporation | Silicon interposer and multi-chip-module (MCM) with through substrate vias |
JP2000357768A (ja) * | 1999-06-17 | 2000-12-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6243272B1 (en) | 1999-06-18 | 2001-06-05 | Intel Corporation | Method and apparatus for interconnecting multiple devices on a circuit board |
US6537482B1 (en) * | 2000-08-08 | 2003-03-25 | Micron Technology, Inc. | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography |
US6355501B1 (en) | 2000-09-21 | 2002-03-12 | International Business Machines Corporation | Three-dimensional chip stacking assembly |
KR100364635B1 (ko) | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
KR100394808B1 (ko) * | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
KR100435813B1 (ko) | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
US6590409B1 (en) * | 2001-12-13 | 2003-07-08 | Lsi Logic Corporation | Systems and methods for package defect detection |
DE10200399B4 (de) | 2002-01-08 | 2008-03-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung |
US6661085B2 (en) | 2002-02-06 | 2003-12-09 | Intel Corporation | Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack |
US6975016B2 (en) | 2002-02-06 | 2005-12-13 | Intel Corporation | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof |
US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
JP3910493B2 (ja) * | 2002-06-14 | 2007-04-25 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US6600222B1 (en) | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
US6790748B2 (en) | 2002-12-19 | 2004-09-14 | Intel Corporation | Thinning techniques for wafer-to-wafer vertical stacks |
US6908565B2 (en) | 2002-12-24 | 2005-06-21 | Intel Corporation | Etch thinning techniques for wafer-to-wafer vertical stacks |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US6946384B2 (en) | 2003-06-06 | 2005-09-20 | Intel Corporation | Stacked device underfill and a method of fabrication |
US7320928B2 (en) | 2003-06-20 | 2008-01-22 | Intel Corporation | Method of forming a stacked device filler |
KR100537892B1 (ko) | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | 칩 스택 패키지와 그 제조 방법 |
US7345350B2 (en) | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
KR100621992B1 (ko) | 2003-11-19 | 2006-09-13 | 삼성전자주식회사 | 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지 |
KR100570514B1 (ko) | 2004-06-18 | 2006-04-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스택 패키지 제조 방법 |
KR100618837B1 (ko) | 2004-06-22 | 2006-09-01 | 삼성전자주식회사 | 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법 |
US7307005B2 (en) | 2004-06-30 | 2007-12-11 | Intel Corporation | Wafer bonding with highly compliant plate having filler material enclosed hollow core |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7087538B2 (en) | 2004-08-16 | 2006-08-08 | Intel Corporation | Method to fill the gap between coupled wafers |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
US7557597B2 (en) | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US7402515B2 (en) | 2005-06-28 | 2008-07-22 | Intel Corporation | Method of forming through-silicon vias with stress buffer collars and resulting devices |
US7432592B2 (en) | 2005-10-13 | 2008-10-07 | Intel Corporation | Integrated micro-channels for 3D through silicon architectures |
US7528494B2 (en) | 2005-11-03 | 2009-05-05 | International Business Machines Corporation | Accessible chip stack and process of manufacturing thereof |
US7410884B2 (en) | 2005-11-21 | 2008-08-12 | Intel Corporation | 3D integrated circuits using thick metal for backside connections and offset bumps |
US7402442B2 (en) | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
US7279795B2 (en) | 2005-12-29 | 2007-10-09 | Intel Corporation | Stacked die semiconductor package |
US7576435B2 (en) | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
KR101213175B1 (ko) | 2007-08-20 | 2012-12-18 | 삼성전자주식회사 | 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지 |
US9136144B2 (en) * | 2009-11-13 | 2015-09-15 | Stats Chippac, Ltd. | Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation |
US10297550B2 (en) | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8581418B2 (en) | 2010-07-21 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die stacking using bumps with different sizes |
US8691626B2 (en) | 2010-09-09 | 2014-04-08 | Advanced Micro Devices, Inc. | Semiconductor chip device with underfill |
-
2012
- 2012-03-23 US US13/429,054 patent/US9006004B2/en active Active
- 2012-07-12 CN CN201210241811.1A patent/CN103325703B/zh active Active
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- 2013-03-13 TW TW102108789A patent/TWI505432B/zh active
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- 2015-04-13 US US14/685,167 patent/US9583461B2/en active Active
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US20150214190A1 (en) | 2015-07-30 |
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