US20040119158A1 - Thermally enhanced package for an integrated circuit - Google Patents

Thermally enhanced package for an integrated circuit Download PDF

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Publication number
US20040119158A1
US20040119158A1 US10/327,465 US32746502A US2004119158A1 US 20040119158 A1 US20040119158 A1 US 20040119158A1 US 32746502 A US32746502 A US 32746502A US 2004119158 A1 US2004119158 A1 US 2004119158A1
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Prior art keywords
heat
conducting
die
plate
chip
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US10/327,465
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Koay Tatt
Tan Ghee
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Avago Technologies International Sales Pte Ltd
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Agilent Technologies Inc
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Priority to US10/327,465 priority Critical patent/US20040119158A1/en
Assigned to AGILENT TECHNOLOGIES INC. reassignment AGILENT TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GHEE, TAN GIN, TATT, KOAY HEAN
Priority to PCT/US2003/039922 priority patent/WO2004062333A1/en
Priority to CNA2003801000441A priority patent/CN1685777A/en
Priority to JP2003419002A priority patent/JP2004200694A/en
Publication of US20040119158A1 publication Critical patent/US20040119158A1/en
Priority to US11/345,104 priority patent/US7312525B2/en
Assigned to AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AGILENT TECHNOLOGIES, INC.
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: AGILENT TECHNOLOGIES, INC.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to packages for integrated circuits and the like.
  • Semiconductor chips are typically sealed in a package that is soldered to a printed circuit board.
  • the various connections between the electrical components on the chip and the conductors on the printed circuit board are made through conductors that pass through the package and are connected to the printed circuit board by solder.
  • the chip is encapsulated in a potting compound that protects the chip from damage caused by exposure to moisture and oxygen.
  • the present invention is a circuit assembly having an insulating base, heat-conducting plate and circuit-containing die.
  • the die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base.
  • the insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate.
  • the die includes an integrated circuit therein and is mounted such that the heat-conducting plate is disposed between the die and the insulating plate.
  • the insulating base preferably includes signal conducting channels for providing electrical connections to the die, the heat-conducting plate having an opening therein for making the connections between the die and the conducting channels.
  • the assembly may also include a heat-spreading cover in thermal contact with the heat-conducting base plate, the heat-spreading cover overlying the die.
  • the heat-conducting channels are preferably filled with solder, and include a solder protrusion extending from the heat-conducting channels to facilitate attachment to a printed circuit board.
  • FIG. 1 is a top view of semiconductor package according to one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of package 10 through line 21 - 22 .
  • FIGS. 3 - 5 are cross-sectional views of the packaged chip at various stages in the packaging process.
  • FIG. 1 is a top view of semiconductor package 10 with a portion of the top heat-conducting plate cut away.
  • FIG. 2 is a cross-sectional view of package 10 through line 21 - 22 .
  • Semiconductor package 10 includes a semiconductor chip 15 that is mounted on a heat-conducting plate 12 .
  • Plate 12 is preferably constructed from copper.
  • Heat-conducting plate 12 is bonded to a substrate 14 by a layer of adhesive 13 .
  • Substrate 14 has a number of holes running therethrough. Some of these holes are utilized for making connections to the ground place of a printed circuit board on which package 10 is to be mounted. These connections are made by solder balls that are heated when the package is mounted to the printed circuit board. Exemplary holes of this type together with the solder balls are shown at 18 .
  • Signal connections between chip 15 and the printed circuit board are made through a copper plated holes in substrate 14 that connect pads on the top and bottom surface of substrate 14 .
  • Exemplary signal conducting paths are shown at 32 .
  • the pads 17 on chip 15 and the corresponding signal paths 32 on substrate 14 are connected via conventional wire bonding techniques.
  • Exemplary wire bonds are shown at 16 .
  • a heat-conducting top plate 19 may also be incorporated in the package to further dissipate heat generated by chip 15 . If such a plate is included, it is preferably connected to heat-conducting plate 12 at the periphery of heat-conducting plate 12 and forms a “roof” over chip 15 . However, embodiments lacking top plate 19 can be advantageously utilized.
  • the space 11 between top plate 19 and chip 15 is filled with a conventional encapsulating compound to protect chip 15 from damage. If top plate 19 is omitted, this encapsulating layer is still utilized to protect the chip.
  • An additional layer of molding compound can be included around the periphery of top plate 19 ; however, to simplify the drawing, this additional layer of molding compound has been omitted from the drawings.
  • the present invention can dissipate substantially more heat than prior art packages because the heat-conducting plate is more efficient in removing the heat from chip 15 and because the heat so removed is channeled to a larger heat dissipating surface.
  • Heat-conducting plate 12 has a higher thermal conductivity then the conventional packaging material on which the chip is normally mounted in prior art devices.
  • heat-conducting plate 12 is thermally connected to the ground plane on the printed circuit board via the heat-conducting plugs shown at 18 .
  • These heat-conducting plugs are preferably constructed from solder that “wets” the copper from which plate 12 is constructed. Hence, heat collected by heat-conducting plate 12 is effectively channeled to the ground plane of the printed circuit on which package 10 is mounted.
  • the heat-conducting plate is slightly smaller than substrate 14 .
  • the heat-conducting plate has dimensions that are 0.5 mm smaller than substrate 14 .
  • top plate 19 which also has a surface area that is substantially larger than chip 15 .
  • the present invention unlike prior art schemes, does not depend on the heat from the chip traversing the encapsulating compound above the chip, and hence, the thermal “bottleneck” that hampers prior art designs is substantially reduced in the present invention.
  • the heat conducting channels are between 0.5 mm and 0.65 mm to assure that these channels do not limit the heat flow from the chip to the ground plane of the printed circuit board.
  • the sizes and numbers of heat-conducting channels can be adjusted to match the heat output of the chip.
  • FIGS. 3 - 5 are cross-sectional views of the packaged chip at various stages in the packaging process.
  • the packaging process starts with a part in which the heat-spreading plate 51 is already attached to a substrate 54 by an adhesive layer 52 . It is assumed that vias 57 have been drilled through the substrate to the heat-spreading plane.
  • Chip 60 is then attached to heat spreader 51 and the wire bonds 61 between chip 60 and the signal pins 53 in the substrate are formed using a conventional wire bonding system. If the optional top heat dissipating plate 62 is to be used, it is attached to heat-spreading plate 51 leaving the package as shown in FIG. 4.
  • a conventional molding process is then used to encapsulate all of the components in an encapsulating layer 65 .
  • the vias 57 are then filled with small solder balls using a conventional drop in process and the substrate is then heated to melt the solder balls leaving the drilled holes filled with solder.
  • solder balls 66 are attached to the various vias and copper pads leaving the package as shown in FIG. 5. It is assumed that the above-described operations are performed on a strip of packages, not just the one shown in the figures. In the final step, the individual packages are separated using a conventional singulation process.
  • the heat from the chip is conducted away from the chip both by utilizing the optional heat dissipating plate and the conducting paths to the ground plane of the underlying printed circuit board. While the paths through the substrate to the ground plane can provide substantially more heat conducting capacity than the top heat dissipating plate 62 , the combination of the heat conducting plate under the chip and the top heat dissipating plate still provides substantially better heat conduction than prior art methods. Accordingly, if the top heat-conducting plate is used, the heat conducting vias may be omitted in cases in which the heat generated by the chip is less intense.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A circuit assembly having an insulating base, heat-conducting plate and circuit containing die is disclosed. The die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base. The insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate. The die includes an integrated circuit therein and is mounted such that the heat-conducting plate is disposed between the die and the insulating plate. The insulating base preferably includes signal conducting channels for providing electrical connections to the die, the heat-conducting plate having an opening therein for making the connections between the die and the conducting channels. The assembly may also include a heat-spreading cover in thermal contact with the heat-conducting base plate, the heat-spreading cover overlying the die. The heat-conducting channels are preferably filled with solder, and include a solder protrusion extending from the heat-conducting channels.

Description

    FIELD OF THE INVENTION
  • The present invention relates to packages for integrated circuits and the like. [0001]
    • BACKGROUND OF THE INVENTION
  • Semiconductor chips are typically sealed in a package that is soldered to a printed circuit board. The various connections between the electrical components on the chip and the conductors on the printed circuit board are made through conductors that pass through the package and are connected to the printed circuit board by solder. Within the package, the chip is encapsulated in a potting compound that protects the chip from damage caused by exposure to moisture and oxygen. [0002]
  • Early chip designs contained relatively few active components operating at relatively slow speeds, and hence, heat dissipation was not a major problem. However, as chip speeds and component densities have increased, heat dissipation has become a major problem. One prior art method for increasing the heat dissipation in a semiconductor package utilizes a heat-conducting cover. In this design, the cover is placed over the encapsulated chip to improve the heat conduction from the chip to the air above the chip. Unfortunately, this approach is of limited value since the heat dissipating cover depends on the conduction of the heat from the chip through the encapsulating material, which is a poor heat conductor. In addition, the surface area of the cover is limited to the size of the semiconductor package, and hence, the amount of heat that can be dissipated by the cover is limited. [0003]
    • SUMMARY OF THE INVENTION
  • The present invention is a circuit assembly having an insulating base, heat-conducting plate and circuit-containing die. The die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base. The insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate. The die includes an integrated circuit therein and is mounted such that the heat-conducting plate is disposed between the die and the insulating plate. The insulating base preferably includes signal conducting channels for providing electrical connections to the die, the heat-conducting plate having an opening therein for making the connections between the die and the conducting channels. The assembly may also include a heat-spreading cover in thermal contact with the heat-conducting base plate, the heat-spreading cover overlying the die. The heat-conducting channels are preferably filled with solder, and include a solder protrusion extending from the heat-conducting channels to facilitate attachment to a printed circuit board.[0004]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top view of semiconductor package according to one embodiment of the present invention. [0005]
  • FIG. 2 is a cross-sectional view of [0006] package 10 through line 21-22.
  • FIGS. [0007] 3-5 are cross-sectional views of the packaged chip at various stages in the packaging process.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
  • The manner in which the present invention provides its advantages can be more easily understood with reference to FIGS. 1 and 2. FIG. 1 is a top view of [0008] semiconductor package 10 with a portion of the top heat-conducting plate cut away. FIG. 2 is a cross-sectional view of package 10 through line 21-22. Semiconductor package 10 includes a semiconductor chip 15 that is mounted on a heat-conducting plate 12. Plate 12 is preferably constructed from copper. Heat-conducting plate 12 is bonded to a substrate 14 by a layer of adhesive 13. Substrate 14 has a number of holes running therethrough. Some of these holes are utilized for making connections to the ground place of a printed circuit board on which package 10 is to be mounted. These connections are made by solder balls that are heated when the package is mounted to the printed circuit board. Exemplary holes of this type together with the solder balls are shown at 18.
  • Signal connections between [0009] chip 15 and the printed circuit board are made through a copper plated holes in substrate 14 that connect pads on the top and bottom surface of substrate 14. Exemplary signal conducting paths are shown at 32. The pads 17 on chip 15 and the corresponding signal paths 32 on substrate 14 are connected via conventional wire bonding techniques. Exemplary wire bonds are shown at 16.
  • A heat-conducting [0010] top plate 19 may also be incorporated in the package to further dissipate heat generated by chip 15. If such a plate is included, it is preferably connected to heat-conducting plate 12 at the periphery of heat-conducting plate 12 and forms a “roof” over chip 15. However, embodiments lacking top plate 19 can be advantageously utilized. The space 11 between top plate 19 and chip 15 is filled with a conventional encapsulating compound to protect chip 15 from damage. If top plate 19 is omitted, this encapsulating layer is still utilized to protect the chip. An additional layer of molding compound can be included around the periphery of top plate 19; however, to simplify the drawing, this additional layer of molding compound has been omitted from the drawings.
  • The present invention can dissipate substantially more heat than prior art packages because the heat-conducting plate is more efficient in removing the heat from [0011] chip 15 and because the heat so removed is channeled to a larger heat dissipating surface. Heat-conducting plate 12 has a higher thermal conductivity then the conventional packaging material on which the chip is normally mounted in prior art devices. In addition, heat-conducting plate 12 is thermally connected to the ground plane on the printed circuit board via the heat-conducting plugs shown at 18. These heat-conducting plugs are preferably constructed from solder that “wets” the copper from which plate 12 is constructed. Hence, heat collected by heat-conducting plate 12 is effectively channeled to the ground plane of the printed circuit on which package 10 is mounted. Since the ground plane of the circuit board has considerably more surface area exposed to the air than chip 15 or top 19, heat can be more effectively transferred to the air above the ground plane provided the heat-conducting plugs have sufficient combined cross-sectional area to assure that the plugs do not inhibit the flow of heat to the ground plane. In optimize the heat transfer area, the heat-conducting plate is slightly smaller than substrate 14. In the preferred embodiment of the invention, the heat-conducting plate has dimensions that are 0.5 mm smaller than substrate 14.
  • In addition, heat from the heat-conducting plate is routed directly to [0012] top plate 19, which also has a surface area that is substantially larger than chip 15. It should be noted that the present invention, unlike prior art schemes, does not depend on the heat from the chip traversing the encapsulating compound above the chip, and hence, the thermal “bottleneck” that hampers prior art designs is substantially reduced in the present invention. In the preferred embodiment of the invention, the heat conducting channels are between 0.5 mm and 0.65 mm to assure that these channels do not limit the heat flow from the chip to the ground plane of the printed circuit board. However, the sizes and numbers of heat-conducting channels can be adjusted to match the heat output of the chip.
  • The manner in which the semiconductor chip is packaged using the present invention may be more easily understood with reference to FIGS. [0013] 3-5, which are cross-sectional views of the packaged chip at various stages in the packaging process. Referring to FIG. 3, in the preferred embodiment of the present invention, the packaging process starts with a part in which the heat-spreading plate 51 is already attached to a substrate 54 by an adhesive layer 52. It is assumed that vias 57 have been drilled through the substrate to the heat-spreading plane.
  • [0014] Chip 60 is then attached to heat spreader 51 and the wire bonds 61 between chip 60 and the signal pins 53 in the substrate are formed using a conventional wire bonding system. If the optional top heat dissipating plate 62 is to be used, it is attached to heat-spreading plate 51 leaving the package as shown in FIG. 4.
  • A conventional molding process is then used to encapsulate all of the components in an [0015] encapsulating layer 65. The vias 57 are then filled with small solder balls using a conventional drop in process and the substrate is then heated to melt the solder balls leaving the drilled holes filled with solder. Finally, solder balls 66 are attached to the various vias and copper pads leaving the package as shown in FIG. 5. It is assumed that the above-described operations are performed on a strip of packages, not just the one shown in the figures. In the final step, the individual packages are separated using a conventional singulation process.
  • In the above-described embodiments of the present invention, the heat from the chip is conducted away from the chip both by utilizing the optional heat dissipating plate and the conducting paths to the ground plane of the underlying printed circuit board. While the paths through the substrate to the ground plane can provide substantially more heat conducting capacity than the top [0016] heat dissipating plate 62, the combination of the heat conducting plate under the chip and the top heat dissipating plate still provides substantially better heat conduction than prior art methods. Accordingly, if the top heat-conducting plate is used, the heat conducting vias may be omitted in cases in which the heat generated by the chip is less intense.
  • Various modifications to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims. [0017]

Claims (8)

What is claimed is:
1. A circuit assembly comprising:
a heat-conducting base plate;
an insulating base; and
a die having an integrated circuit therein, said die being in thermal contact with said heat-conducting base plate, said heat-conducting plate being disposed between said die and said insulating base.
2. The circuit assembly of claim 1 wherein said insulating base further comprises a plurality of heat-conducting channels, said heat-conducting channels being in thermal contact with said heat-conducting plate.
3. The circuit assembly of claim 2 wherein said insulating base further comprises signal conducting channels for providing electrical connections to said die, said heat-conducting plate having an opening therein for making said connections between said die and said conducting channels.
4. The circuit assembly of claim 1 further comprising a heat-spreading cover in thermal contact with said heat-conducting base plate, said heat-spreading cover overlying said die.
5. The circuit assembly of claim 2 wherein said heat-conducting channels comprise solder.
6. The circuit assembly of claim 2 further comprising a solder protrusion extending from said heat-conducting channels.
7. The circuit assembly of claim 1 wherein said heat-conducting base plate comprises copper.
8. The circuit assembly of claim 1 wherein said heat-conducting plate is bonded to said insulating base.
US10/327,465 2002-12-19 2002-12-19 Thermally enhanced package for an integrated circuit Abandoned US20040119158A1 (en)

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US10/327,465 US20040119158A1 (en) 2002-12-19 2002-12-19 Thermally enhanced package for an integrated circuit
PCT/US2003/039922 WO2004062333A1 (en) 2002-12-19 2003-12-16 Thermally enhanced package for an integrated circuit
CNA2003801000441A CN1685777A (en) 2002-12-19 2003-12-16 Thermally enhanced package for an integrated circuit
JP2003419002A JP2004200694A (en) 2002-12-19 2003-12-17 Thermal property enhancement package for integrated circuits
US11/345,104 US7312525B2 (en) 2002-12-19 2006-01-31 Thermally enhanced package for an integrated circuit

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US10/327,465 US20040119158A1 (en) 2002-12-19 2002-12-19 Thermally enhanced package for an integrated circuit

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US11/345,104 Expired - Lifetime US7312525B2 (en) 2002-12-19 2006-01-31 Thermally enhanced package for an integrated circuit

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JP (1) JP2004200694A (en)
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040075166A1 (en) * 2002-07-18 2004-04-22 Orient Semiconductor Electronics, Ltd. Semiconductor device with heat-dissipating capability
US20080211079A1 (en) * 2006-12-27 2008-09-04 Masanori Onodera Heat dissipation methods and structures for semiconductor device
US20110116244A1 (en) * 2008-01-02 2011-05-19 Clayton James E Thin multi-chip flex module
US20160300778A1 (en) * 2014-05-30 2016-10-13 Fuji Electric Co., Ltd. Semiconductor device
US9554453B2 (en) * 2013-02-26 2017-01-24 Mediatek Inc. Printed circuit board structure with heat dissipation function
US9814142B1 (en) * 2015-06-24 2017-11-07 Automated Assembly Corporation Electronic devices wire bonded to substrate through an adhesive layer and method of making the same

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8049313B2 (en) * 2006-09-20 2011-11-01 Freescale Semiconductor, Inc. Heat spreader for semiconductor package
US8643172B2 (en) * 2007-06-08 2014-02-04 Freescale Semiconductor, Inc. Heat spreader for center gate molding
US8178956B2 (en) * 2007-12-13 2012-05-15 Stats Chippac Ltd. Integrated circuit package system for shielding electromagnetic interference
US20110012257A1 (en) * 2009-07-14 2011-01-20 Freescale Semiconductor, Inc Heat spreader for semiconductor package
US8248803B2 (en) * 2010-03-31 2012-08-21 Hong Kong Applied Science and Technology Research Institute Company Limited Semiconductor package and method of manufacturing the same
US20170071076A1 (en) * 2015-09-03 2017-03-09 Adlink Technology Inc. Thermal conducting structure applied to network control automation system
KR102437673B1 (en) * 2015-09-09 2022-08-26 삼성전자주식회사 Semiconductor device
US10290678B2 (en) * 2017-09-26 2019-05-14 Globalfoundries Singapore Pte. Ltd. Magnetic shielding package structure for MRAM device and method for producing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293301A (en) * 1990-11-30 1994-03-08 Shinko Electric Industries Co., Ltd. Semiconductor device and lead frame used therein
US5600179A (en) * 1994-09-27 1997-02-04 Nec Corporation Package for packaging a semiconductor device suitable for being connected to a connection object by soldering
US5834839A (en) * 1997-05-22 1998-11-10 Lsi Logic Corporation Preserving clearance between encapsulant and PCB for cavity-down single-tier package assembly
US6206997B1 (en) * 1999-02-11 2001-03-27 International Business Machines Corporation Method for bonding heat sinks to overmolds and device formed thereby
US6282094B1 (en) * 1999-04-12 2001-08-28 Siliconware Precision Industries, Co., Ltd. Ball-grid array integrated circuit package with an embedded type of heat-dissipation structure and method of manufacturing the same
US6528882B2 (en) * 2000-10-04 2003-03-04 Advanced Semiconductor Engineering, Inc. Thermal enhanced ball grid array package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011304A (en) * 1997-05-05 2000-01-04 Lsi Logic Corporation Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid
TW418511B (en) * 1998-10-12 2001-01-11 Siliconware Precision Industries Co Ltd Packaged device of exposed heat sink
KR100391093B1 (en) * 2001-01-04 2003-07-12 삼성전자주식회사 Ball Grid Array package mounting heat sink
US6707168B1 (en) * 2001-05-04 2004-03-16 Amkor Technology, Inc. Shielded semiconductor package with single-sided substrate and method for making the same
US6882041B1 (en) * 2002-02-05 2005-04-19 Altera Corporation Thermally enhanced metal capped BGA package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293301A (en) * 1990-11-30 1994-03-08 Shinko Electric Industries Co., Ltd. Semiconductor device and lead frame used therein
US5600179A (en) * 1994-09-27 1997-02-04 Nec Corporation Package for packaging a semiconductor device suitable for being connected to a connection object by soldering
US5834839A (en) * 1997-05-22 1998-11-10 Lsi Logic Corporation Preserving clearance between encapsulant and PCB for cavity-down single-tier package assembly
US6206997B1 (en) * 1999-02-11 2001-03-27 International Business Machines Corporation Method for bonding heat sinks to overmolds and device formed thereby
US6282094B1 (en) * 1999-04-12 2001-08-28 Siliconware Precision Industries, Co., Ltd. Ball-grid array integrated circuit package with an embedded type of heat-dissipation structure and method of manufacturing the same
US6528882B2 (en) * 2000-10-04 2003-03-04 Advanced Semiconductor Engineering, Inc. Thermal enhanced ball grid array package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040075166A1 (en) * 2002-07-18 2004-04-22 Orient Semiconductor Electronics, Ltd. Semiconductor device with heat-dissipating capability
US6847111B2 (en) * 2002-07-18 2005-01-25 Orient Semiconductor Electronics, Ltd. Semiconductor device with heat-dissipating capability
US20080211079A1 (en) * 2006-12-27 2008-09-04 Masanori Onodera Heat dissipation methods and structures for semiconductor device
US8531019B2 (en) * 2006-12-27 2013-09-10 Spansion Llc Heat dissipation methods and structures for semiconductor device
US20110116244A1 (en) * 2008-01-02 2011-05-19 Clayton James E Thin multi-chip flex module
US8559181B2 (en) * 2008-01-02 2013-10-15 Microelectronics Assembly Technologies, Inc. Thin multi-chip flex module
US9554453B2 (en) * 2013-02-26 2017-01-24 Mediatek Inc. Printed circuit board structure with heat dissipation function
US20160300778A1 (en) * 2014-05-30 2016-10-13 Fuji Electric Co., Ltd. Semiconductor device
US10192806B2 (en) * 2014-05-30 2019-01-29 Fuji Electric Co., Ltd. Semiconductor device
US9814142B1 (en) * 2015-06-24 2017-11-07 Automated Assembly Corporation Electronic devices wire bonded to substrate through an adhesive layer and method of making the same

Also Published As

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WO2004062333A1 (en) 2004-07-22
US7312525B2 (en) 2007-12-25
CN1685777A (en) 2005-10-19
US20060125089A1 (en) 2006-06-15

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