JPH04346250A - Mounting method for semiconductor device - Google Patents
Mounting method for semiconductor deviceInfo
- Publication number
- JPH04346250A JPH04346250A JP11836391A JP11836391A JPH04346250A JP H04346250 A JPH04346250 A JP H04346250A JP 11836391 A JP11836391 A JP 11836391A JP 11836391 A JP11836391 A JP 11836391A JP H04346250 A JPH04346250 A JP H04346250A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- cavity
- semiconductor device
- resin
- mounting method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 13
- 230000017525 heat dissipation Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 17
- 238000009429 electrical wiring Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、フリップチップ型の
ような半導体装置(以下、「ICチップ」と記す)の単
層又は多層電気配線基板(以下、「基板」と記す)への
実装方法に関するものである。[Industrial Application Field] This invention relates to a method for mounting a semiconductor device such as a flip-chip type (hereinafter referred to as an "IC chip") onto a single-layer or multilayer electrical wiring board (hereinafter referred to as a "substrate"). It is related to.
【0002】0002
【従来の技術】従来、基板へのICチップの実装方法の
一つにフリップチップ実装方法がある。この実装方法は
基板の表面に配線された電気回路の電極に、バンプを介
してICチップの電極をボンディングする方法であって
、所謂ワイヤボンド実装方法に比べて実装密度を高めら
れる優れた特徴がある。2. Description of the Related Art Conventionally, one of the methods for mounting an IC chip on a substrate is a flip-chip mounting method. This mounting method is a method in which the electrodes of an IC chip are bonded via bumps to the electrodes of an electric circuit wired on the surface of the board, and has the advantage of increasing the packaging density compared to the so-called wire bond mounting method. be.
【0003】0003
【発明が解決しようとする課題】しかし、前記フリップ
チップ実装方法は、ICチップの裏面が基板に密着しな
いために放熱性が悪いという欠点がある。この欠点を補
うために、ICチップに直接ヒートシンクを装着しよう
としても装着することができず、間に基板等を入れなけ
ればならなかったために放熱性が良くないという欠点が
あった。この発明は、このような欠点を解決するICチ
ップの実装方法を提供しようとするものである。However, the flip-chip mounting method has a drawback in that heat dissipation is poor because the back surface of the IC chip does not come into close contact with the substrate. Even if an attempt was made to attach a heat sink directly to the IC chip in order to compensate for this disadvantage, it could not be done and a board or the like had to be inserted between the IC chips, resulting in poor heat dissipation. The present invention aims to provide an IC chip mounting method that solves these drawbacks.
【0004】0004
【課題を解決するための手段】そのためこの発明は、キ
ャビティを有する基板のそのキャビティ内に配線された
電気回路の電極に、バンプを介してICチップの電極を
接続し、このように接続されたICチップのその電極が
無い面及び前記キャビティの少なくとも側壁に跨がって
、熱伝導率の高い樹脂を封入し、前記ICチップから発
する熱を前記基板に伝導、発散させ、或いは前記キャビ
ティの上部に前記樹脂を介してヒートシンクを装着し、
より熱発散を高めさせるようにした。[Means for Solving the Problems] Therefore, the present invention connects the electrodes of an IC chip via bumps to the electrodes of an electric circuit wired in the cavity of a substrate having a cavity, and connects the electrodes of an IC chip in this way. A resin with high thermal conductivity is sealed over the surface of the IC chip where no electrode is provided and at least the side wall of the cavity, and the heat emitted from the IC chip is conducted to and dissipated from the substrate, or the upper part of the cavity is sealed. Attach a heat sink to the resin via the resin,
Improved heat dissipation.
【0005】[0005]
【作用】従って、この発明のICチップの実装方法であ
れば、ICチップから発生する熱の大半を基板を介して
伝導、発散でき、しかも通常のフリップチップ実装方法
に比べて、ICチップを基板の中に実装するため、薄型
実装が可能である。[Function] Therefore, with the IC chip mounting method of the present invention, most of the heat generated from the IC chip can be conducted and dissipated through the substrate. Because it is mounted inside the device, thin mounting is possible.
【0006】[0006]
【実施例】以下、この発明の実施例を図面と共に詳述す
る。図1はこの発明のICチップの実装方法の第1の実
施例を説明するための断面図、図2はこの発明のICチ
ップの実装方法の第2の実施例を説明するための断面図
、そして図3はこの発明のICチップの実装方法の第3
の実施例を説明するとめの断面図である。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view for explaining a first embodiment of the IC chip mounting method of the present invention, FIG. 2 is a cross-sectional view for explaining a second embodiment of the IC chip mounting method of the present invention, FIG. 3 shows the third method of mounting an IC chip according to the present invention.
FIG.
【0007】先ず、図1を用いてこの発明のICチップ
の実装方法を説明する。1はICチップで、その複数の
電極(図示していない)にバンプ2を接合してある。3
はセラミック、ガラスエポキシ樹脂等からなる基板で、
その表面にキャビティ4を形成し、その底面には電極5
を有する電気配線パターン(図示していない)が施され
ている。First, a method for mounting an IC chip according to the present invention will be explained with reference to FIG. 1 is an IC chip, and bumps 2 are bonded to a plurality of electrodes (not shown) of the IC chip. 3
is a substrate made of ceramic, glass epoxy resin, etc.
A cavity 4 is formed on its surface, and an electrode 5 is formed on its bottom.
An electrical wiring pattern (not shown) is provided.
【0008】このような構造の基板3のキャビティ4に
、フェースダウンでICチップ1を配置し、バンプ2を
電極5に接合させる。即ち、フリップチップ実装を行う
。その後、ICチップ1の裏面6及びキャビティ4の側
壁7に跨がって、そして図1の実施例ではキャビティ4
周辺の基板3の表面8にも跨がって、熱伝導率の高い樹
脂9、例えばエポキシ系のポッティング樹脂で封止する
。The IC chip 1 is placed face down in the cavity 4 of the substrate 3 having such a structure, and the bumps 2 are bonded to the electrodes 5. That is, flip-chip mounting is performed. Thereafter, it is applied over the back surface 6 of the IC chip 1 and the side wall 7 of the cavity 4, and in the embodiment of FIG.
The peripheral surface 8 of the substrate 3 is also covered and sealed with a resin 9 having high thermal conductivity, for example, an epoxy potting resin.
【0009】図2の第2の実施例では、図1の第1の実
施例と同様に、基板3のキャビティ4内にフリップチッ
プ実装したICチップ1の、その裏面6及び側壁7に跨
がって、樹脂の量をコントロールして、薄い厚さの樹脂
でICチップ1を封止し、この樹脂層を介してキャビテ
ィ4の周辺の基板3の表面8に跨がってヒートシンク1
0を装着し、より一層熱発散を高めさせるようにした。
11は櫛形のフィンである。In the second embodiment shown in FIG. 2, similar to the first embodiment shown in FIG. By controlling the amount of resin, the IC chip 1 is sealed with a thin resin, and the heat sink 1 is spread over the surface 8 of the substrate 3 around the cavity 4 via this resin layer.
0 was installed to further increase heat dissipation. 11 is a comb-shaped fin.
【0010】前記の第1及び第2の実施例において、キ
ャビティ4は一層の基板3に形成し、その中にICチッ
プ1を配置したが、図3の第3の実施例では、キャビテ
ィ4を多層基板3aに形成した。図3の実施例では多層
基板3aは5枚の基板からなり、その内の3枚の基板に
わたってキャビティ4を形成している。そして図1の実
施例のように、このキャビティ4内にICチップ1を配
置し、樹脂9で封止している。12は内層電極を示し、
13はビアホールを指し、これらのビアホール13で内
層電極12間を接続している。In the first and second embodiments described above, the cavity 4 was formed in a single layer of the substrate 3 and the IC chip 1 was placed therein, but in the third embodiment shown in FIG. It was formed on a multilayer substrate 3a. In the embodiment shown in FIG. 3, the multilayer substrate 3a consists of five substrates, and the cavity 4 is formed across three of the substrates. As in the embodiment shown in FIG. 1, the IC chip 1 is placed inside this cavity 4 and sealed with resin 9. 12 indicates an inner layer electrode;
Reference numeral 13 indicates via holes, and these via holes 13 connect the inner layer electrodes 12.
【0011】なお、前記の説明では、バンプ2をICチ
ップ1の電極に接合した場合を例示して説明したが、こ
れらのバンプ2は電気配線パターンの電極5に予め接合
しておいてもよいことはいうまでもない。In the above description, the bumps 2 are bonded to the electrodes of the IC chip 1, but these bumps 2 may be bonded to the electrodes 5 of the electrical wiring pattern in advance. Needless to say.
【0012】0012
【発明の効果】以上の説明から明らかなように、この発
明のICチップの実装方法によれば、ICチップから発
生する熱の大半を基板を介して伝導、発散できる。従っ
て、発熱量の多いICチップでもフリップチップ実装が
でき、そしてより一層高密度実装化ができる。そしてま
た、通常のフリップチップ実装方法に比べて、ICチッ
プを基板の中に実装するため、薄型実装が可能になる。
それ故、電子機器を超小型、超薄型に構成できる等の望
ましい効果が得られる。As is clear from the above description, according to the IC chip mounting method of the present invention, most of the heat generated from the IC chip can be conducted and dissipated through the substrate. Therefore, flip-chip mounting is possible even with IC chips that generate a large amount of heat, and even higher density mounting is possible. Furthermore, since the IC chip is mounted within the substrate, thinner mounting is possible compared to the normal flip-chip mounting method. Therefore, desirable effects such as making the electronic device ultra-small and ultra-thin can be obtained.
【図1】この発明のICチップの実装方法の第1の実施
例を説明するための断面図である。FIG. 1 is a cross-sectional view for explaining a first embodiment of the IC chip mounting method of the present invention.
【図2】この発明のICチップの実装方法の第2の実施
例を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining a second embodiment of the IC chip mounting method of the present invention.
【図3】この発明のICチップの実装方法の第3の実施
例を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a third embodiment of the IC chip mounting method of the present invention.
1 半導体装置(ICチップ) 2 バンプ 3 (電気配線)基板 3a 多層(電気配線)基板 4 キャビティ 5 電極 6 裏面 7 側壁 8 表面 9 樹脂 10 ヒートシンク 11 フィン 12 内層電極 13 ビアホール 1 Semiconductor device (IC chip) 2 Bump 3 (Electrical wiring) board 3a Multilayer (electrical wiring) board 4 Cavity 5 Electrode 6 Back side 7 Side wall 8 Surface 9 Resin 10 Heat sink 11 Fin 12 Inner layer electrode 13 Beer hall
Claims (2)
ビティ内に配線された電気回路の電極に、バンプを介し
て半導体装置の電極を接続し、このように接続された該
半導体装置の該電極が無い面及び前記キャビティの少な
くとも側壁に跨がって、熱伝導率の高い樹脂で封入し、
前記半導体装置から発する熱を伝導、発散させることを
特徴とする半導体装置の実装方法。Claim 1: An electrode of a semiconductor device is connected via a bump to an electrode of an electric circuit wired in the cavity of an electric wiring board having a cavity, and the electrode of the semiconductor device connected in this way is encapsulating with a resin having high thermal conductivity across the empty surface and at least the side wall of the cavity,
A method for mounting a semiconductor device, comprising conducting and dissipating heat generated from the semiconductor device.
ヒートシンクを装着し、より熱発散を高めさせることを
特徴とする請求項1に記載の半導体装置の実装方法。2. The method of mounting a semiconductor device according to claim 1, further comprising attaching a heat sink to the upper part of the cavity via the resin to further enhance heat dissipation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11836391A JPH04346250A (en) | 1991-05-23 | 1991-05-23 | Mounting method for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11836391A JPH04346250A (en) | 1991-05-23 | 1991-05-23 | Mounting method for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04346250A true JPH04346250A (en) | 1992-12-02 |
Family
ID=14734853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11836391A Pending JPH04346250A (en) | 1991-05-23 | 1991-05-23 | Mounting method for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04346250A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002232257A (en) * | 2001-01-31 | 2002-08-16 | Kyocera Corp | Electronic parts device and manufacturing method of the same |
-
1991
- 1991-05-23 JP JP11836391A patent/JPH04346250A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002232257A (en) * | 2001-01-31 | 2002-08-16 | Kyocera Corp | Electronic parts device and manufacturing method of the same |
JP4582922B2 (en) * | 2001-01-31 | 2010-11-17 | 京セラ株式会社 | Electronic component device and manufacturing method thereof |
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