JPS62250648A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS62250648A
JPS62250648A JP61094287A JP9428786A JPS62250648A JP S62250648 A JPS62250648 A JP S62250648A JP 61094287 A JP61094287 A JP 61094287A JP 9428786 A JP9428786 A JP 9428786A JP S62250648 A JPS62250648 A JP S62250648A
Authority
JP
Japan
Prior art keywords
flip chip
substrate
wiring pattern
chip
metallic base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61094287A
Other languages
Japanese (ja)
Inventor
Masayasu Onishi
正泰 大西
Hiroyuki Nakano
弘幸 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP61094287A priority Critical patent/JPS62250648A/en
Publication of JPS62250648A publication Critical patent/JPS62250648A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a shielding effect to a flip chip while improving heat- dissipating properties without lowering mounting density by mounting a chip part onto a metallic base substrate in three dimensions and coating the upper surface of the flip chip with the metallic base substrate. CONSTITUTION:The lower surface of a flip chip 10 has projecting electrodes 11a, 11b, a predetermined wiring pattern 14 is shaped to a ceramic substrate 12 by Al, etc. previously, and the flip chip 10 is connected at the prescribed position of the wiring pattern. The flip chip 10 is covered and sealed with a resin 13 having excellent thermal conductivity and adhesive properties with a metal, and a metallic base substrate 15 is fastened to the upper section of the resin 13 before the resin cures. A metallic base 16 is shaped to the lower surface of the substrate 15, and a wiring pattern 18 consisting of a metallic section is formed to the upper section of the metallic base 16 through an insulating surface 17. Chip parts 19, 20 are mounted previously to the wiring pattern 18 as the upper surface of the substrate 15. When a hybrid integrated circuit constituted in this manner is operated, heat generated in the flip chip 10 is transmitted easily over the resin 13 and the metallic base substrate 15 and dissipated.

Description

【発明の詳細な説明】 〔発明の分野〕 本発明はフリップチップをフェースダウンボンディング
して構成される混成集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a hybrid integrated circuit device constructed by face-down bonding flip chips.

〔発明の概要〕[Summary of the invention]

本発明による混成集積回路装置は、基板上にフェースダ
ウンボンディングにより接続されたフリップチップの上
部に熱伝導性の良い樹脂を介して放熱効果を有する金属
ベース基板を接続すると共に、その上面の所定の配線パ
ターンにチップ部品を実装し基板の配線パターンとリー
ド線を介して接続することによって混成集積回路を立体
的に高密度実装して構成したものである。In the hybrid integrated circuit device according to the present invention, a metal base substrate having a heat dissipation effect is connected to the top of a flip chip connected to the substrate by face-down bonding via a resin with good thermal conductivity, and a predetermined portion of the top surface A hybrid integrated circuit is constructed by mounting chip components on a wiring pattern and connecting them to the wiring pattern of a board via lead wires in a three-dimensional manner with high density.

（従来技術とその問題点〕 （従来技術） 近年混成集積回路において、第２図に示すように集積回
路素子やチップ部品（以下フリップチップという）１を
基板２上に実装するために、フリップチップ１の所定位
置にはんだにより突起電極３を形成した後、突起電極面
を下向きとしてセラミック基板２等の対応する配線パタ
ーン４に合わせてリフロ一工程又は熱圧着等によっては
んだを）８解させ、ボンディングするフェースダウンボ
ンディングが用いられている。そしてフリップチップ１
はボンディング後樹脂５によって封止されている。又基
板２上にコンデンサやコイル、抵抗等のチップ部品６，
７が同様にして実装されて混成集積回路が平面的に形成
されている。(Prior art and its problems) (Prior art) In recent years, in hybrid integrated circuits, flip chips are used to mount integrated circuit elements and chip components (hereinafter referred to as flip chips) 1 on a substrate 2, as shown in FIG. After forming a protruding electrode 3 with solder at a predetermined position of 1, the protruding electrode surface is facing downward and the solder is melted by a reflow process or thermocompression bonding in accordance with the corresponding wiring pattern 4 of the ceramic substrate 2, etc., and bonding is performed. Face-down bonding is used. and flip chip 1
is sealed with resin 5 after bonding. Also, chip parts 6 such as capacitors, coils, and resistors are mounted on the substrate 2.
7 is similarly mounted to form a two-dimensional hybrid integrated circuit.

このようなフリップチップを有する混成集積回路では、
フリップチップからの熱放散は主として突起電極３を介
しての放熱であるため高密度集積化が進み、フリップチ
ップの消費電力が増加した場合には熱放散性が悪くなる
という問題点がある。In a hybrid integrated circuit with such a flip chip,
Since the heat dissipation from the flip chip is mainly through the protruding electrodes 3, there is a problem that the heat dissipation performance deteriorates as the power consumption of the flip chip increases as the density of integration progresses.

（発明が解決しようとする問題点） そこで第３図に示すようにフリップチップの電極面と反
対側の面に熱伝導体８を介してヒートシンク９を設ける
ようにした混成集積回路が提案されている（特開昭５５
−５３４３３号、特開昭５８−２００５６０号）。この
ような混成集積回路では、基板２上に他に接続されるチ
ップ部品の形状によってはヒートシンク９と接触するこ
とがあるため、実装面積が拡大してしまうという問題点
があった。(Problems to be Solved by the Invention) Therefore, as shown in FIG. 3, a hybrid integrated circuit has been proposed in which a heat sink 9 is provided on the surface of the flip chip opposite to the electrode surface via a thermal conductor 8. There is (Unexamined Japanese Patent Publication No. 1983)
-53433, JP-A No. 58-200560). In such a hybrid integrated circuit, depending on the shape of other chip components connected on the substrate 2, the chips may come into contact with the heat sink 9, resulting in an increase in the mounting area.

〔発明の目的〕 本発明はこのような従来のフリップチップを用いた混成
集積回路の問題点に鑑みてなされたちのであって、実装
密度を低下させることなく熱放散性を改善できるように
することを技術的課題とする。[Object of the Invention] The present invention has been made in view of the problems of hybrid integrated circuits using conventional flip chips, and it is an object of the present invention to improve heat dissipation without reducing packaging density. is a technical issue.

〔発明の構成と効果〕[Structure and effects of the invention]

（構成） 本発明はフリップチップをフェースダウンボンディング
して構成される混成集積回路装置であって第１図に示す
ように、一面に複数の電極を有しこの電極を基板（１２
）にフェースダウンボンディングして固定されたフリッ
プチップ（１０）と、フリップチップ（ｌＯ）を被う高
熱伝導性の樹脂（１３）と、上面に所定の配線パターン
（１８）を有しチップ部品（１９，２０）が実装され樹
脂（１３）上に設けられた金属ベース基板（１５）と、
金属ベース基板（１５）及び基板（１２）を接続するリ
ード線（２１）と、を有することを特徴とするものであ
る。(Structure) The present invention is a hybrid integrated circuit device constructed by face-down bonding flip chips, and as shown in FIG.
), a flip chip (10) fixed by face-down bonding to a chip component ( 19, 20) mounted on a metal base substrate (15) provided on a resin (13);
It is characterized by having a metal base substrate (15) and a lead wire (21) connecting the substrate (12).

（作用） このような特徴を有する本発明によれば、基板上にフェ
ースダウンボンディングにより接続されたフリップチッ
プ（１０）からの発熱は、高熱伝導性の樹脂（１３）を
介してその上部のヒートシンクを兼用した金属ベース基
板（１５）に伝わって放熱される。更に金属ベース基板
（１５）上に所定のパターンを形成してチップ部品（１
９，２０）を実装し、基板との間にリード線（２１）に
よって接続するようにしている。(Function) According to the present invention having such characteristics, heat generated from the flip chip (10) connected to the substrate by face-down bonding is transferred to the heat sink on the upper part of the flip chip (10) via the highly thermally conductive resin (13). The heat is transmitted to the metal base substrate (15) which also serves as a radiator. Furthermore, a predetermined pattern is formed on the metal base substrate (15) to form a chip component (1).
9, 20) are mounted and connected to the board via lead wires (21).

（効果） 従って本発明によれば、フリップチップが発熱する場合
にも熱放散性の良い混成集積回路とすることができる。(Effects) Therefore, according to the present invention, a hybrid integrated circuit with good heat dissipation properties can be obtained even when the flip chip generates heat.

又金属ベース基板上にチップ部品を立体的に実装するよ
うにしているため、ヒートシンクを有する従来の混成集
積回路より高密度な実装をすることができる。又フリッ
プチップの上面が金属ベース基板で被われているため、
フリップチップに対するシールド効果を得ることもでき
る。Furthermore, since the chip components are three-dimensionally mounted on the metal base substrate, it is possible to perform higher density mounting than conventional hybrid integrated circuits having heat sinks. Also, since the top surface of the flip chip is covered with a metal base substrate,
It is also possible to obtain a shielding effect against flip chips.

〔実施例の説明〕[Explanation of Examples]

第１図は本発明の一実施例による混成集積回路の構造を
示す断面図である。フリップチップ１０は前述した従来
例と同様に下面に突起電極１１３゜１１ｂを有している
。セラミック基板１２にはあらかじめＡｊ！等によって
所定の配線パターン１４が形成されており、その配線パ
ターン１４の所定位置にフリップチップｌＯをはんだリ
フロー法や熱圧着法によって接続する。そしてフリップ
チップ１０を熱伝導性、金属との接着性が良い樹脂１３
で被って封止し、この樹脂１３が硬化する前に金属ベー
ス基板１５をその上部に固定する。金属ベース基板１５
は下面に金属ベース１６が形成されその上部には絶縁面
１７を介して所定の金属部から成る配線パターン１８が
形成されている。金属ベース基板１５の上面の配線パタ
ーン１８にはあらかじめコンデンサ、コイル、抵抗等の
チップ部品１９．２０が実装されている。そしてこの金
属ベース基板１５の配線パターン１８とセラミック基板
１２の配線パターン１４とをリード線２１を介して任意
の位置で接続して混成集積回路を構成する。FIG. 1 is a sectional view showing the structure of a hybrid integrated circuit according to an embodiment of the present invention. The flip chip 10 has a protruding electrode 113.degree. 11b on the lower surface, similar to the conventional example described above. Aj! on the ceramic substrate 12 in advance! A predetermined wiring pattern 14 is formed by, for example, a predetermined wiring pattern 14, and a flip chip 10 is connected to a predetermined position of the wiring pattern 14 by a solder reflow method or a thermocompression bonding method. The flip chip 10 is made of a resin 13 that has good thermal conductivity and good adhesion to metal.
The metal base substrate 15 is fixed on top of the resin 13 before it hardens. Metal base substrate 15
A metal base 16 is formed on the bottom surface, and a wiring pattern 18 made of a predetermined metal portion is formed on the top thereof with an insulating surface 17 interposed therebetween. Chip components 19 and 20 such as capacitors, coils, and resistors are mounted in advance on the wiring pattern 18 on the upper surface of the metal base substrate 15. Then, the wiring pattern 18 of the metal base substrate 15 and the wiring pattern 14 of the ceramic substrate 12 are connected at an arbitrary position via the lead wire 21 to form a hybrid integrated circuit.

こうして構成された混成集積回路を動作させればフリッ
プチップＩＯで生じる熱は樹脂１３及び金属ベース基板
１５に容易に伝導して放熱することができる。従って金
属ベース基板１５は上面にチップ部品を実装する基板で
あり、同時にフリップチップを放熱させる放熱板として
作用している。When the hybrid integrated circuit configured in this manner is operated, the heat generated by the flip-chip IO can be easily conducted to the resin 13 and the metal base substrate 15 and radiated. Therefore, the metal base substrate 15 is a substrate on which chip components are mounted, and at the same time functions as a heat sink for dissipating heat from the flip chip.

尚本実施例はフリップチップとしてチップＩＣについて
説明しているが、他の半導体素子や抵抗。Although this embodiment describes a chip IC as a flip chip, other semiconductor elements or resistors may also be used.

コンデンサ等のチップ素子であっても同様に本発明を適
用することができることはいうまでもない。It goes without saying that the present invention can be similarly applied to chip elements such as capacitors.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例による混成集積回路を示す断
面図、第２図及び第３図は従来の混成集積回路の一例を
示す断面図である。 １　、　１０−−−−−−−フリップチップ　　２．１
２・−・−・セラミック基板　　３　、　１１　ａ　、
　　１　ｌ　ｂ−−−−−−−−突起電極　　４，１４
．１ＥＩ−・・・・−配線パターン　　６゜７．１９．
２０・・・・−・−チップ部品　　１３−・−・−樹脂
１５−・−・−・金属ベース基板　　２１−−−−−−
−−・リード線第２図 第３図FIG. 1 is a sectional view showing a hybrid integrated circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing an example of a conventional hybrid integrated circuit. 1, 10---Flip chip 2.1
2.--Ceramic substrate 3, 11a,
1 l b------Protruding electrode 4,14
．． 1EI-...-Wiring pattern 6゜7.19.
20...--Chip parts 13---Resin 15---Metal base board 21--
--・Lead wire Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] （１）一面に複数の電極を有しこの電極を基板にフェー
スダウンボンディングして固定されたフリップチップと
、 前記フリップチップを被う高熱伝導性の樹脂と、上面に
所定の配線パターンを有しチップ部品が実装され前記樹
脂上に設けられた金属ベース基板と、 前記金属ベース基板及び前記基板を接続するリード線と
、を有することを特徴とする混成集積回路装置。(1) A flip chip having a plurality of electrodes on one side and fixed to the substrate by face-down bonding, a highly thermally conductive resin covering the flip chip, and a predetermined wiring pattern on the top surface. A hybrid integrated circuit device comprising: a metal base substrate on which chip components are mounted and provided on the resin; and lead wires connecting the metal base substrate and the substrate.
JP61094287A 1986-04-23 1986-04-23 Hybrid integrated circuit device Pending JPS62250648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61094287A JPS62250648A (en) 1986-04-23 1986-04-23 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61094287A JPS62250648A (en) 1986-04-23 1986-04-23 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62250648A true JPS62250648A (en) 1987-10-31

Family

ID=14106043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61094287A Pending JPS62250648A (en) 1986-04-23 1986-04-23 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62250648A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure

Similar Documents

Publication Publication Date Title
US5583377A (en) Pad array semiconductor device having a heat sink with die receiving cavity
EP1374305B1 (en) Enhanced die-down ball grid array and method for making the same
JP4729244B2 (en) Non-mold package for semiconductor devices
US6933612B2 (en) Semiconductor device with improved heatsink structure
TWI235469B (en) Thermally enhanced semiconductor package with EMI shielding
JP4493121B2 (en) Semiconductor device and semiconductor chip packaging method
KR101391924B1 (en) Semiconductor package
JPH0964099A (en) Semiconductor device and its mounting structure
US7361995B2 (en) Molded high density electronic packaging structure for high performance applications
JP2708309B2 (en) Multi-chip type semiconductor device
JPH05275580A (en) Semiconductor device
JP2003258165A (en) Semiconductor device
US6963129B1 (en) Multi-chip package having a contiguous heat spreader assembly
JPH05211256A (en) Semiconductor device
JPS62250648A (en) Hybrid integrated circuit device
JPH09213847A (en) Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith
JP2810130B2 (en) Semiconductor package
JPH06132441A (en) Resin-sealed semiconductor device and manufacture thereof
JPS62150837A (en) Semiconductor device
JP2690248B2 (en) Surface mount type semiconductor device
JP2564645Y2 (en) Hybrid integrated circuit device having heat-generating components
JP2907187B2 (en) Bare chip mounting method and semiconductor integrated circuit device
JPH05343607A (en) Hybrid integrated circuit device
JPS63284831A (en) Manufacture of hybrid integrated circuit
JPH04144162A (en) Semiconductor device