JP2907187B2 - Bare chip mounting method and semiconductor integrated circuit device - Google Patents

Bare chip mounting method and semiconductor integrated circuit device

Info

Publication number
JP2907187B2
JP2907187B2 JP9134851A JP13485197A JP2907187B2 JP 2907187 B2 JP2907187 B2 JP 2907187B2 JP 9134851 A JP9134851 A JP 9134851A JP 13485197 A JP13485197 A JP 13485197A JP 2907187 B2 JP2907187 B2 JP 2907187B2
Authority
JP
Japan
Prior art keywords
bare chip
semiconductor
dielectric substrate
semiconductor bare
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9134851A
Other languages
Japanese (ja)
Other versions
JPH10326852A (en
Inventor
靖 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9134851A priority Critical patent/JP2907187B2/en
Publication of JPH10326852A publication Critical patent/JPH10326852A/en
Application granted granted Critical
Publication of JP2907187B2 publication Critical patent/JP2907187B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体ベアチップを
フリップチップ実装するためのベアチップ実装方法とこ
のベアチップ実装方法を用いて製造する半導体集積回路
装置に関する。
The present invention relates to a bare chip mounting method for flip-chip mounting a semiconductor bare chip and a semiconductor integrated circuit device manufactured by using the bare chip mounting method.

【0002】[0002]

【従来の技術】図3は、従来のベアチップ実装方法を説
明するためのものである。半導体ベアチップ11は、電
気絶縁性の樹脂12によって誘電体基板13へ実装され
る。半導体ベアチップのパッドに形成した微細なはんだ
端子としてのバンプ14がこの状態で誘電体基板13の
対応する箇所に接続されることになる。
2. Description of the Related Art FIG. 3 illustrates a conventional method of mounting a bare chip. The semiconductor bare chip 11 is mounted on a dielectric substrate 13 with an electrically insulating resin 12. The bumps 14 as fine solder terminals formed on the pads of the semiconductor bare chip are connected to the corresponding portions of the dielectric substrate 13 in this state.

【0003】半導体集積回路装置の回路動作の高速化や
回路機能の向上に伴って、回路装置の集積度が一段と高
まり、消費電力ならびに発熱がますます増大している。
図3に示したベアチップ実装方法では、半導体ベアチッ
プ11上で発生した熱がバンプ14のみを介して誘電体
基板13へ伝達される。したがって、十分な放熱特性を
得ることができないという問題が生じてしまう。
[0003] With the increase in the speed of circuit operation and the improvement of circuit functions of a semiconductor integrated circuit device, the degree of integration of the circuit device is further increased, and power consumption and heat generation are further increasing.
In the bare chip mounting method shown in FIG. 3, heat generated on the semiconductor bare chip 11 is transmitted to the dielectric substrate 13 via only the bumps 14. Therefore, there arises a problem that sufficient heat radiation characteristics cannot be obtained.

【0004】図4は、このような問題を解決するものと
して提案されたベアチップ実装方法を説明するためのも
のである。この方法では、配線基板21に枠状の部材2
2を銀ろう付け等によって固着し、キャビティ状の空間
を形成するようにしている。放熱スタッド23を接合部
材24によって固着した集積回路チップ25は、はんだ
バンプ26を介して配線基板21に接続されている。ま
た、枠状の部材22と放熱スタッド23の間には、集積
回路チップ25、配線基板21の表面を完全に覆うよう
にして、封止用の電気絶縁性樹脂27が充填されてい
る。電気絶縁性樹脂27の上部には、低融点金属28の
被膜が形成されている。
FIG. 4 illustrates a bare chip mounting method proposed to solve such a problem. In this method, the frame-shaped member 2
2 is fixed by silver brazing or the like so as to form a cavity-like space. The integrated circuit chip 25 to which the heat radiation stud 23 is fixed by the joining member 24 is connected to the wiring board 21 via the solder bump 26. The space between the frame-shaped member 22 and the heat radiation stud 23 is filled with an electric insulating resin 27 for sealing so as to completely cover the surfaces of the integrated circuit chip 25 and the wiring board 21. On the upper part of the electrically insulating resin 27, a coating of a low melting point metal 28 is formed.

【0005】ここで、集積回路チップ25の電気信号
は、はんだバンプ26、配線基板21内部のスルーホー
ル31を介してキップキャリアの外部へ導かれ、はんだ
接合部32により配線基板33に接続されるようになっ
ている。また、集積回路チップ25で生じる熱は、放熱
スタッド23を介してこれに固着または圧接する図示し
ないヒートシンクで吸収されるようになっている。
Here, the electric signal of the integrated circuit chip 25 is guided to the outside of the chip carrier through the solder bump 26 and the through hole 31 inside the wiring board 21, and is connected to the wiring board 33 by the solder joint 32. It has become. Further, heat generated in the integrated circuit chip 25 is absorbed by a heat sink (not shown) fixed or pressed against the heat sink via the heat radiation stud 23.

【0006】[0006]

【発明が解決しようとする課題】図3あるいは図4に示
したベアチップ実装方法あるいはこの方法により製造さ
れた半導体集積回路装置によれば、半導体ベアチップ、
すなわち集積回路チップ25の実装のみでは良好な放熱
特性を得ることはできない。これは図3で説明したと同
様に半導体ベアチップだけでは放熱の経路がはんだバン
プ26のみとなるからである。そこで図4に示したよう
に集積回路チップ25の裏面に放熱スタッド23を使用
してこれに放熱材を取り付けることが提案されている。
しかしながら、この方法では放熱スタッド23ならびに
ヒートシンクのような放熱材が半導体ベアチップに重ね
るようにして取り付けられるので、モジュール全体とし
ての高さがかさばるといった問題があった。
According to the bare chip mounting method shown in FIG. 3 or FIG. 4 or the semiconductor integrated circuit device manufactured by this method, a semiconductor bare chip,
That is, good heat radiation characteristics cannot be obtained only by mounting the integrated circuit chip 25. This is because, as described with reference to FIG. 3, only the semiconductor bare chip has a heat radiation path of only the solder bump 26. Therefore, it has been proposed to use a heat radiating stud 23 on the back surface of the integrated circuit chip 25 and attach a heat radiating material thereto, as shown in FIG.
However, in this method, since the heat dissipating material such as the heat dissipating stud 23 and the heat sink is mounted on the semiconductor bare chip so as to overlap, there is a problem that the height of the entire module is bulky.

【0007】そこで本発明の目的は、半導体ベアチップ
の裏面に放熱材を取り付けることなく良好な放熱特性を
持つことのできるベアチップ実装方法およびこの方法を
使用した半導体集積回路装置を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a bare chip mounting method capable of providing good heat radiation characteristics without attaching a heat radiating material to the back surface of a semiconductor bare chip, and a semiconductor integrated circuit device using this method.

【0008】[0008]

【課題を解決するための手段】請求項1記載の発明で
は、(イ)平板状の半導体ベアチップの側面のみを取り
囲むようにこの半導体ベアチップと同一の厚さで半導体
ベアチップの延長された位置に、良熱伝導性の接着剤を
介して良熱伝導性の枠状部材を取り付ける第1の工程
と、(ロ)枠状部材との間に良熱伝導性の材料を介在さ
せるようにして誘電体基板に半導体ベアチップをフリッ
プチップ実装する第2の工程とをベアチップ実装方法に
具備させる。
According to the first aspect of the present invention, there is provided a semiconductor device having the same thickness as a semiconductor bare chip so as to surround only a side surface of the flat semiconductor bare chip.
Apply a good heat conductive adhesive to the extended position of the bare chip.
(B) flip chip mounting of a bare semiconductor chip on a dielectric substrate such that a material having good heat conductivity is interposed between the first step of attaching a frame member having good heat conductivity through the first step; And the second step to be performed are provided in the bare chip mounting method.

【0009】すなわち請求項1記載の発明では、半導体
ベアチップの側面にのみ良熱伝導性の接着剤を介して、
第1の工程で良熱伝導性の枠状部材を取り付け、誘電体
基板と枠状部材の間に第2の工程で良熱伝導性の材料を
介在させることにより、誘電体基板側への放熱効果を高
め、半導体ベアチップの裏面に放熱材を取り付ける必要
を無くすことにしている。
That is, according to the first aspect of the present invention, only the side surface of the semiconductor bare chip is interposed with a good heat conductive adhesive.
In the first step, a frame member having good heat conductivity is attached, and in the second step, a material having good heat conductivity is interposed between the dielectric substrate and the frame member, thereby radiating heat to the dielectric substrate side. The effect is enhanced, and the need to attach a heat radiator to the back surface of the semiconductor bare chip is eliminated.

【0010】請求項2記載の発明では、(イ)平板状の
半導体ベアチップと、(ロ)この平板状の半導体ベアチ
ップの側面のみを取り囲むようにこの半導体ベアチップ
と同一の厚さで半導体ベアチップの延長された位置に、
良熱伝導性の接着剤を介して取り付けられた良熱伝導性
の枠状部材と、(ハ)この枠状部材との間に良熱伝導性
の材料を介在させるようにして半導体ベアチップをフリ
ップチップ実装する誘電体基板とを半導体集積回路装置
に具備させる。
According to the second aspect of the present invention, (a) the flat plate-shaped semiconductor bare chip and (b) the semiconductor bare chip so as to surround only the side surface of the flat-shaped semiconductor bare chip.
In the extended position of the semiconductor bare chip with the same thickness as
(C) good thermal conductivity between the frame-like member attached via a good thermal conductive adhesive and this frame-like member ;
Semiconductor bare chip so that the material of
And a dielectric substrate to be mounted on a chip .

【0011】すなわち請求項2記載の発明では、半導体
ベアチップの側面にのみ良熱伝導性の接着剤を介して、
取り付けられた良熱伝導性の枠状部材から良熱伝導性の
材料を介して誘電体基板に放熱を行わせるようにして、
半導体ベアチップの裏面に放熱材を取り付ける必要を無
くすことにしている。
That is, according to the second aspect of the present invention, only the side surface of the semiconductor bare chip is provided with an adhesive having good heat conductivity,
By letting the dielectric substrate radiate heat from the attached frame member with good heat conductivity through the material with good heat conductivity,
The need to attach a heat radiator to the back surface of the semiconductor bare chip is eliminated.

【0012】請求項3記載の発明では、半導体ベアチッ
プおよび枠状部材には誘電体基板と対向する面にそれぞ
れ熱伝導性に優れた金製のバンプが形成されていること
を特徴としている。バンプとしては、はんだバンプのよ
うに他の導電性の材料でもよいが、金を使用することで
放熱特性も良好となる。
According to a third aspect of the present invention, the semiconductor bare chip and the frame-shaped member are formed with gold bumps having excellent thermal conductivity on the surfaces facing the dielectric substrate. As the bump, another conductive material such as a solder bump may be used. However, the use of gold improves the heat radiation characteristics.

【0013】請求項4記載の発明では、半導体ベアチッ
プには誘電体基板と対向する面に金製のバンプが形成さ
れており、枠状部材と誘電体基板の間隙には銀ペースト
が充填されていることを特徴としている。枠状部材は、
このようにバンプを形成する代わりに熱の伝導性に優れ
た材料を充填することでも同様に放熱効果を高めること
ができる。
According to the fourth aspect of the present invention, the semiconductor bare chip has gold bumps formed on the surface facing the dielectric substrate, and the gap between the frame member and the dielectric substrate is filled with silver paste. It is characterized by having. The frame member is
By filling a material having excellent heat conductivity instead of forming the bumps, the heat radiation effect can be similarly increased.

【0014】[0014]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

【0015】[0015]

【実施例】以下実施例につき本発明を詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

【0016】第1の実施例 First Embodiment

【0017】図1は本発明の第1の実施例におけるベア
チップ実装方法を表わしたものである。第1の実施例の
半導体ベアチップ101の周囲には、良熱伝導性の接着
剤102を介して同じく良熱伝導性の枠状部材103が
取り付けられている。ここで接着剤102は、エポキシ
系の樹脂であり、枠状部材103はアルミニウム材であ
る。接着剤102は金属粒等をフィラーとして添加され
ているとなお良い。本実施例では半導体ベアチップ10
1が6mm角のサイズであり、枠状部材103は内寸法
が6.5mm角で外寸法が9mm角の形状のものを使用
している。
FIG. 1 shows a bare chip mounting method according to a first embodiment of the present invention. A frame member 103 having good heat conductivity is attached around a semiconductor bare chip 101 of the first embodiment via an adhesive 102 having good heat conductivity. Here, the adhesive 102 is an epoxy resin, and the frame member 103 is an aluminum material. The adhesive 102 is more preferably added with metal particles or the like as a filler. In this embodiment, the semiconductor bare chip 10
1 is a size of 6 mm square, and the frame-shaped member 103 has an inner size of 6.5 mm square and an outer size of 9 mm square.

【0018】半導体ベアチップ101の回路面上の電極
の上には高さが50μmの金からなる第1のバンプ10
1 が形成されており、枠状部材103の上には同じく
高さが50μmの金からなる第2のバンプ1042 が形
成されている。第1のバンプ1041 は、アルミナから
なる誘電体基板105のランドに接続されている。第2
のバンプ1042 は、この誘電体基板105の枠状部材
103接続用に配置された導電性のパターンに接続され
ている。また、半導体ベアチップ101、枠状部材10
3および誘電体基板105の間を封止するようにして、
エポキシ系の電気絶縁性の樹脂106が充填されてい
る。誘電体基板105は、これ以外にも一般に使用され
ている回路基板の材料を使用することができる。例え
ば、ガラスエポキシ、ポリイミド、テフロン等の樹脂系
の材料や、ガラスセラミック等の一般に電子回路用基板
に使用されている材料の使用が可能である。
The first bumps 10 made of gold having a height of 50 μm are formed on the electrodes on the circuit surface of the semiconductor bare chip 101.
4 1 are formed, a second bump 104 2 similarly height consists 50μm gold on top of the frame member 103 is formed. The first bump 104 1 is connected to a land of a dielectric substrate 105 made of alumina. Second
The bumps 104 2 are connected to a conductive pattern arranged for connection of the frame-shaped member 103 of the dielectric substrate 105. In addition, the semiconductor bare chip 101, the frame-shaped member 10
3 and the dielectric substrate 105 so as to be sealed.
An epoxy-based electrically insulating resin 106 is filled. For the dielectric substrate 105, other commonly used materials for circuit boards can be used. For example, resin-based materials such as glass epoxy, polyimide, and Teflon, and materials generally used for electronic circuit boards, such as glass ceramic, can be used.

【0019】このような実装方法で製作された半導体集
積回路装置で、半導体ベアチップ101へ電源が供給さ
れるとその回路面に発生した熱は第1のバンプ1041
を介して誘電体基板105へ放熱される他、側面の接着
剤102を介して枠状部材103に伝達する。そして、
枠状部材103から外部および第2のバンプ1042
介して更に誘電体基板105へと放熱され、これら相互
の放熱経路によって放熱特性を向上させることができ
る。
In the semiconductor integrated circuit device manufactured by such a mounting method, when power is supplied to the semiconductor bare chip 101, the heat generated on the circuit surface thereof generates the first bump 104 1.
The heat is dissipated to the dielectric substrate 105 via the side surface, and is transmitted to the frame member 103 via the adhesive 102 on the side surface. And
The heat is further radiated from the frame-shaped member 103 to the dielectric substrate 105 through the outside and the second bumps 104 2 , and the heat radiating characteristics can be improved by these mutual heat radiating paths.

【0020】このように半導体ベアチップ101に枠状
部材103が取り付けられ、この枠状部材103が第2
のバンプ1042 を介して誘電体基板105と接続され
たことにより、半導体ベアチップ101の放熱性が良好
となり、半導体集積回路を安定して動作させることがで
きる。しかも、図4で示したように半導体ベアチップ1
01の裏面に放熱材を取り付ける必要がなくなるので、
モジュール全体を低背型にすることができる。なお、本
実施例では第1および第2のバンプ1041 、1042
を全く同一サイズのバンプとしたが、第2のバンプ10
2 を半導体ベアチップ101や誘電体基板105との
接触面積のより広いバンプとしてもよいことは当然であ
る。
In this manner, the frame-shaped member 103 is attached to the semiconductor bare chip 101, and the frame-shaped member 103 is
By being connected to the dielectric substrate 105 via a bump 104 2, heat radiation of the semiconductor bare chip 101 is improved, the semiconductor integrated circuit can be stably operated. Moreover, as shown in FIG.
Since there is no need to attach a heat radiator to the back of 01,
The whole module can be made low profile. In this embodiment, the first and second bumps 104 1 , 104 2
Are exactly the same size, but the second bump 10
4 2 may be used as the wider bump contact area between the semiconductor bare chip 101 and the dielectric substrate 105 that is natural.

【0021】第2の実施例 Second Embodiment

【0022】図2は、本発明の第2の実施例におけるベ
アチップ実装方法を表わしたものである。図2で図1と
同一部分には同一の符号を付しており、これらの説明を
適宜省略する。この第2の実施例では、半導体ベアチッ
プ101の側面に接着剤102を介して取り付けられた
枠状部材103の下面と誘電体基板105の対応する部
位との間隙に、良熱伝導性のエポキシ系の接着剤121
を充填している。接着剤121は、必ずしも絶縁性の良
好なものである必要がない。したがって、エポキシ系の
接着剤121の代わりに、例えば銀ペースト等の導電性
接着剤を使用することも可能である。
FIG. 2 shows a bare chip mounting method according to a second embodiment of the present invention. In FIG. 2, the same portions as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In the second embodiment, the gap between the lower surface of the frame-like member 103 attached to the side surface of the semiconductor bare chip 101 via the adhesive 102 and the corresponding portion of the dielectric substrate 105 is made of a good heat conductive epoxy-based material. Adhesive 121
Is filled. The adhesive 121 does not necessarily have to have good insulating properties. Therefore, instead of the epoxy adhesive 121, for example, a conductive adhesive such as a silver paste can be used.

【0023】以上説明した第1の実施例における第1お
よび第2のパンプならびに第2の実施例における第1の
バンプに金を使用したが、放熱の状態によっては、これ
以外の金属あるいは合金のバンプ、例えばはんだバンプ
を使用することも可能である。枠状部材についても、第
1および第2の実施例でアルミニウムを使用したが、か
わりに銅、銅タングステン等の良熱伝導性の金属や窒化
アルミニウム等の良熱伝導性のセラミック型材料を使用
することも可能である。枠状部材は、半導体ベアチップ
にあわせて製作されるが、内寸法と外寸法の間隔は一定
ではなく、外寸法はできる限り大きくとれる方がよい。
Although gold was used for the first and second pumps in the first embodiment and the first bump in the second embodiment described above, depending on the state of heat radiation, other metals or alloys may be used. It is also possible to use bumps, for example solder bumps. As for the frame member, aluminum was used in the first and second embodiments. Instead, a metal having good heat conductivity such as copper or copper tungsten or a ceramic material having good heat conductivity such as aluminum nitride was used. It is also possible. Although the frame-shaped member is manufactured according to the semiconductor bare chip, the interval between the inner and outer dimensions is not constant, and the outer dimension should be as large as possible.

【0024】[0024]

【発明の効果】以上説明したように請求項1および請求
項2記載の発明によれば、平板状の半導体ベアチップの
側面のみを取り囲むようにこの半導体ベアチップと同一
の厚さで半導体ベアチップの延長された位置に、良熱伝
導性の枠状部材を取り付けることにした。このように、
誘電体基板と反対側の半導体ベアチップ面には放熱用の
部材を取り付けないので、モジュール全体を低背型とす
ることができ、半導体集積回路装置の高密度化を達成す
ることができる。また、半導体ベアチップの側面と良熱
伝導性の枠状部材は良熱伝導性の接着剤によって取り付
けられているばかりでなく、枠状部材と誘電体基板の間
にも良熱伝導性の材料が介在しているので、良好な放熱
特性を得ることができるという効果がある。
As described above, claims 1 and 2
According to the invention described in Item 2 , the semiconductor bare chip is the same as the semiconductor bare chip so as to surround only the side surface of the semiconductor bare chip.
Good heat transfer to the extended position of the semiconductor bare chip
We decided to attach a conductive frame. in this way,
On the semiconductor bare chip surface opposite to the dielectric substrate,
Since no members are attached, the entire module is low profile.
And a higher density of the semiconductor integrated circuit device can be achieved. Also, the side of the semiconductor bare chip and good heat
Conductive frame members are attached with a good thermal conductive adhesive
Not only between the frame-shaped member and the dielectric substrate
Good heat dissipation due to high thermal conductivity material
There is an effect that characteristics can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例におけるベアチップ実装
状態を表わした断面図である。
FIG. 1 is a sectional view showing a bare chip mounting state according to a first embodiment of the present invention.

【図2】本発明の第2の実施例におけるベアチップ実装
状態を表わした断面図である。
FIG. 2 is a sectional view illustrating a bare chip mounting state according to a second embodiment of the present invention.

【図3】従来のベアチップ実装状態を表わした断面図で
ある。
FIG. 3 is a cross-sectional view illustrating a conventional bare chip mounting state.

【図4】従来提案されたベアチップ実装状態を表わした
断面図である。
FIG. 4 is a cross-sectional view showing a conventionally proposed bare chip mounting state.

【符号の説明】[Explanation of symbols]

101 半導体ベアチップ 102 接着剤 103 枠状部材 1041 第1のバンプ 1042 第2のバンプ 105 誘電体基板 106 電気絶縁性の樹脂 121 エポキシ系の接着剤Reference Signs List 101 semiconductor bare chip 102 adhesive 103 frame-shaped member 104 1 first bump 104 2 second bump 105 dielectric substrate 106 electrically insulating resin 121 epoxy-based adhesive

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 平板状の半導体ベアチップの側面のみ
取り囲むようにこの半導体ベアチップと同一の厚さで半
導体ベアチップの延長された位置に、良熱伝導性の接着
剤を介して良熱伝導性の枠状部材を取り付ける第1の工
程と、 枠状部材との間に良熱伝導性の材料を介在させるように
して誘電体基板に半導体ベアチップをフリップチップ実
装する第2の工程とを具備することを特徴とするベアチ
ップ実装方法。
1. A semiconductor chip having a thickness equal to that of a semiconductor bare chip so as to surround only a side surface of the semiconductor bare chip.
Good thermal conductivity bonding to the extended position of the conductor bare chip
A first step of mounting a frame member having good thermal conductivity via an agent, and flip-chip mounting a semiconductor bare chip on a dielectric substrate such that a material having good thermal conductivity is interposed between the frame member and the frame member. A bare chip mounting method, comprising: a second step.
【請求項2】 平板状の半導体ベアチップと、 この平板状の半導体ベアチップの側面のみを取り囲むよ
うにこの半導体ベアチップと同一の厚さで半導体ベアチ
ップの延長された位置に、良熱伝導性の接着剤を介して
取り付けられた良熱伝導性の枠状部材と、この枠状部材との間に良熱伝導性の材料を介在させるよ
うにして半導体ベアチップをフリップチップ実装する
電体基板とを具備することを特徴とする半導体集積回路
装置。
2. A plate-shaped semiconductor bare chip and a semiconductor Beachi in the flat plate-like semiconductor side only the same thickness as the semiconductor bare chip so as to surround of a bare chip
To the extended position of the
A good heat conductive material is interposed between the attached good heat conductive frame member and the frame member.
And a dielectric substrate on which the semiconductor bare chip is flip-chip mounted .
【請求項3】 前記半導体ベアチップおよび枠状部材に
は前記誘電体基板と対向する面にそれぞれ金製のバンプ
が形成されていることを特徴とする請求項2記載の半導
体集積回路装置。
3. The semiconductor integrated circuit device according to claim 2, wherein a gold bump is formed on each of the semiconductor bare chip and the frame-shaped member on a surface facing the dielectric substrate.
【請求項4】 前記半導体ベアチップには前記誘電体基
板と対向する面に金製のバンプが形成されており、枠状
部材と誘電体基板の間隙には銀ペーストが充填されてい
ることを特徴とする請求項2記載の半導体集積回路装
置。
4. The semiconductor bare chip has a gold bump formed on a surface facing the dielectric substrate, and a gap between the frame-shaped member and the dielectric substrate is filled with a silver paste. 3. The semiconductor integrated circuit device according to claim 2, wherein
JP9134851A 1997-05-26 1997-05-26 Bare chip mounting method and semiconductor integrated circuit device Expired - Lifetime JP2907187B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9134851A JP2907187B2 (en) 1997-05-26 1997-05-26 Bare chip mounting method and semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9134851A JP2907187B2 (en) 1997-05-26 1997-05-26 Bare chip mounting method and semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH10326852A JPH10326852A (en) 1998-12-08
JP2907187B2 true JP2907187B2 (en) 1999-06-21

Family

ID=15137961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9134851A Expired - Lifetime JP2907187B2 (en) 1997-05-26 1997-05-26 Bare chip mounting method and semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2907187B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012609A (en) 1998-06-17 2000-01-14 Shinko Electric Ind Co Ltd Method of mounting semiconductor chip on circuit board
JP3813079B2 (en) 2001-10-11 2006-08-23 沖電気工業株式会社 Chip size package
JP2004327951A (en) * 2003-03-06 2004-11-18 Shinko Electric Ind Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH10326852A (en) 1998-12-08

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