JPH08162575A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH08162575A JPH08162575A JP30334794A JP30334794A JPH08162575A JP H08162575 A JPH08162575 A JP H08162575A JP 30334794 A JP30334794 A JP 30334794A JP 30334794 A JP30334794 A JP 30334794A JP H08162575 A JPH08162575 A JP H08162575A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- semiconductor
- semiconductor device
- bump electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置およびその
製造方法に関し、特に、半導体チップよりの熱を効率良
く放熱することのできる技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique capable of efficiently radiating heat from a semiconductor chip.
【０００２】[0002]
【従来の技術】従来、半導体装置におけるオンパック
（ＯＭＰＡＣ）実装技術は、一般に、多層配線基板に半
導体チップをフェース・アップですなわち信号の入出力
端子部（電極部）が上側になるように固着させ、当該チ
ップの電極部と当該多層配線基板上の配線とを金線など
のワイヤーで電気的に接続する所謂ワイヤーボンディン
グで電気的に接続し、樹脂（レジン）により当該チップ
やボンディングワイヤーを被覆してこれらを外的環境か
ら保護するという封止方法が採用されていた。2. Description of the Related Art Conventionally, in an on-pack (OMPAC) mounting technique for a semiconductor device, a semiconductor chip is generally fixed face-up on a multilayer wiring board, that is, a signal input / output terminal portion (electrode portion) is on an upper side. Then, the electrode portion of the chip and the wiring on the multilayer wiring board are electrically connected by a wire such as a gold wire, so-called wire bonding, and the chip and the bonding wire are covered with resin (resin). Then, the sealing method of protecting these from the external environment was adopted.
【０００３】尚、当該半導体装置について述べた文献の
例としては、例えば工業調査会発行「電子材料」１９８
２年９月号Ｐ４９〜５４、同１９８２年８月号Ｐ６９〜
７４および同１９８４年８月号Ｐ６８〜７３が挙げられ
る。Incidentally, as an example of a document describing the semiconductor device, for example, "Electronic Material" 198 issued by Industrial Research Society is published.
September 2 issue P49-54, August 1982 issue P69-
74 and August 1984, P68-73.
【０００４】[0004]
【発明が解決しようとする課題】しかるに、当該実装技
術では、半導体チップからの発熱が、それを被覆してい
るレジンを通して行われることになり、レジンはその熱
抵抗が高いので、高パワーの半導体素子を有するチップ
を実装することは困難であった。However, in the mounting technique, heat generated from the semiconductor chip is generated through the resin covering the semiconductor chip, and the resin has a high thermal resistance, so that the semiconductor of high power is used. It was difficult to mount a chip having an element.
【０００５】また、当該実装におけるワイヤーボンディ
ングは、電極数の増加に伴いピッチも狭くなってワイヤ
ー間の短絡などを生じ多ピン化への対応において無理を
生じてきている。Further, in the wire bonding in the mounting, the pitch becomes narrower as the number of electrodes increases, and short-circuiting between wires occurs, which makes it difficult to cope with a large number of pins.
【０００６】本発明は、上記問題点を解決することを目
的とする。An object of the present invention is to solve the above problems.
【０００７】本発明の前記ならびにそのほかの目的と新
規な特徴は、本明細書の記述および添付図面からあきら
かになるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【０００９】上記目的を達成するため、本発明では、半
導体チップをそのバンプ電極と称される突起電極を介し
て実装用基板上にフリップチップ実装し、当該チップの
裏面に直接ヒートシンクなどの放熱器を取付けするよう
にしたものである。In order to achieve the above object, according to the present invention, a semiconductor chip is flip-chip mounted on a mounting substrate via bump electrodes called bump electrodes, and a radiator such as a heat sink is directly mounted on the back surface of the chip. Is attached.
【００１０】[0010]
【作用】上記手段によれば、半導体チップからの発熱
は、直接、ヒートシンクなどの放熱器を通して放熱する
ことができるので、大型で高パワーの半導体素子を有す
るチップをＯＭＰＡＣ実装することができ、また、バン
プ電極による電気的接続をとるので、ワイヤーボンディ
ングにより生じる問題点を解消して多ピン化への対応に
おいても優れたものとすることができる。According to the above means, the heat generated from the semiconductor chip can be directly radiated through a radiator such as a heat sink, so that a chip having a large and high power semiconductor element can be mounted on the OMPAC. Since the bump electrodes are used for the electrical connection, the problems caused by the wire bonding can be eliminated, and the structure can be made excellent in dealing with the increase in the number of pins.
【００１１】[0011]
【実施例】以下、本発明の実施例を図面を参照しつつ説
明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１２】図１（Ａ）は、本発明の実施例を示す組立
後の半導体装置の要部構成図、同図（Ｂ）および（Ｃ）
は、それぞれ同半導体装置の製造工程の断面図、図１
（Ｄ）は、本発明の他の実施例を示す半導体装置の要部
構成図である。FIG. 1A is a schematic view of a main part of a semiconductor device after assembly showing an embodiment of the present invention, and FIGS. 1B and 1C.
1A and 1B are sectional views of the manufacturing process of the same semiconductor device, respectively.
(D) is a principal part block diagram of the semiconductor device which shows another Example of this invention.
【００１３】図１（Ｂ）に示すように、半導体チップ１
を、そのバンプ電極２を介して、多層配線基板３上にフ
リップチップ実装する。As shown in FIG. 1B, the semiconductor chip 1
Are flip-chip mounted on the multilayer wiring board 3 via the bump electrodes 2.
【００１４】当該半導体チップ１は、通常、素子表面上
の信号のＩ／０（入／出力）端子部に形成されたバンプ
電極２を上側にして製造される。従来例では、当該半導
体チップをフェース・アップで信号のＩ／０（入／出
力）が上側になるように多層配線基板に固着させ、当該
チップのパッド電極部と当該多層配線基板上の配線とを
ワイヤーボンディングにより電気的に接続していたので
あるが、本発明では、当該半導体チップ１にバンプ電極
２を形成して、当該半導体チップ１を裏返して、当該バ
ンプ電極２側を下側にして、当該バンプ電極２を多層配
線基板上に溶着させ、フリップチップ実装する。The semiconductor chip 1 is usually manufactured with the bump electrode 2 formed on the I / 0 (input / output) terminal portion of the signal on the surface of the element facing upward. In the conventional example, the semiconductor chip is fixed face-up to the multilayer wiring board so that the signal I / 0 (input / output) is on the upper side, and the pad electrode portion of the chip and the wiring on the multilayer wiring board are connected. In the present invention, the bump electrode 2 is formed on the semiconductor chip 1, the semiconductor chip 1 is turned over, and the bump electrode 2 side is turned downward. Then, the bump electrode 2 is welded on the multilayer wiring board and flip-chip mounted.
【００１５】上記半導体チップ１は、例えばシリコン単
結晶基板から成り、周知の技術によってその内部には多
数の回路素子が形成され、１つの回路機能が与えられて
いる。回路素子の具体例は、例えばＭＯＳトランジスタ
から成り、これらの回路素子によって、例えば論理回路
およびメモリの回路機能が形成されている。The semiconductor chip 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed in the inside by a well-known technique to provide one circuit function. A specific example of the circuit element includes, for example, a MOS transistor, and these circuit elements form a circuit function of a logic circuit and a memory, for example.
【００１６】バンプ電極２は、例えば、ＰｂーＳｎハン
ダ、Ａｕボール等よりなる。The bump electrode 2 is made of, for example, Pb-Sn solder or Au ball.
【００１７】多層配線基板３は、プリント配線基板ある
いはセラミック配線基板などにより構成されている。The multilayer wiring board 3 is composed of a printed wiring board, a ceramic wiring board, or the like.
【００１８】上記のように、半導体チップ１をＣＣＢ
（Ｃｏｎｔｒｏｌｌｅｄ Ｃｏｌｌａｐｓｅ Ｂｏｎｄ
ｉｎｇ）接続技術により多層配線基板３とバンプ電極２
を介して電気的に接続後、 図１（Ｃ）に示すように、
当該半導体チップ１の裏面に、直接、放熱器４を取付け
する。As described above, the semiconductor chip 1 is connected to the CCB
(Controlled Collapse Bond
ing) connection technology and multilayer wiring board 3 and bump electrodes 2
After being electrically connected via, as shown in FIG.
The radiator 4 is directly attached to the back surface of the semiconductor chip 1.
【００１９】放熱器４は、例えば、図示のような放熱用
ヒレが多数設けられた放熱フイン（ヒートシンク）によ
り構成されている。放熱器４は、例えば、金属、窒化ア
ルミニウム、炭化シリコン等からなる。The radiator 4 is composed of, for example, a radiation fin (heat sink) provided with a large number of fins for radiation as shown in the figure. The radiator 4 is made of, for example, metal, aluminum nitride, silicon carbide, or the like.
【００２０】次いで、図１（Ａ）に示すように、当該チ
ップ１と多層配線基板３との間を封止して、当該チップ
１やバンプ電極部２を外的環境から保護する。この実施
例では、これらチップ１と多層配線基板３との間に樹脂
５を充填することにより、バンプ電極２の接続部を被覆
し封止してなる例を示してある。Then, as shown in FIG. 1A, the space between the chip 1 and the multilayer wiring board 3 is sealed to protect the chip 1 and the bump electrode portion 2 from the external environment. In this embodiment, a resin 5 is filled between the chip 1 and the multilayer wiring board 3 to cover and seal the connection portion of the bump electrode 2.
【００２１】当該樹脂による封止は、例えばトランスフ
ァーモールドにより行うことができる。The sealing with the resin can be performed, for example, by transfer molding.
【００２２】こうして得られた半導体装置６は、半導体
チップ１からの発熱は、直接、ヒートシンク４を通して
放熱することができるので、大型で高パワーの半導体素
子を有するチップ１をＯＭＰＡＣ実装することができ、
また、バンプ電極２による電気的接続をとるので、ワイ
ヤーボンディングにより生じる問題点を解消して多ピン
化への対応においても優れたものとすることができる。In the semiconductor device 6 thus obtained, the heat generated from the semiconductor chip 1 can be directly radiated through the heat sink 4, so that the chip 1 having a large and high-power semiconductor element can be mounted on the OMPAC. ,
Further, since the bump electrodes 2 are electrically connected, the problems caused by the wire bonding can be eliminated, and it can be made excellent in dealing with the increase in the number of pins.
【００２３】図２（Ａ）〜（Ｃ）は、他の封止方法の例
を示してあり、同図（Ａ）は、ヒートシンク４の下部を
多層配線基板３の表面に固着させることができるように
延在させてキャップ状となし、当該キャップ状のヒート
シンク４により当該チップ１と多層配線基板３との間を
封止して、当該チップ１やバンプ電極部２を外的環境か
ら保護するようにしたものである。2A to 2C show an example of another sealing method. In FIG. 2A, the lower portion of the heat sink 4 can be fixed to the surface of the multilayer wiring board 3. Thus extending to form a cap shape, and the heat sink 4 in the cap shape seals between the chip 1 and the multilayer wiring board 3 to protect the chip 1 and the bump electrode portion 2 from the external environment. It was done like this.
【００２４】また、同図（Ｂ）は、ヒートシンク４の下
部に、封止用リング７を介在させ、当該チップ１と多層
配線基板３との間を封止して、当該チップ１やバンプ電
極部２を外的環境から保護するようにしたものである。In FIG. 1B, a sealing ring 7 is provided below the heat sink 4 to seal the space between the chip 1 and the multilayer wiring board 3 and the chip 1 and bump electrodes. It is intended to protect the part 2 from the external environment.
【００２５】さらに、同図（Ｃ）は、多層配線基板３上
に放熱脚部８を立脚して、当該放熱脚部８の天面と当該
チップ１とを接触させ、当該放熱脚部８の上にヒートシ
ンク４を取付けてなる実施例を示す。Further, in FIG. 2C, the heat dissipation leg 8 is erected on the multilayer wiring board 3 to bring the top surface of the heat dissipation leg 8 and the chip 1 into contact with each other, and An embodiment in which the heat sink 4 is attached is shown.
【００２６】これら半導体装置６によっても、半導体チ
ップ１からの発熱は、直接、ヒートシンク４などからな
る放熱器を通して放熱することができるので、大型で高
パワーの半導体素子を有するチップ１をＯＭＰＡＣ実装
することができ、また、バンプ電極２による電気的接続
をとるので、ワイヤーボンディングにより生じる問題点
を解消して多ピン化への対応においても優れたものとす
ることができる。With these semiconductor devices 6 as well, the heat generated from the semiconductor chip 1 can be directly radiated through a radiator composed of a heat sink 4, etc., so that the chip 1 having a large and high-power semiconductor element is mounted by OMPAC. Moreover, since the bump electrodes 2 are electrically connected, the problems caused by the wire bonding can be eliminated, and it is excellent in dealing with the increase in the number of pins.
【００２７】図１（Ｄ）は、本発明の他の実施例を示す
半導体装置の要部構成図で、当該チップ１を複数多層配
線基板３上に上記と同様にして固着させ、同様に当該チ
ップ１やバンプ電極部２を外的環境から保護してある。FIG. 1D is a main part configuration diagram of a semiconductor device showing another embodiment of the present invention, in which the chip 1 is fixed on the multi-layered wiring board 3 in the same manner as described above. The chip 1 and the bump electrode portion 2 are protected from the external environment.
【００２８】このようなマルチ・チップ・モジュール９
では、より一層発熱があり、したがって、本発明の構造
は、より一層放熱効果を発揮できる。Such a multi-chip module 9
Then, more heat is generated, and therefore, the structure of the present invention can exert more heat dissipation effect.
【００２９】図３は、図１（Ａ）に示すような半導体装
置５の多層配線基板３の下部にさらに上記と同様のバン
プ電極部１０を形成して、当該バンプ電極部１０を下側
にして配線基板１１上に実装する方法を示している。In FIG. 3, a bump electrode portion 10 similar to the above is further formed below the multilayer wiring substrate 3 of the semiconductor device 5 as shown in FIG. 1A, and the bump electrode portion 10 is placed on the lower side. The method of mounting on the wiring board 11 is shown.
【００３０】以上本発明者によってなされた発明を実施
例にもとずき具体的に説明したが、本発明は上記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
【００３１】[0031]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３２】本発明によれば、半導体チップからの発熱
は、直接、ヒートシンクなどの放熱器を通して放熱する
ことができるので、大型で高パワーの半導体素子を有す
るチップをＯＭＰＡＣ実装することができ、また、バン
プ電極による電気的接続をとるので、ワイヤーボンディ
ングにより生じる問題点を解消して多ピン化への対応に
おいても優れたものとすることができる。According to the present invention, the heat generated from the semiconductor chip can be directly radiated through a radiator such as a heat sink, so that a chip having a large-sized and high-power semiconductor element can be mounted on the OMPAC. Since the bump electrodes are used for the electrical connection, the problems caused by the wire bonding can be eliminated, and the structure can be made excellent in dealing with the increase in the number of pins.
【図１】図１（Ａ）は、本発明の実施例を示す組立後の
半導体装置の要部構成図、同図（Ｂ）および（Ｃ）は、
それぞれ同半導体装置の製造工程の断面図、図１（Ｄ）
は、本発明の他の実施例を示す半導体装置の要部構成図
である。FIG. 1A is a configuration diagram of a main part of a semiconductor device after assembly showing an embodiment of the present invention, and FIGS.
1D is a cross-sectional view of the manufacturing process of the same semiconductor device.
FIG. 6 is a configuration diagram of a main part of a semiconductor device showing another embodiment of the present invention.
【図２】図２（Ａ）〜（Ｃ）は、本発明の他の実施例を
示す半導体装置の要部構成図である。FIG. 2A to FIG. 2C are main part configuration diagrams of a semiconductor device showing another embodiment of the present invention.
【図３】図３は、図１の半導体装置の実装方法を示す略
断面図である。3 is a schematic cross-sectional view showing a method of mounting the semiconductor device of FIG.
１・・・半導体チップ ２・・・バンプ電極 ３・・・多層配線基板 ４・・・放熱器（ヒートシンク） ５・・・封止樹脂 ６・・・半導体装置 ７・・・封止用リング ８・・・放熱脚部 ９・・・マルチ・チップ・モジュール 10・・・バンプ電極部 11・・・配線基板 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Bump electrode 3 ... Multilayer wiring board 4 ... Radiator (heat sink) 5 ... Sealing resin 6 ... Semiconductor device 7 ... Sealing ring 8 ... Heat dissipation leg 9 ... Multi-chip module 10 ... Bump electrode section 11 ... Wiring board
───────────────────────────────────────────────────── フロントページの続き (72)発明者 船木 月夫 北海道亀田郡七飯町字中島145番地 日立 北海セミコンダクタ株式会社内 (72)発明者 宇田 隆之 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 佐藤 俊彦 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 林田 哲哉 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsukio Funaki 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Hokkai Semiconductor Co., Ltd. (72) Takayuki Uda 2326 Imai, Ome-shi, Tokyo Hitachi Development Co., Ltd. In the center (72) Inventor Toshihiko Sato 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Tetsuya Hayashida 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center
Claims (4)
の突起電極を介して固着し、前記半導体チップの前記突
起電極による接続側とは反対側の当該チップ表面に直接
放熱器を取付けし、前記半導体チップと前記実装用基板
との間を封止してなることを特徴とする半導体装置。1. A semiconductor chip is fixed on a mounting substrate via a protruding electrode of the chip, and a radiator is directly attached to the surface of the semiconductor chip opposite to the connection side of the protruding electrode of the semiconductor chip, A semiconductor device, wherein a space between the semiconductor chip and the mounting substrate is sealed.
導体チップと実装用基板との間に樹脂を充填することに
より封止してなることを特徴とする、請求項１に記載の
半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor chip and the mounting substrate are sealed by filling a resin between them. .
導体チップと実装用基板との間に封止用リングを介在さ
せることにより封止してなることを特徴とする、請求項
１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor chip is sealed by interposing a sealing ring between the semiconductor chip and the mounting substrate. Semiconductor device.
を裏返して当該チップの突起電極側を下側にして当該チ
ップを実装用基板上に電気的に接続後、当該チップの前
記突起電極による接続側とは反対側の当該チップ表面に
直接放熱器を取付けし、次いで、樹脂を充填することに
よりまたは封止用リングを介在させることにより当該チ
ップと前記実装用基板との間を封止してなることを特徴
とする半導体装置の製造方法。4. A semiconductor chip having a protruding electrode formed on an upper surface thereof is turned upside down to electrically connect the chip to a mounting substrate with the protruding electrode side of the chip facing downward, and then the protruding electrode of the chip is used. A radiator is directly attached to the surface of the chip on the side opposite to the connection side, and then the chip and the mounting board are sealed by filling with a resin or by interposing a sealing ring. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30334794A JPH08162575A (en) | 1994-12-07 | 1994-12-07 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30334794A JPH08162575A (en) | 1994-12-07 | 1994-12-07 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08162575A true JPH08162575A (en) | 1996-06-21 |
Family
ID=17919886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30334794A Pending JPH08162575A (en) | 1994-12-07 | 1994-12-07 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08162575A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001078138A1 (en) * | 2000-04-07 | 2001-10-18 | Advanced Micro Devices, Inc. | Flip chip semiconductor device including a compliant support for supporting a heat sink |
| FR2868877A1 (en) * | 2004-04-13 | 2005-10-14 | Intexys Sa | Semiconductor laser emitter has laser diode in stack with two heat dissipators for improved thermal properties |
| EP2251903A1 (en) * | 2009-05-14 | 2010-11-17 | Thomson Licensing, Inc. | Heat sink mounting method |
| JP2013105878A (en) * | 2011-11-14 | 2013-05-30 | Ibiden Co Ltd | Electronic component and manufacturing method of the same |
| CN109390293A (en) * | 2017-08-03 | 2019-02-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
| CN110634753A (en) * | 2019-09-25 | 2019-12-31 | 北京比特大陆科技有限公司 | Method for welding chip with radiator and PCB assembly |
-
1994
- 1994-12-07 JP JP30334794A patent/JPH08162575A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001078138A1 (en) * | 2000-04-07 | 2001-10-18 | Advanced Micro Devices, Inc. | Flip chip semiconductor device including a compliant support for supporting a heat sink |
| FR2868877A1 (en) * | 2004-04-13 | 2005-10-14 | Intexys Sa | Semiconductor laser emitter has laser diode in stack with two heat dissipators for improved thermal properties |
| EP2251903A1 (en) * | 2009-05-14 | 2010-11-17 | Thomson Licensing, Inc. | Heat sink mounting method |
| JP2013105878A (en) * | 2011-11-14 | 2013-05-30 | Ibiden Co Ltd | Electronic component and manufacturing method of the same |
| CN109390293A (en) * | 2017-08-03 | 2019-02-26 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
| CN109390293B (en) * | 2017-08-03 | 2023-01-24 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
| CN110634753A (en) * | 2019-09-25 | 2019-12-31 | 北京比特大陆科技有限公司 | Method for welding chip with radiator and PCB assembly |
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