JP2003060132A - Substrate structure, semiconductor device and manufacturing method therefor - Google Patents

Substrate structure, semiconductor device and manufacturing method therefor

Info

Publication number
JP2003060132A
JP2003060132A JP2001246902A JP2001246902A JP2003060132A JP 2003060132 A JP2003060132 A JP 2003060132A JP 2001246902 A JP2001246902 A JP 2001246902A JP 2001246902 A JP2001246902 A JP 2001246902A JP 2003060132 A JP2003060132 A JP 2003060132A
Authority
JP
Japan
Prior art keywords
bonding pad
radiation fin
die bonding
semiconductor element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001246902A
Other languages
Japanese (ja)
Inventor
Minoru Senda
実 仙田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2001246902A priority Critical patent/JP2003060132A/en
Publication of JP2003060132A publication Critical patent/JP2003060132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To solve the problem that effect of heat radiation is poor, since a heat radiation path from a semiconductor element to radiation fin contains a sealing resin. SOLUTION: A radiation fin attaching wiring 13 is so placed as to enclose surroundings of a die bonding pad 12 formed at a center part of a substrate 11, and connected to the die bonding pad 12; a radiation fin 18 has a leg part 17 of a shape, corresponding to the radiation fin attaching wiring 13; the leg part 17 is fixed to the radiation fin attaching wiring 13; and thereby heat is made to efficiently transmit from a semiconductor element 4, through the radiation fin attaching wiring 13 to the radiation fin 18.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の基板構
造・半導体装置及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device substrate structure, a semiconductor device, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】図5は従来の基板構造を示す平面図であ
る。
2. Description of the Related Art FIG. 5 is a plan view showing a conventional substrate structure.

【0003】基板1の中心部に半導体素子を搭載するた
めのダイボンディングパッド2を形成し、その外側にワ
イヤを接続するためのワイヤボンディングパッド3を形
成している。
A die bonding pad 2 for mounting a semiconductor element is formed in the center of a substrate 1, and a wire bonding pad 3 for connecting a wire is formed on the outside thereof.

【0004】図6は従来の半導体装置を示す断面図で、
図5に示した基板に半導体素子を搭載している。
FIG. 6 is a sectional view showing a conventional semiconductor device.
A semiconductor element is mounted on the substrate shown in FIG.

【0005】基板1のダイボンディングパッド2に半導
体素子4をダイボンディングし、半導体素子4の配線と
基板1の配線を電気的に接続するため、半導体素子4の
電極とワイヤボンディングパッド3とをワイヤ5により
ボンディングする。
The semiconductor element 4 is die-bonded to the die bonding pad 2 of the substrate 1 to electrically connect the wiring of the semiconductor element 4 and the wiring of the substrate 1. Therefore, the electrode of the semiconductor element 4 and the wire bonding pad 3 are wired. Bonding is done by 5.

【0006】半導体素子4やワイヤ5を保護するため、
封止樹脂6を基板1上に形成し、基板1の下面に半導体
装置の出力端子として例えば半田ボール7を接続する。
In order to protect the semiconductor element 4 and the wire 5,
The sealing resin 6 is formed on the substrate 1, and solder balls 7, for example, are connected to the lower surface of the substrate 1 as output terminals of the semiconductor device.

【0007】更に、半導体素子4から発する熱を逃すた
めに放熱フィン8を封止樹脂6の上に接着している。
Further, in order to dissipate the heat generated from the semiconductor element 4, a radiation fin 8 is adhered on the sealing resin 6.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
実装構造では、図7に従来技術の問題点を説明する断面
図を示したように、半導体素子4から放熱フィン8への
放熱経路は熱の流れAの矢印の通り封止樹脂6を介して
いる。
However, in the conventional mounting structure, as shown in FIG. 7 which is a sectional view for explaining the problems of the prior art, the heat dissipation path from the semiconductor element 4 to the heat dissipation fin 8 is As shown by the arrow of the flow A, it is through the sealing resin 6.

【0009】封止樹脂6にはエポキシ樹脂が一般に使用
されるが、エポキシ樹脂は表1に示すように熱伝導率が
小さく、半導体素子4から発する熱が効率よく放熱フィ
ン8に伝わらないという問題があった。
Epoxy resin is generally used as the sealing resin 6. However, as shown in Table 1, the epoxy resin has a small thermal conductivity, and the heat generated from the semiconductor element 4 is not efficiently transmitted to the radiation fin 8. was there.

【0010】[0010]

【表1】 そのため、半導体装置として良好な放熱効果が得られな
かった。
[Table 1] Therefore, a good heat dissipation effect cannot be obtained as a semiconductor device.

【0011】[0011]

【課題を解決するための手段】上記した課題を解決する
ため、本発明は基板構造として、ダイボンディングパッ
ドの周囲を囲むように配置され、ダイボンディングパッ
ドと接続された放熱フィン取付け配線を設けたものであ
る。
In order to solve the above problems, the present invention has a substrate structure provided with a radiation fin mounting wiring which is arranged so as to surround the periphery of a die bonding pad and is connected to the die bonding pad. It is a thing.

【0012】また、本発明は半導体装置として、半導体
素子とダイボンディングパッドの周囲を囲むように配置
され、ダイボンディングパッドと接続された放熱フィン
取付け配線を有する基板と放熱フィン取付け配線に対応
した形状の脚部を底面に形成し、放熱フィン取付け配線
に脚部を固着した放熱フィンとを備えたものである。
Further, the present invention is a semiconductor device, which is arranged so as to surround a semiconductor element and a die bonding pad, and has a shape corresponding to a substrate having a radiation fin mounting wiring connected to the die bonding pad and a radiation fin mounting wiring. The leg portions are formed on the bottom surface and the fins are fixed to the radiation fin mounting wiring.

【0013】[0013]

【発明の実施の形態】図1は本発明の実施形態である基
板構造を示す平面図である。なお、従来と同じ構成要素
にはすべての図において同じ符号を付してある。
1 is a plan view showing a substrate structure according to an embodiment of the present invention. It should be noted that the same components as those of the related art are denoted by the same reference numerals in all the drawings.

【0014】基板11の中心部に半導体素子を搭載する
ためのダイボンディングパッド12を形成し、その外側
に従来と同様にワイヤを接続するためのワイヤボンディ
ングパッド3を形成している。
A die bonding pad 12 for mounting a semiconductor element is formed in the center of a substrate 11, and a wire bonding pad 3 for connecting a wire is formed on the outside of the die bonding pad 12 as in the conventional case.

【0015】更に、その外側にダイボンディングパッド
12、ワイヤボンディングパッド3の周囲を囲むように
放熱フィン取付け配線13が形成されている。
Further, a radiation fin mounting wiring 13 is formed outside the die bonding pad 12 and the wire bonding pad 3 so as to surround them.

【0016】放熱フィン取付け配線13はダイボンディ
ングパッド12の4角14とブリッジ部15により接続
されている。ダイボンディングパッド12、放熱フィン
取付け配線13及びブリッジ部15は導電体パターンに
より同時に形成することができる。
The radiation fin mounting wiring 13 is connected to the four corners 14 of the die bonding pad 12 by the bridge portion 15. The die bonding pad 12, the radiation fin mounting wiring 13, and the bridge portion 15 can be simultaneously formed by a conductor pattern.

【0017】図2は本発明の実施形態の半導体装置を示
す断面図で、図1に示した基板に半導体素子を搭載して
いる。
FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention, in which a semiconductor element is mounted on the substrate shown in FIG.

【0018】基板11のダイボンディングパッド12に
半導体素子4をダイボンディングし、従来と同様に半導
体素子4の配線と基板11の配線を電気的に接続するた
め、半導体素子4の電極とワイヤボンディングパッド3
とをワイヤ5によりボンディングする。
The semiconductor element 4 is die-bonded to the die bonding pad 12 of the substrate 11 and the wiring of the semiconductor element 4 and the wiring of the substrate 11 are electrically connected in the same manner as in the conventional case. Three
And are bonded by the wire 5.

【0019】次に、基板11の下面に半導体装置の出力
端子として、例えば半田ボール7を接続する。
Next, solder balls 7, for example, are connected to the lower surface of the substrate 11 as output terminals of the semiconductor device.

【0020】更に、半導体素子4から発する熱を逃すた
めに、上方に複数のフィン部16を形成し、底面に脚部
17を形成した放熱フィン18を放熱フィン取付け配線
13に脚部17を位置合わせして導電体が混入された接
着剤で固着する。
Further, in order to dissipate the heat generated from the semiconductor element 4, a plurality of fin portions 16 are formed on the upper side, and a heat radiating fin 18 having a leg portion 17 formed on the bottom surface is disposed on the heat radiating fin mounting wiring 13 with the leg portion 17 positioned. It is also fixed with an adhesive containing a conductor.

【0021】図3は本発明の実施形態の放熱フィンを示
す斜視図で、脚部がわかるように下方から見た図であ
る。
FIG. 3 is a perspective view showing a heat radiation fin according to an embodiment of the present invention, and is a view seen from below so that the legs can be seen.

【0022】放熱フィン18の脚部17は茶碗の高台の
ように形成され、図1に示した放熱フィン取付け配線1
3の四角形に対応した形状をしており、放熱フィン取付
け配線13に接着することにより半導体素子4を封止し
て保護する作用をする。
The leg portions 17 of the heat radiation fin 18 are formed like a plate of a bowl, and the heat radiation fin mounting wiring 1 shown in FIG.
It has a shape corresponding to the quadrangle 3 and adheres to the radiation fin mounting wiring 13 to seal and protect the semiconductor element 4.

【0023】図4は本発明による効果を説明する断面図
である。
FIG. 4 is a sectional view for explaining the effect of the present invention.

【0024】半導体素子4から放熱フィン18への経路
は、熱の流れBの矢印のように、半導体素子4、ダイボ
ンディングパッド12、図1のブリッジ部15、放熱フ
ィン取付け配線13、脚部17を通して構成される。
The path from the semiconductor element 4 to the radiation fin 18 is as indicated by the arrow of the heat flow B, the semiconductor element 4, the die bonding pad 12, the bridge portion 15 in FIG. 1, the radiation fin mounting wiring 13, and the leg portion 17. Composed through.

【0025】ダイボンディングパッド12、ブリッジ部
15及び放熱フィン取付け配線13は例えば銅パターン
であり、表1に示すように熱伝導率が398.0W/m
・Kと大きく、半導体素子4から発する熱が効率よく放
熱フィン18に伝わる。
The die bonding pad 12, the bridge portion 15 and the radiation fin mounting wiring 13 are, for example, copper patterns and have a thermal conductivity of 398.0 W / m as shown in Table 1.
・ K is large, and the heat generated from the semiconductor element 4 is efficiently transmitted to the radiation fins 18.

【0026】このため、実施形態によれば半導体装置全
体として、良好な放熱効果を得ることができる。
Therefore, according to the embodiment, a good heat dissipation effect can be obtained in the semiconductor device as a whole.

【0027】また、脚部17を有する放熱フィン18を
搭載することによって、半導体素子4が保護されるの
で、封止樹脂が不用になるという利点もある。
Further, since the semiconductor element 4 is protected by mounting the heat radiation fins 18 having the leg portions 17, there is an advantage that the sealing resin becomes unnecessary.

【0028】次に本発明の半導体装置の製造方法につい
て図1及び図2を参照して説明する。
Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIGS.

【0029】まず、半導体素子4を準備し、半導体素子
4を搭載するために中心部に形成したダイボンディング
パッド12と、ダイボンディングパッド12の外側に形
成したワイヤボンディングパッド3と、ダイボンディン
グパッド12及びワイヤボンディングパッド3の周囲を
囲むように配置され、ダイボンディングパッド12とブ
リッジ部15により接続された放熱フィン取付け配線1
3を有する基板11を準備する。
First, the semiconductor element 4 is prepared, and the die bonding pad 12 formed at the center for mounting the semiconductor element 4, the wire bonding pad 3 formed outside the die bonding pad 12, and the die bonding pad 12 And the radiation fin mounting wiring 1 arranged so as to surround the wire bonding pad 3 and connected by the die bonding pad 12 and the bridge portion 15.
A substrate 11 having 3 is prepared.

【0030】更に、放熱フィン取付け配線13に対応し
た形状の脚部17を底面に形成した放熱フィン18を準
備する。
Further, a heat radiation fin 18 having a leg portion 17 having a shape corresponding to the heat radiation fin mounting wiring 13 formed on the bottom surface is prepared.

【0031】半導体素子4をダイボンディングパッド1
2にダイボンディングし、従来と同様に半導体素子4の
電極とワイヤボンディングパッド3をワイヤ5によりワ
イヤボンディングする。
The semiconductor element 4 is attached to the die bonding pad 1
2 is die-bonded, and the electrode of the semiconductor element 4 and the wire bonding pad 3 are wire-bonded with the wire 5 as in the conventional case.

【0032】次に半導体装置の出力端子として、従来と
同様に例えば半田ボール7を接続する。
Next, as an output terminal of the semiconductor device, for example, a solder ball 7 is connected as in the conventional case.

【0033】そして、放熱フィン取付け配線13に放熱
フィン18の脚部17を位置合わせして、導電体の混入
された接着剤で固着して完成する。
Then, the leg portions 17 of the radiation fins 18 are aligned with the radiation fin mounting wirings 13 and fixed by an adhesive containing a conductor to complete the process.

【0034】このようにすれば、半導体素子4は放熱フ
ィン18によって密閉された空間に封止されて保護され
るので、従来のような封止樹脂は不用となり、従って樹
脂封止工程を省略することができ、製造工程を短縮する
ことができる。
In this way, since the semiconductor element 4 is sealed and protected by the radiation fins 18 in the sealed space, the conventional sealing resin is unnecessary, and therefore the resin sealing step is omitted. Therefore, the manufacturing process can be shortened.

【0035】上記の実施形態においては、BGA(Ba
ll Grid Array)構造の半導体装置で説明
したが、LGA(Lang Grid Array)や
QFP(Quad Flatpack Packag
e)等のパッケージ構造の半導体装置にも適用すること
ができる。
In the above embodiment, BGA (Ba
Although the semiconductor device having the ll grid array structure has been described above, the LGA (Lang Grid Array) and the QFP (Quad Flatpack Package) have been described.
It can also be applied to a semiconductor device having a package structure such as e).

【0036】[0036]

【発明の効果】上記したように、本発明によれば、基板
に放熱フィン取付け配線を設け、放熱フィンの脚部を放
熱フィン取付け配線に固着することにより、良好な放熱
効果を得ることができる。
As described above, according to the present invention, by providing the radiation fin mounting wiring on the substrate and fixing the legs of the radiation fin to the radiation fin mounting wiring, a good heat radiation effect can be obtained. .

【0037】更に、半導体素子の保護のために必要であ
った封止樹脂を無くすこともできる。
Further, the sealing resin which is necessary for protecting the semiconductor element can be eliminated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態の基板構造を示す平面図FIG. 1 is a plan view showing a substrate structure according to an embodiment of the present invention.

【図2】実施形態の半導体装置を示す断面図FIG. 2 is a cross-sectional view showing a semiconductor device of an embodiment.

【図3】実施形態の放熱フィンを示す斜視図FIG. 3 is a perspective view showing a heat dissipation fin of the embodiment.

【図4】本発明による効果を説明する断面図FIG. 4 is a sectional view for explaining the effect of the present invention.

【図5】従来の基板構造を示す平面図FIG. 5 is a plan view showing a conventional substrate structure.

【図6】従来の半導体装置を示す断面図FIG. 6 is a sectional view showing a conventional semiconductor device.

【図7】従来技術による問題点を説明する断面図FIG. 7 is a cross-sectional view illustrating a problem with a conventional technique.

【符号の説明】[Explanation of symbols]

3 ワイヤボンディングパッド 4 半導体素子 5 ワイヤ 7 半田ボール 11 基板 12 ダイボンディングパッド 13 放熱フィン取付け配線 14 4角 15 ブリッジ部 16 フィン部 17 脚部 18 放熱フィン 3 wire bonding pad 4 Semiconductor element 5 wires 7 Solder balls 11 board 12 Die bonding pad 13 Radiation fin mounting wiring 14 squares 15 Bridge section 16 fin section 17 legs 18 radiating fins

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載するために基板の中心
部に形成したダイボンディングパッドと、 前記ダイボンディングパッドの周囲を囲むように配置さ
れ、前記ダイボンディングパッドと接続された放熱フィ
ン取付け配線とを備えたことを特徴とする基板構造。
1. A die bonding pad formed in the center of a substrate for mounting a semiconductor element, and a radiation fin mounting wiring arranged so as to surround the periphery of the die bonding pad and connected to the die bonding pad. A substrate structure comprising:
【請求項2】 前記放熱フィン取付け配線が前記ダイボ
ンディングパッドの4角とブリッジ部で接続されたこと
を特徴とする請求項1記載の基板構造。
2. The substrate structure according to claim 1, wherein the radiation fin mounting wiring is connected to the four corners of the die bonding pad at a bridge portion.
【請求項3】 前記放熱フィン取付け配線とダイボンデ
ィングパッドが導電体パターンで同時に形成されたこと
を特徴とする請求項1又は2記載の基板構造。
3. The substrate structure according to claim 1, wherein the heat radiation fin mounting wiring and the die bonding pad are simultaneously formed by a conductor pattern.
【請求項4】 半導体素子と、 前記半導体素子を搭載するために基板の中心部に形成し
たダイボンディングパッドと、前記ダイボンディングパ
ッドの周囲に配置され、前記ダイボンディングパッドと
接続された放熱フィン取付け配線を有する基板と、 前記放熱フィン取付け配線に対応した形状の脚部を底面
に形成し、前記放熱フィン取付け配線に前記脚部を固着
した放熱フィンとを備えたことを特徴とする半導体装
置。
4. A semiconductor element, a die bonding pad formed in a central portion of a substrate for mounting the semiconductor element, and a radiation fin attachment arranged around the die bonding pad and connected to the die bonding pad. A semiconductor device comprising: a substrate having wiring; and a heat dissipation fin in which a leg portion having a shape corresponding to the heat radiation fin mounting wiring is formed on a bottom surface, and the leg portion is fixed to the heat radiation fin mounting wiring.
【請求項5】 前記放熱フィン取付け配線が前記ダイボ
ンディングパッドの4角とブリッジ部で接続されたこと
を特徴とする請求項4記載の半導体装置。
5. The semiconductor device according to claim 4, wherein the radiation fin mounting wiring is connected to the four corners of the die bonding pad by a bridge portion.
【請求項6】 半導体素子を準備する工程と、 前記半導体素子を搭載するために中心部に形成したダイ
ボンディングパッドと、前記ダイボンディングパッドの
周囲を囲むように配置され、前記ダイボンディングパッ
ドと接続された放熱フィン取付け配線を有する基板を準
備する工程と、 前記放熱フィン取付け配線に対応した形状の脚部を底面
に形成した放熱フィンを準備する工程と、 前記半導体素子を前記ダイボンディングパッドにダイボ
ンディングする工程と、 前記放熱フィン取付け配線に前記放熱フィンの脚部を固
着する工程とを備えたことを特徴とする半導体装置の製
造方法。
6. A step of preparing a semiconductor element, a die bonding pad formed in a central portion for mounting the semiconductor element, and a die bonding pad disposed so as to surround the die bonding pad and connected to the die bonding pad. A substrate having the heat radiation fin mounting wiring formed thereon, a step of preparing a heat radiation fin having a leg portion having a shape corresponding to the heat radiation fin mounting wiring formed on the bottom surface, and the semiconductor element being bonded to the die bonding pad by a die. A method of manufacturing a semiconductor device, comprising: a step of bonding, and a step of fixing a leg portion of the radiation fin to the radiation fin mounting wiring.
【請求項7】 前記放熱フィン取付け配線とダイボンデ
ィングパッドを導電体パターンで同時に形成することを
特徴とする請求項6記載の半導体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 6, wherein the radiation fin mounting wiring and the die bonding pad are simultaneously formed by a conductor pattern.
JP2001246902A 2001-08-16 2001-08-16 Substrate structure, semiconductor device and manufacturing method therefor Pending JP2003060132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001246902A JP2003060132A (en) 2001-08-16 2001-08-16 Substrate structure, semiconductor device and manufacturing method therefor

Publications (1)

Publication Number Publication Date
JP2003060132A true JP2003060132A (en) 2003-02-28

Family

ID=19076344

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062480A (en) * 2011-09-14 2013-04-04 Samsung Electro-Mechanics Co Ltd Power module package
WO2014182403A1 (en) * 2013-05-08 2014-11-13 Delphi Technologies, Inc. Printed circuit board heat dissipation system
US8933558B2 (en) 2011-09-30 2015-01-13 Fujitsu Limited Semiconductor package, wiring board unit, and electronic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062480A (en) * 2011-09-14 2013-04-04 Samsung Electro-Mechanics Co Ltd Power module package
US8933558B2 (en) 2011-09-30 2015-01-13 Fujitsu Limited Semiconductor package, wiring board unit, and electronic apparatus
WO2014182403A1 (en) * 2013-05-08 2014-11-13 Delphi Technologies, Inc. Printed circuit board heat dissipation system

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