TWI643297B - Semiconductor package having internal heat sink - Google Patents
Semiconductor package having internal heat sink Download PDFInfo
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- TWI643297B TWI643297B TW105142289A TW105142289A TWI643297B TW I643297 B TWI643297 B TW I643297B TW 105142289 A TW105142289 A TW 105142289A TW 105142289 A TW105142289 A TW 105142289A TW I643297 B TWI643297 B TW I643297B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
揭示一種具有內置散熱片之半導體封裝構造，包含一基板、一設置在基板上之晶片、一設置在基板上之內置散熱片以及一形成於基板上以密封晶片與內置散熱片之封膠體。複數個定位孔為貫穿基板。該內置散熱片之頂板部延伸有複數個側腳部，其一部份嵌陷於定位孔中，以定位該內置散熱片，並且側腳部之嵌陷部份包含側腳部之複數個接合端，顯露於基板底面。封膠體結合固定內置散熱片，更包覆該些側腳部在基板上之其餘部份。因此，有效提高內置散熱片之散熱力與抗翹曲強化。 A semiconductor package structure having a built-in heat sink is disclosed, comprising a substrate, a wafer disposed on the substrate, a built-in heat sink disposed on the substrate, and a sealant formed on the substrate to seal the wafer and the built-in heat sink. A plurality of positioning holes are through the substrate. The top plate portion of the built-in heat sink extends a plurality of side leg portions, a portion of which is embedded in the positioning hole to position the built-in heat sink, and the embedded portion of the side leg portion includes a plurality of joint ends of the side leg portions , exposed on the bottom surface of the substrate. The encapsulant is combined with the built-in heat sink to cover the remaining portions of the side legs on the substrate. Therefore, the heat dissipation and warpage strengthening of the built-in heat sink are effectively improved.
Description
本發明係有關於半導體晶片封裝領域，特別係有關於一種具有內置散熱片之半導體封裝構造。 The present invention relates to the field of semiconductor chip packaging, and more particularly to a semiconductor package structure having a built-in heat sink.
傳統半導體封裝構造會安裝散熱片，以提供散熱能力。其中，半導體封裝構造包含基板、設置在基板上之晶片以及形成在基板上之封膠體，以密封晶片。在一種散熱片的安裝方法中，當封膠體形成之後，外置型散熱片是貼附在封膠體之頂面。在另一種散熱片的安裝方法中，當封膠體形成之前，內置型散熱片是預先設置在基板上，在封膠體之形成過程中，封膠體同時密封晶片與內置型散熱片。 Traditional semiconductor package constructions mount heat sinks to provide heat dissipation. Wherein, the semiconductor package structure comprises a substrate, a wafer disposed on the substrate, and a sealant formed on the substrate to seal the wafer. In a method of mounting a heat sink, after the sealant is formed, the external heat sink is attached to the top surface of the sealant. In another method of mounting a heat sink, the built-in heat sink is previously disposed on the substrate before the sealant is formed. During the formation of the sealant, the sealant simultaneously seals the wafer and the built-in heat sink.
在習知的具有內置散熱片之半導體封裝構造中，內置型散熱片對基板之結合部位只有到基板之模封表面，故沒辦法更有效率的散熱。在形成封膠體之模封溫度影響下，內置型散熱片對基板之結合力即使使用銲料也會降低，不利於內置型散熱片在模封步驟前之定位。 In a conventional semiconductor package structure having a built-in heat sink, the bonding portion of the built-in heat sink to the substrate has only a molded surface to the substrate, so there is no way to dissipate heat more efficiently. Under the influence of the molding temperature of the encapsulant, the bonding force of the built-in heat sink to the substrate is reduced even if solder is used, which is disadvantageous for the positioning of the built-in heat sink before the molding step.
為了解決上述之問題，本發明之主要目的係在於提 供一種具有內置散熱片之半導體封裝構造，改善傳統散熱片只在封裝基板之安裝面導熱之現象，使得內置散熱片可直接熱耦合至外接端子，以增進封裝散熱並加強封裝構造之抗翹曲度。 In order to solve the above problems, the main object of the present invention is to provide a semiconductor package structure having a built-in heat sink, which improves the heat conduction of the conventional heat sink only on the mounting surface of the package substrate, so that the built-in heat sink can be directly thermally coupled to the external terminal. To enhance package heat dissipation and enhance the warpage resistance of the package structure.
本發明之次一目的係在於提供一種具有內置散熱片之半導體封裝構造，用以加強內置散熱片在封裝基板上之抗模封衝擊能力，以避免在形成封膠體之過程中內置散熱片之位移。 A second object of the present invention is to provide a semiconductor package structure having a built-in heat sink for enhancing the impact resistance of the built-in heat sink on the package substrate to avoid displacement of the built-in heat sink during formation of the sealant. .
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種具有內置散熱片之半導體封裝構造，包含一基板、一晶片、一內置散熱片以及一封膠體。該基板係具有一安裝面、一底面以及複數個定位孔，該些定位孔係由該安裝面貫穿至該底面。該晶片係設置在該基板之該安裝面上，該晶片係具有一主動面與一背面。該內置散熱片係設置在該基板之該安裝面上，以遮蓋該晶片，該內置散熱片係具有一頂板部與複數個由該頂板部周邊曲折延伸之側腳部，該內置散熱片之該些側腳部之一部份係嵌陷於該些定位孔中，以定位該內置散熱片，並且該些側腳部之該些嵌陷部份係包含該些側腳部之複數個接合端，其係顯露於該底面。該封膠體係形成於該基板之該安裝面上，以密封該晶片並結合固定該內置散熱片，其中該封膠體係更包覆該些側腳部在該基板上之其餘部份。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure with a built-in heat sink, comprising a substrate, a wafer, a built-in heat sink and a gel. The substrate has a mounting surface, a bottom surface and a plurality of positioning holes, and the positioning holes are penetrated from the mounting surface to the bottom surface. The wafer is disposed on the mounting surface of the substrate, and the wafer has an active surface and a back surface. The built-in heat sink is disposed on the mounting surface of the substrate to cover the wafer, and the built-in heat sink has a top plate portion and a plurality of side legs extending from the periphery of the top plate portion, the built-in heat sink One of the side leg portions is embedded in the positioning holes to position the built-in heat sink, and the indented portions of the side leg portions include a plurality of joint ends of the side leg portions. It is exposed on the bottom surface. The encapsulation system is formed on the mounting surface of the substrate to seal the wafer and bond the built-in heat sink, wherein the encapsulation system further covers the remaining portions of the side legs on the substrate.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述半導體封裝構造中，該內置散熱片之該頂板 部係具體地具有一外表面，係顯露於該封膠體之一頂面，以供表面散熱。在一具體形態中，該外表面係與該頂面為共平面，以利用平板模具形成該封膠體。 In the foregoing semiconductor package structure, the top plate portion of the built-in heat sink specifically has an outer surface exposed on a top surface of the sealant for heat dissipation from the surface. In one embodiment, the outer surface is coplanar with the top surface to form the encapsulant using a flat mold.
在前述半導體封裝構造中，可另包含複數個銲線，係電連接該晶片之複數個銲墊與該基板在該安裝面上之複數個接點，該些銲線係位於該內置散熱片之遮罩空間，該封膠體係填滿該遮罩空間，以密封該些銲線。 In the foregoing semiconductor package structure, a plurality of bonding wires may be further included, which are electrically connected to a plurality of pads of the chip and a plurality of contacts of the substrate on the mounting surface, wherein the bonding wires are located in the built-in heat sink The masking space fills the masking space to seal the bonding wires.
在前述半導體封裝構造中，該基板之該底面係可設置有複數個第一接墊與複數個第二接墊，該些第一接墊係相對該些第二接墊鄰近於該基板之周邊，該內置散熱片之該些側腳部係熱耦合連接至該些第一接墊。因此，該內置散熱片之該些側腳部得以貫穿該些第一接墊，達到該內置散熱片在該基板上之良好機械固定與該內置散熱片對基板下層接墊的直接熱耦合效果。 In the foregoing semiconductor package structure, the bottom surface of the substrate may be provided with a plurality of first pads and a plurality of second pads, and the first pads are adjacent to the periphery of the substrate with respect to the second pads. The side legs of the built-in heat sink are thermally coupled to the first pads. Therefore, the side legs of the built-in heat sink can penetrate the first pads to achieve a good mechanical coupling of the built-in heat sink on the substrate and a direct thermal coupling effect of the built-in heat sink on the lower layer of the substrate.
在前述半導體封裝構造中，另包含複數個第一外接端子，該些第一外接端子係設置於該基板之該些第一接墊，並且該些第一外接端子係更連接至該些側腳部之該些接合端之該些接合端，藉此進一步達成該內置散熱片對基板下方外接端子的直接熱耦合效果。 In the foregoing semiconductor package structure, a plurality of first external terminals are further disposed, the first external terminals are disposed on the first pads of the substrate, and the first external terminals are further connected to the side legs. The joint ends of the joint ends of the portion further achieve a direct thermal coupling effect of the built-in heat sink on the external terminals under the substrate.
在前述半導體封裝構造中，該些第一外接端子係具體地包含複數個銲球，以成為球格陣列封裝下方銲球群之散熱片導熱球。 In the foregoing semiconductor package structure, the first external terminals specifically include a plurality of solder balls to become heat sink balls of the solder ball group under the ball grid array package.
在前述半導體封裝構造中，可另包含複數個第二外 接端子，該些第二外接端子係設置於該基板之該些第二接墊，可電連接至該晶片。 In the foregoing semiconductor package structure, a plurality of second external terminals may be further included, and the second external terminals are disposed on the second pads of the substrate and electrically connected to the wafer.
在前述半導體封裝構造中，該些第二外接端子係具體地包含複數個銲球，以成為球格陣列封裝下方銲球群之訊號輸出輸入球。 In the foregoing semiconductor package structure, the second external terminals specifically include a plurality of solder balls to serve as a signal output input ball of the solder ball group under the ball grid array package.
在前述半導體封裝構造中，較佳地另包含一晶片貼附層，係形成於該晶片之該背面與該基板之該安裝面之間，該基板之該底面係更設置有複數個第三接墊，其係位於該些第一接墊與該些第二接墊之間，該晶片係經由該晶片貼附層熱耦合連接至該些第三接墊。 Preferably, the semiconductor package structure further includes a wafer attaching layer formed between the back surface of the wafer and the mounting surface of the substrate, wherein the bottom surface of the substrate is further provided with a plurality of third connections. The pad is located between the first pads and the second pads, and the chip is thermally coupled to the third pads via the wafer attaching layer.
在前述半導體封裝構造中，具體地可另包含複數個第三外接端子，該些第三外接端子係設置於該基板之該些第三接墊，其中該些第三外接端子係包含複數個銲球，以成為球格陣列封裝下方銲球群之晶片導熱球。 In the foregoing semiconductor package structure, a plurality of third external terminals may be further included, and the third external terminals are disposed on the third pads of the substrate, wherein the third external terminals comprise a plurality of solders The ball is used to become the thermal ball of the wafer of the solder ball group under the ball grid array package.
藉由上述的技術手段，本發明可以解決習知內置散熱片只導熱到基板之安裝面而沒辦法在封裝表面有效散熱之問題，本發明包含之該內置散熱片具有針對該基板直通到底之該些側腳部，更加上其連接之該些第一外接端子(可具體為錫球)的熱耦合連接，故可以更有效提高散熱效率，並且該內置散熱片對該基板之連接機構也可以強化封裝構造之抗翹曲能力。 According to the above technical means, the present invention can solve the problem that the conventional built-in heat sink only conducts heat to the mounting surface of the substrate and cannot effectively dissipate heat on the surface of the package. The present invention includes the built-in heat sink having the direct through to the substrate. The side legs are further thermally coupled to the first external terminals (which may be specifically solder balls) connected thereto, so that the heat dissipation efficiency can be more effectively improved, and the connection mechanism of the built-in heat sink to the substrate can also be strengthened. The warpage resistance of the package construction.
100‧‧‧半導體封裝構造 100‧‧‧Semiconductor package construction
110‧‧‧基板 110‧‧‧Substrate
111‧‧‧安裝面 111‧‧‧Installation surface
112‧‧‧底面 112‧‧‧ bottom
113‧‧‧定位孔 113‧‧‧Positioning holes
114‧‧‧接點 114‧‧‧Contacts
115‧‧‧第一接墊 115‧‧‧First mat
116‧‧‧第二接墊 116‧‧‧second mat
117‧‧‧第三接墊 117‧‧‧ third mat
120‧‧‧晶片 120‧‧‧ wafer
121‧‧‧主動面 121‧‧‧Active surface
122‧‧‧背面 122‧‧‧Back
123‧‧‧銲墊 123‧‧‧ solder pads
130‧‧‧內置散熱片 130‧‧‧ Built-in heat sink
131‧‧‧頂板部 131‧‧‧Top Board
132‧‧‧側腳部 132‧‧‧Side foot
133‧‧‧接合端 133‧‧‧ joint end
134‧‧‧外表面 134‧‧‧ outer surface
140‧‧‧封膠體 140‧‧‧ Sealant
141‧‧‧頂面 141‧‧‧ top
150‧‧‧銲線 150‧‧‧welding line
160‧‧‧第一外接端子 160‧‧‧First external terminal
170‧‧‧第二外接端子 170‧‧‧Second external terminal
180‧‧‧晶片貼附層 180‧‧‧ wafer attach layer
190‧‧‧第三外接端子 190‧‧‧ Third external terminal
第1圖：依據本發明之一具體實施例，一種具有內置散熱片之半導體封裝構造之截面示意圖。 1 is a cross-sectional view showing a semiconductor package structure having a built-in heat sink according to an embodiment of the present invention.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例，一種具有內置散熱片之半導體封裝構造100舉例說明於第1圖之截面示意圖。該半導體封裝構造100係包含一基板110、一晶片120、一內置散熱片130以及一封膠體140。 In accordance with an embodiment of the present invention, a semiconductor package structure 100 having a built-in heat sink is illustrated in cross-section in FIG. The semiconductor package structure 100 includes a substrate 110, a wafer 120, a built-in heat sink 130, and a gel 140.
該基板110係具有一安裝面111、一底面112以及複數個定位孔113，該些定位孔113係由該安裝面111貫穿至該底面112。該基板110係具體可為一微小化切單之印刷電路板。複數個接點114係可配置於該安裝面111，用以電性連接至該晶片120。複數個第一接墊115、複數個第二接墊116與複數個第三接墊117係可配置於該底面112，以供接合例如銲球等外接端子。 The substrate 110 has a mounting surface 111 , a bottom surface 112 , and a plurality of positioning holes 113 . The positioning holes 113 are penetrated from the mounting surface 111 to the bottom surface 112 . The substrate 110 is specifically a printed circuit board that is miniaturized and singulated. A plurality of contacts 114 are disposed on the mounting surface 111 for electrically connecting to the wafer 120. A plurality of first pads 115, a plurality of second pads 116 and a plurality of third pads 117 may be disposed on the bottom surface 112 for bonding external terminals such as solder balls.
該晶片120係設置在該基板110之該安裝面111上，該晶片120係具有一主動面121與一背面122。該晶片120係具體為一 具有積體電路的半導體基板，其積體電路係製作成該主動面121，該主動面121上可配置有複數個銲墊123，其為該晶片120內部積體電路之對外電極端。在本實施例中，該半導體封裝構造100係另包含一晶片貼附層180，係形成於該晶片120之該背面122與該基板110之該安裝面111之間，用以固定該晶片120在該基板110上。該晶片貼附層180係具有導熱性，其材質係具體可為包含有導熱顆粒之熱固膠、銀膠或是錫金共晶。 The wafer 120 is disposed on the mounting surface 111 of the substrate 110. The wafer 120 has an active surface 121 and a back surface 122. The wafer 120 is specifically a semiconductor substrate having an integrated circuit, and the integrated circuit is formed on the active surface 121. The active surface 121 can be provided with a plurality of pads 123, which are internal integrated circuits of the wafer 120. The external electrode end. In this embodiment, the semiconductor package structure 100 further includes a wafer attaching layer 180 formed between the back surface 122 of the wafer 120 and the mounting surface 111 of the substrate 110 for fixing the wafer 120. On the substrate 110. The wafer attaching layer 180 is thermally conductive, and the material thereof may specifically be a thermosetting adhesive, a silver paste or a tin-gold eutectic containing thermally conductive particles.
該內置散熱片130係設置在該基板110之該安裝面111上，以遮蓋該晶片120，該內置散熱片130係具有一頂板部131與複數個由該頂板部131周邊曲折延伸之側腳部132，該內置散熱片130之該些側腳部132之一部份係嵌陷於該些定位孔113中，以定位該內置散熱片130之該頂板部131在該基板110上，並且該些側腳部132之該些嵌陷部份係包含該些側腳部132之複數個接合端133，其係顯露於該底面112。該內置散熱片130之主要材質係可為銅或已知導熱材料。在本實施例中，該內置散熱片130之該頂板部131係具體地具有一外表面134，係顯露於該封膠體140之一頂面141，以供表面散熱。在一具體形態中，該外表面134係與該頂面141為共平面，以利用平板模具形成該封膠體140。 The built-in heat sink 130 is disposed on the mounting surface 111 of the substrate 110 to cover the wafer 120. The built-in heat sink 130 has a top plate portion 131 and a plurality of side legs extending from the periphery of the top plate portion 131. 132. One of the side leg portions 132 of the built-in heat sink 130 is embedded in the positioning holes 113 to position the top plate portion 131 of the built-in heat sink 130 on the substrate 110, and the sides are The indented portions of the leg portion 132 include a plurality of engaging ends 133 of the side leg portions 132 that are exposed to the bottom surface 112. The main material of the built-in heat sink 130 may be copper or a known heat conductive material. In this embodiment, the top plate portion 131 of the built-in heat sink 130 specifically has an outer surface 134 exposed on a top surface 141 of the sealant 140 for heat dissipation from the surface. In one embodiment, the outer surface 134 is coplanar with the top surface 141 to form the encapsulant 140 using a flat mold.
該封膠體140係形成於該基板110之該安裝面111上，以密封該晶片120並結合固定該內置散熱片130，其中該封膠體140係更包覆該些側腳部132在該基板110上之其餘部份。該封膠體140係具體可為模封環氧化合物(Epoxy Molding Compound, EMC)，以模封方式形成於該基板110上。 The encapsulant 140 is formed on the mounting surface 111 of the substrate 110 to seal the wafer 120 and bond the built-in heat sink 130. The encapsulant 140 further covers the side legs 132 at the substrate 110. The rest of the list. The encapsulant 140 is specifically an Epoxy Molding Compound (EMC) formed on the substrate 110 in a mold-sealing manner.
在本實施例中，該半導體封裝構造100係可另包含複數個銲線150，係電連接該晶片120之該些銲墊123與該基板110在該安裝面111上之該些接點114，該些銲線150係位於該內置散熱片130之遮罩空間，該封膠體140係填滿該遮罩空間，以密封該些銲線150。 In this embodiment, the semiconductor package structure 100 can further include a plurality of bonding wires 150 electrically connecting the pads 123 of the wafer 120 and the contacts 114 of the substrate 110 on the mounting surface 111. The bonding wires 150 are located in the mask space of the built-in heat sink 130, and the sealing body 140 fills the mask space to seal the bonding wires 150.
在本實施例中，該些第一接墊115與該些第二接墊116係設置於該基板110之該底面112，該些第一接墊115係相對該些第二接墊116鄰近於該基板110之周邊，該內置散熱片130之該些側腳部132係熱耦合連接至該些第一接墊115。因此，該內置散熱片130之該些側腳部132得以貫穿該些第一接墊115，達到該內置散熱片130在該基板110上之良好機械固定與該內置散熱片130對基板110下層接墊的直接熱耦合效果。此外，該些第三接墊117係可設置於該基板110之該底面112，並位於該些第一接墊115與該些第二接墊116之間，該晶片120係經由該晶片貼附層180熱耦合連接至該些第三接墊117。 In this embodiment, the first pads 115 and the second pads 116 are disposed on the bottom surface 112 of the substrate 110, and the first pads 115 are adjacent to the second pads 116. The side legs 132 of the built-in heat sink 130 are thermally coupled to the first pads 115 . Therefore, the side leg portions 132 of the built-in heat sink 130 can penetrate the first pads 115, and the good mechanical fixing of the built-in heat sink 130 on the substrate 110 and the built-in heat sink 130 are connected to the substrate 110. The direct thermal coupling effect of the pad. In addition, the third pads 117 can be disposed on the bottom surface 112 of the substrate 110 and between the first pads 115 and the second pads 116. The wafers 120 are attached via the wafers. Layer 180 is thermally coupled to the third pads 117.
在本實施例中，該半導體封裝構造100係可另包含複數個第一外接端子160，該些第一外接端子160係設置於該基板110之該些第一接墊115，並且該些第一外接端子160係更連接至該些側腳部132之該些接合端133之該些接合端133，藉此進一步達成該內置散熱片130對基板110下方外接端子的直接熱耦合效果。該些第一外接端子160係具體地包含複數個銲球，以成為球 格陣列封裝下方銲球群之散熱片導熱球。 In this embodiment, the semiconductor package structure 100 can further include a plurality of first external terminals 160. The first external terminals 160 are disposed on the first pads 115 of the substrate 110, and the first The external terminals 160 are further connected to the joint ends 133 of the joint ends 133 of the side legs 132, thereby further achieving the direct thermal coupling effect of the built-in heat sink 130 on the external terminals below the substrate 110. The first external terminals 160 specifically include a plurality of solder balls to be the heat transfer balls of the solder balls of the solder ball group under the grid array package.
在本實施例中，該半導體封裝構造100係可另包含複數個第二外接端子170，該些第二外接端子170係設置於該基板110之該些第二接墊116，可電連接至該晶片120。該些第二外接端子170係具體地包含複數個銲球，以成為球格陣列封裝下方銲球群之訊號輸出輸入球。 In this embodiment, the semiconductor package structure 100 can further include a plurality of second external terminals 170, and the second external terminals 170 are disposed on the second pads 116 of the substrate 110, and can be electrically connected to the Wafer 120. The second external terminals 170 specifically include a plurality of solder balls to be the signal output input balls of the solder ball group under the ball grid array package.
在本實施例中，該半導體封裝構造100係更包含複數個第三外接端子190，該些第三外接端子190係設置於該基板110之該些第三接墊117，其中該些第三外接端子190係包含複數個銲球，以成為球格陣列封裝下方銲球群之晶片120導熱球。 In this embodiment, the semiconductor package structure 100 further includes a plurality of third external terminals 190, and the third external terminals 190 are disposed on the third pads 117 of the substrate 110, wherein the third external connections are Terminal 190 includes a plurality of solder balls to become a thermal ball of wafer 120 of the solder ball group below the ball grid array package.
本發明提供一種具有內置散熱片之半導體封裝構造100係具有以下功效： The present invention provides a semiconductor package structure 100 having a built-in heat sink having the following effects:
一、改善傳統散熱片只在封裝基板之安裝面導熱之現象，使得該內置散熱片130可直接熱耦合至該些第一外接端子160，以增進封裝散熱並加強該半導體封裝構造100之抗翹曲度。 1. Improving the phenomenon that the conventional heat sink only conducts heat on the mounting surface of the package substrate, so that the built-in heat sink 130 can be directly thermally coupled to the first external terminals 160 to improve heat dissipation of the package and enhance the anti-warping of the semiconductor package structure 100. Curvature.
二、加強該內置散熱片130在該封裝基板110上之抗模封衝擊能力，以避免在形成該封膠體140之過程中造成該內置散熱片130之位移。 2. The anti-molding impact capability of the built-in heat sink 130 on the package substrate 110 is enhanced to avoid displacement of the built-in heat sink 130 during the formation of the encapsulant 140.
以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。 The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.
Claims (9)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI281238B (en) * | 2002-09-30 | 2007-05-11 | Advanced Interconnect Tech Ltd | Thermal enhanced package for block mold assembly |
| TW200820403A (en) * | 2006-10-30 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing semiconductor device |
| TWI365521B (en) * | 2008-03-11 | 2012-06-01 | Powertech Technology Inc | Semiconductor package structure with heat sink |
| TWI425599B (en) * | 2009-11-11 | 2014-02-01 | Bridge Semoconductor Corp | Semiconductor chip assembly with post/base heat spreaderand substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI281238B (en) * | 2002-09-30 | 2007-05-11 | Advanced Interconnect Tech Ltd | Thermal enhanced package for block mold assembly |
| TW200820403A (en) * | 2006-10-30 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing semiconductor device |
| TWI365521B (en) * | 2008-03-11 | 2012-06-01 | Powertech Technology Inc | Semiconductor package structure with heat sink |
| TWI425599B (en) * | 2009-11-11 | 2014-02-01 | Bridge Semoconductor Corp | Semiconductor chip assembly with post/base heat spreaderand substrate |
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