WO2004088727B1 - Multi-chip ball grid array package and method of manufacture - Google Patents

Multi-chip ball grid array package and method of manufacture

Info

Publication number
WO2004088727B1
WO2004088727B1 PCT/IB2004/001734 IB2004001734W WO2004088727B1 WO 2004088727 B1 WO2004088727 B1 WO 2004088727B1 IB 2004001734 W IB2004001734 W IB 2004001734W WO 2004088727 B1 WO2004088727 B1 WO 2004088727B1
Authority
WO
WIPO (PCT)
Prior art keywords
base
substrate
face
wires
chip
Prior art date
Application number
PCT/IB2004/001734
Other languages
French (fr)
Other versions
WO2004088727A2 (en
WO2004088727A8 (en
WO2004088727A3 (en
Inventor
Fung Leng Chen
Seong Kwang Brandon Kim
Wee Lim Cha
Yi-Sheng Anthony Sun
Wolfgang Hetzel
Jochen Thomas
Original Assignee
United Test & Assembly Ct Ltd
Infineon Technologies
Fung Leng Chen
Seong Kwang Brandon Kim
Wee Lim Cha
Yi-Sheng Anthony Sun
Wolfgang Hetzel
Jochen Thomas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Test & Assembly Ct Ltd, Infineon Technologies, Fung Leng Chen, Seong Kwang Brandon Kim, Wee Lim Cha, Yi-Sheng Anthony Sun, Wolfgang Hetzel, Jochen Thomas filed Critical United Test & Assembly Ct Ltd
Priority to US10/552,046 priority Critical patent/US7851899B2/en
Priority to DE112004000572T priority patent/DE112004000572B4/en
Publication of WO2004088727A2 publication Critical patent/WO2004088727A2/en
Publication of WO2004088727A3 publication Critical patent/WO2004088727A3/en
Publication of WO2004088727A8 publication Critical patent/WO2004088727A8/en
Publication of WO2004088727B1 publication Critical patent/WO2004088727B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A BGA package (500) is disclosed including a base IC structure (300) having a base substrate (302), with an opening (301c) running lengthwise therethrough. A first semiconductor chip (315) is mounted face-down on the base substrate (301) so that the bond pads (317) thereof are accessible through the opening (301c). The package (500) also includes a secondary IC structure (400) including a secondary substrate (401), having an opening (401c) running there through, and a second semiconductor chip (415). The second chip (415) is mounted face-down on the secondary substrate (401) so that the bond pads (417) thereof are accessible through the opening (401c) in the secondary substrate (401). An encapsulant (425) fills the opening (401c) in the secondary substrate (401) and forms a substantially planar surface (425a) over the underside of the secondary substrate (401). The substantially planar surface (425a) is mounted to the first chip (315) of the base IC structure (300) through an adhesive (504). Wires (521) connect a conductive portion (406) of the secondary IC structure (400) to a conductive portion (303) of the base IC structure (300).

Claims

AMENDED CLAIMS [received by the International Bureau on 03 December 2004 (03.12.2004); original claims 1, 5, 8 and 9 amended; original claims 3 and 4 cancelled ; remaining claims unchanged (4 pages)]
1. A ball grid array package comprising: a base IC structure, the base IC structure comprising: a base substrate having a first base substrate face, a second base substrate face opposite to said first base substrate face, a base substrate opening extending between said first base substrate face and said second base substrate face, and a base conductor, a first semiconductor chip, comprising a first chip face, a second chip face opposite to said first chip face, and first bond pads disposed over said base opening; and a first plurality of wires disposed to pass through said substrate base opening and electrically connecting said first bond pads to said base conductor; and a secondary IC structure, comprising: a second substrate having a first secondary substrate base, a second secondary substrate face opposite to said first secondary substrate face, a secondary opening extending between said first secondary substrate face and said second secondary substrate face, and a secondary conductor; a second semiconductor chip, comprising a second chip face, and a second bond pad disposed over said secondary opening; and a second plurality of wires electrically connecting said second bond pads to said secondary conductor through said secondary opening; and a first encapsulant filling said secondary opening around said second plurality of wires and covering said second secondary substrate face; and said secondary IC structure being mounted on said face IC structure, and further comprising a third plurality of wires connecting said secondary IC structure to said base IC structure.
22
2. A ball grid array package according to claim 1, wherein: said base substrate further comprises a plurality of vias extending between said first base substrate face and said second base substrate face; said base conductor extends through said vias; and said base substrate further comprises a layer of solder mask disposed on portions of said first and second chip faces.
3. Cancelled.
4. Cancelled.
5. The ball grid array package according to claim 1, further comprising molding compound encapsulating at least portions of said base IC structure and said secondary IC structure.
6. The ball grid array package according to claim 5, wherein said molding compound encapsulates said third plurality of wires.
7. The ball grid array package according to claim 5, wherein said first secondary chip face is free of said molding compound.
8. The ball grid array package according to claim 1, further comprising:
24 at least one additional of said secondary IC structure mounted over said first secondary chip face; and respective wires connecting a conductive portion of said at least one additional secondary IC structure to said base IC structure.
9. The ball grid array package according to claim 1, further comprising a thermal dissipation element disposed over said first secondary chip face.
10. A method of assembling a ball grid array package, comprising: providing a base IC structure, comprising a base substrate and a first semiconductor chip mounted on said base substrate in a die-down configuration; linking the bond pads of the base chip to the base substrate using the first plurality of wires; providing a first secondary IC structure, comprising a secondary substrate and a second semiconductor chip mounted on said second substrate in a die-down configuration; mounting the first secondary IC structure to said base IC structure; electrically connecting a conductive portion of said secondary IC structure to a conductive portion of said base IC structure using at least a second plurality of wires, and encapsulating said base IC structure and said first secondary IC structure, including said first plurality of wires and said second plurality of wires.
11. The method of claim 10, wherein said encapsulating step comprises first encapsulating said first secondary IC structure and subsequently encapsulating said base IC structure and said first secondary IC structure, together with said first and second plurality of wires.
25
PCT/IB2004/001734 2003-04-02 2004-04-02 Multi-chip ball grid array package and method of manufacture WO2004088727A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/552,046 US7851899B2 (en) 2004-04-02 2004-04-02 Multi-chip ball grid array package and method of manufacture
DE112004000572T DE112004000572B4 (en) 2003-04-02 2004-04-02 Multi-chip ball grid array housing and manufacturing process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45935303P 2003-04-02 2003-04-02
US60/459,353 2003-04-02

Publications (4)

Publication Number Publication Date
WO2004088727A2 WO2004088727A2 (en) 2004-10-14
WO2004088727A3 WO2004088727A3 (en) 2004-11-11
WO2004088727A8 WO2004088727A8 (en) 2004-12-29
WO2004088727B1 true WO2004088727B1 (en) 2005-03-10

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US9299684B2 (en) 2005-08-26 2016-03-29 Micron Technology, Inc. Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200536089A (en) * 2004-03-03 2005-11-01 United Test & Assembly Ct Ltd Multiple stacked die window csp package and method of manufacture
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices

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Publication number Priority date Publication date Assignee Title
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
JP3420706B2 (en) * 1998-09-22 2003-06-30 株式会社東芝 Semiconductor device, method of manufacturing semiconductor device, circuit board, and method of manufacturing circuit board
US6424033B1 (en) * 1999-08-31 2002-07-23 Micron Technology, Inc. Chip package with grease heat sink and method of making
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
DE10259221B4 (en) * 2002-12-17 2007-01-25 Infineon Technologies Ag Electronic component comprising a stack of semiconductor chips and method of making the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299684B2 (en) 2005-08-26 2016-03-29 Micron Technology, Inc. Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US9583476B2 (en) 2005-08-26 2017-02-28 Micron Technology, Inc. Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

Also Published As

Publication number Publication date
WO2004088727A2 (en) 2004-10-14
TWI338927B (en) 2011-03-11
DE112004000572T5 (en) 2006-03-23
WO2004088727A8 (en) 2004-12-29
TW200504894A (en) 2005-02-01
DE112004000572B4 (en) 2008-05-29
WO2004088727A3 (en) 2004-11-11

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