KR100727728B1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
KR100727728B1
KR100727728B1 KR1020060047966A KR20060047966A KR100727728B1 KR 100727728 B1 KR100727728 B1 KR 100727728B1 KR 1020060047966 A KR1020060047966 A KR 1020060047966A KR 20060047966 A KR20060047966 A KR 20060047966A KR 100727728 B1 KR100727728 B1 KR 100727728B1
Authority
KR
South Korea
Prior art keywords
circuit pattern
semiconductor chip
printed circuit
conductive adhesive
conductive
Prior art date
Application number
KR1020060047966A
Other languages
Korean (ko)
Inventor
황선하
Original Assignee
에스티에스반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스티에스반도체통신 주식회사 filed Critical 에스티에스반도체통신 주식회사
Priority to KR1020060047966A priority Critical patent/KR100727728B1/en
Application granted granted Critical
Publication of KR100727728B1 publication Critical patent/KR100727728B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package is provided to quickly dissipate the heat generated from a semiconductor chip by directly connecting a heat sink with a printed circuit tape or board through a conductive adhesive. A printed circuit tape(100) as a circuit pattern(101) formed on an upper surface and plural external connection pads(102) electrically connected to the circuit pattern through a via hole(102). A solder mask(110) is formed on the upper surface of the printed circuit tape to expose a given region of the circuit pattern. A heat sink(130) is adhered on the solder mask, and a conductive adhesive(140) is applied on an upper surface of the heat sink and the exposed circuit pattern. A semiconductor chip(150) is attached to the adhesive, and is connected to the circuit pattern by a conductive wire(160).

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor Package {SEMICONDUCTOR PACKAGE}

도 1은 본 발명의 제1 실시예에 따른 반도체 패키지를 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a semiconductor package in accordance with a first embodiment of the present invention.

도 2는 본 발명의 제2 실시예에 따른 반도체 패키지를 설명하기 위한 단면도이다.2 is a cross-sectional view for describing a semiconductor package according to a second exemplary embodiment of the present invention.

도 3은 본 발명의 제3 실시예에 따른 반도체 패키지를 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a semiconductor package in accordance with a third embodiment of the present invention.

도 4는 본 발명의 제4 실시예에 따른 반도체 패키지를 설명하기 위한 단면도이다.4 is a cross-sectional view illustrating a semiconductor package in accordance with a fourth embodiment of the present invention.

*** 도면의 주요 부분에 대한 부호 설명 ****** Explanation of symbols on main parts of drawing ***

100,200 : 인쇄회로테이프, 101,201,302,402 : 회로패턴,100,200: printed circuit tape, 101,201,302,402: circuit pattern,

101a,201a,302a,302b,402a,402b : 금속단자,101a, 201a, 302a, 302b, 402a, 402b: metal terminal,

102,202 : 비아홀, 103,203,304,404 : 솔더볼,102, 202: via hole, 103,203,304,404: solder ball,

110,210,310,410 : 솔더마스크, 120,320 : 접착테이프,110,210,310,410: solder mask, 120,320: adhesive tape,

130,230,330,430 : 방열판, 140,340 : 전도성 접착제,130,230,330,430: heat sink, 140,340: conductive adhesive,

150,250,350,450 : 반도체 칩, 160,260,360,460 : 전도성 와이어,150,250,350,450: semiconductor chip, 160,260,360,460: conductive wire,

170,270,370,470 : 패키지 몸체,170,270,370,470: package body,

220,240 및 420,440 : 제1,2 전도성 접착제,220,240 and 420,440: first and second conductive adhesives,

300,400 : 인쇄회로기판, 301,401 : 코어층,300,400: printed circuit board, 301,401: core layer,

303,403 : 비아303,403: Via

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 내장된 반도체 칩의 구동 시 발생한 열을 외부로 신속하게 방출하여 신뢰성과 수명이 향상될 수 있도록 한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which heat generated during driving of an embedded semiconductor chip is quickly released to the outside to improve reliability and lifespan.

일반적으로, 반도체 패키지란 웨이퍼로(Wafer)부터 소잉(Sawing)된 반도체 칩을 섭스트레이트(Substrate) 예컨대, 인쇄회로기판(Printed Circuit Board, PCB), 인쇄회로필름(Printed Circuit Film), 인쇄회로테이프(Printed Circuit Tape) 등에 전기적으로 연결함과 동시에 수지 봉지재로 이루어진 패키지 몸체를 감싸서 마더보드(Mother Board)에 전기적으로 실장할 수 있는 형태의 것을 말한다.In general, a semiconductor package refers to a semiconductor chip that is sawed from wafer to substrate, for example, a printed circuit board (PCB), a printed circuit film, or a printed circuit tape. It refers to a type that can be electrically connected to a printed circuit tape and wrapped on a package body made of a resin encapsulant and electrically mounted on a motherboard.

이러한 반도체 패키지는 매우 다양한 종류가 있으나, 최근에는 섭스트레이트(Substrate)의 회로패턴 밀도를 높일 수 있고, 많은 입출력 단자를 확보할 수 있는 볼 그리드 어레이(Ball Grid Array, BGA) 계열의 반도체 패키지가 많이 생산 되고 있다.There are many kinds of semiconductor packages, but in recent years, there are many ball grid array (BGA) -based semiconductor packages that can increase the circuit pattern density of the substrate and secure many input / output terminals. Is being produced.

그러나, 종래의 반도체 패키지 및 시스템 인 패키지(System in Package, SiP)에서는 열 갇힘 현상에 의하여 열적 특성이 저하되는 문제점이 있다.However, in the conventional semiconductor package and the system in package (SiP), there is a problem that the thermal characteristics are degraded due to the heat trapping phenomenon.

본 발명은 전술한 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 에폭시와 같은 열 매개 물질인 전도성 접착제로 내장된 방열판과 인쇄회로테이프 또는 인쇄회로기판에 직접적으로 연결시킴으로써, 반도체 칩의 구동 시 발생한 열을 외부로 신속하게 방출하여 신뢰성과 수명이 향상되는 반도체 패키지를 제공하는데 있다.The present invention has been made to solve the above problems, an object of the present invention is to drive a semiconductor chip by directly connecting to a heat sink and a printed circuit tape or a printed circuit board embedded with a conductive adhesive that is a thermal media such as epoxy To provide a semiconductor package that can quickly release the heat generated during the outside to improve reliability and lifespan.

전술한 목적을 달성하기 위하여 본 발명의 제1 측면은, 상면에 형성된 회로패턴과 저면에 형성된 다수의 외부 접속패드가 비아홀에 의해 전기적으로 접속되는 인쇄회로테이프; 상기 인쇄회로테이프의 상면에 상기 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크; 상기 솔더마스크의 상면에 부착되는 방열판; 노출된 상기 회로패턴을 비롯한 상기 방열판의 상면에 형성된 전도성 접착제; 상기 전도성 접착제의 상면에 부착된 반도체 칩; 상기 반도체 칩과 상기 회로패턴을 접속시키는 전도성 와이어; 및 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로테이프의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지를 제공하는 것이다.In order to achieve the above object, a first aspect of the present invention provides a printed circuit tape including a circuit pattern formed on an upper surface and a plurality of external connection pads formed on a lower surface thereof to be electrically connected by via holes; A solder mask formed on the upper surface of the printed circuit tape to expose a predetermined region of the circuit pattern; A heat sink attached to an upper surface of the solder mask; A conductive adhesive formed on an upper surface of the heat sink including the exposed circuit pattern; A semiconductor chip attached to an upper surface of the conductive adhesive; A conductive wire connecting the semiconductor chip and the circuit pattern; And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit tape from an external environment.

본 발명의 제2 측면은, 코어층을 중심으로 상/하면에 다수의 회로패턴이 형성되고, 상기 상/하면의 회로패턴은 도전성 비아로 상호 연결된 판 형상의 인쇄회로기판; 상기 상/하면의 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크; 상기 상면의 회로패턴에 형성된 솔더마스크의 상면에 부착되는 방열판; 노출된 상기 상면의 회로패턴을 비롯한 상기 방열판의 상면에 형성된 전도성 접착제; 상기 전도성 접착제의 상면에 부착된 반도체 칩; 상기 반도체 칩과 상기 상면의 회로패턴을 접속시키는 전도성 와이어; 및 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로기판의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지를 제공하는 것이다.According to a second aspect of the present invention, a plurality of circuit patterns are formed on upper and lower surfaces of a core layer, and the upper and lower circuit patterns include a plate-shaped printed circuit board interconnected by conductive vias; A solder mask formed to expose a predetermined region of the upper and lower circuit patterns; A heat sink attached to an upper surface of the solder mask formed on the upper circuit pattern; A conductive adhesive formed on an upper surface of the heat sink including an exposed circuit pattern of the upper surface; A semiconductor chip attached to an upper surface of the conductive adhesive; A conductive wire connecting the semiconductor chip and the circuit pattern of the upper surface; And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit board from an external environment.

본 발명의 제3 측면은, 상면에 형성된 회로패턴과 저면에 형성된 다수의 외부 접속패드가 비아홀에 의해 전기적으로 접속되는 인쇄회로테이프; 상기 인쇄회로테이프의 상면에 상기 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크; 노출된 상기 회로패턴을 비롯한 상기 솔더마스크의 상면에 형성된 제1 전도성 접착제; 상기 제1 전도성 접착제의 상면에 부착되는 방열판; 상기 방열판의 상면에 형성된 제2 전도성 접착제; 상기 제2 전도성 접착제의 상면에 부착된 반도체 칩; 상기 반도체 칩과 상기 회로패턴을 접속시키는 전도성 와이어; 및 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로테이프의 표면 일부를 외부 환경으로부 터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지를 제공하는 것이다.According to a third aspect of the present invention, there is provided a printed circuit tape including a circuit pattern formed on an upper surface thereof and a plurality of external connection pads formed on a lower surface thereof electrically connected by via holes; A solder mask formed on the upper surface of the printed circuit tape to expose a predetermined region of the circuit pattern; A first conductive adhesive formed on an upper surface of the solder mask including the exposed circuit pattern; A heat sink attached to an upper surface of the first conductive adhesive; A second conductive adhesive formed on an upper surface of the heat sink; A semiconductor chip attached to an upper surface of the second conductive adhesive; A conductive wire connecting the semiconductor chip and the circuit pattern; And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit tape from an external environment.

본 발명의 제4 측면은, 코어층을 중심으로 상/하면에 다수의 회로패턴이 형성되고, 상기 상/하면의 회로패턴은 도전성 비아로 상호 연결된 판 형상의 인쇄회로기판; 상기 상/하면의 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크; 노출된 상기 상면의 회로패턴을 비롯한 상기 솔더마스크의 상면에 형성된 제1 전도성 접착제; 상기 제1 전도성 접착제의 상면에 부착되는 방열판; 상기 방열판의 상면에 형성된 제2 전도성 접착제; 상기 제2 전도성 접착제의 상면에 부착된 반도체 칩; 상기 반도체 칩과 상기 상면의 회로패턴을 접속시키는 전도성 와이어; 및 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로기판의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지를 제공하는 것이다.According to a fourth aspect of the present invention, a plurality of circuit patterns are formed on upper and lower surfaces of a core layer, and the upper and lower circuit patterns include a plate-shaped printed circuit board interconnected by conductive vias; A solder mask formed to expose a predetermined region of the upper and lower circuit patterns; A first conductive adhesive formed on an upper surface of the solder mask including an exposed circuit pattern of the upper surface; A heat sink attached to an upper surface of the first conductive adhesive; A second conductive adhesive formed on an upper surface of the heat sink; A semiconductor chip attached to an upper surface of the second conductive adhesive; A conductive wire connecting the semiconductor chip and the circuit pattern of the upper surface; And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit board from an external environment.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세하게 설명한다. 그러나, 다음에 예시하는 본 발명의 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 본 발명의 실시예는 당업계에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되어지는 것이다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

(제1 실시예)(First embodiment)

도 1은 본 발명의 제1 실시예에 따른 반도체 패키지를 설명하기 위한 단면도로서, 인쇄회로테이프(Printed Circuit Tape)를 이용한 볼 그리드 어레이(Ball Grid Array, BGA) 형태로 이루어진 것이다.FIG. 1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention and is formed in a ball grid array (BGA) using a printed circuit tape.

도 1을 참조하면, 본 발명의 제1 실시예에 따른 반도체 패키지는, 인쇄회로테이프(100), 솔더마스크(110), 접착테이프(120), 방열판(130), 전도성 접착제(140), 반도체 칩(150) 및 전도성 와이어(160), 패키지 몸체(170) 등을 포함하여 이루어진다.Referring to FIG. 1, the semiconductor package according to the first embodiment of the present invention may include a printed circuit tape 100, a solder mask 110, an adhesive tape 120, a heat sink 130, a conductive adhesive 140, and a semiconductor. The chip 150, the conductive wire 160, the package body 170, and the like are formed.

여기서, 인쇄회로테이프(100)는 가요성(flexible)을 가지며, 그 상면에는 다수의 회로패턴(101)이 형성되어 있으며, 일정한 간격으로 형성된 비아홀(Via Hole)(102)을 통해 저면에 다수의 외부 접속패드 예컨대, 도전성 솔더볼(Solder ball)(103)이 회로패턴(101)과 전기적으로 연결되도록 융착되어 있어, 차후 마더보드에 실장 가능하게 되어 있다.Here, the printed circuit tape 100 has a flexible (flexible), a plurality of circuit patterns 101 are formed on the upper surface of the printed circuit tape 100, a plurality of on the bottom surface via the via hole (102) formed at regular intervals An external connection pad, for example, a conductive solder ball 103 is fused to be electrically connected to the circuit pattern 101, so that it can be mounted on the motherboard later.

솔더마스크(Solder Mask)(110)는 통상의 절연성 물질로 이루어지는 바, 인쇄회로테이프(100)의 상면에 있는 회로패턴(101)의 소정영역만 노출되도록 형성되어 있다.The solder mask 110 is formed of a conventional insulating material, and is formed to expose only a predetermined region of the circuit pattern 101 on the upper surface of the printed circuit tape 100.

접착테이프(Adhesive tape)(120)는 방열판(130)을 솔더마스크(110)의 상면에 부착시키기 위한 것으로서, 방열판(130)과 솔더마스크(110)의 사이에 개재되어 있다. 이러한 접착테이프(120)는 통상의 열경화성 접착테이프 또는 양면 접착테이프로 이루어질 수 있으며, 이는 통상적인 대기 온도 하에서는 접착력이 약하지만 제조 공정 중 예컨대, 와이어 본딩(bonding) 시 히터 블록(Heater Block) 등에 안착되어 고온을 제공받게 되면 접착력이 극대화되는 것을 사용함이 바람직하다.The adhesive tape 120 is used to attach the heat sink 130 to the upper surface of the solder mask 110, and is interposed between the heat sink 130 and the solder mask 110. The adhesive tape 120 may be formed of a conventional thermosetting adhesive tape or a double-sided adhesive tape. The adhesive tape 120 may have a weak adhesive force under a normal air temperature, but may be seated on a heater block during manufacturing, for example, during wire bonding. When the high temperature is provided, it is preferable to use the adhesive force is maximized.

방열판(130)은 접착테이프(120)를 통해 솔더마스크(110)의 상면에 부착되어 반도체 패키지의 방열 효과를 향상시키기 위한 것으로서, 솔더마스크(110)에 의해 노출된 회로패턴(101)이 계속 남아 있도록 솔더마스크(110) 또는 접착테이프(120)의 형태와 동일하거나 유사하게 형성됨이 바람직하며, 그 재료로는 알루미늄, 알루미늄 합금 또는 구리합금 등을 주로 사용할 수 있다.The heat sink 130 is attached to the upper surface of the solder mask 110 through the adhesive tape 120 to improve the heat dissipation effect of the semiconductor package, and the circuit pattern 101 exposed by the solder mask 110 remains. It is preferable that the solder mask 110 or the adhesive tape 120 be formed in the same or similar form, and as the material, aluminum, aluminum alloy or copper alloy may be mainly used.

전도성 접착제(140)는 솔더마스크(110)에 의해 노출된 회로패턴(101)을 비롯한 방열판(130)의 상부면에 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다. 이와 같이 전도성 접착제(140)를 방열판(130) 및 인쇄회로테이프(100)의 회로패턴(101)에 직접적으로 접촉되도록 형성함으로써, 반도체 칩(150)의 구동 시 발생된 열을 보다 신속하게 외부로 방출할 수 있는 효과가 있다.The conductive adhesive 140 is formed on the upper surface of the heat sink 130, including the circuit pattern 101 exposed by the solder mask 110, and is preferably made of a conventional epoxy resin. As such, the conductive adhesive 140 is formed to be in direct contact with the heat sink 130 and the circuit pattern 101 of the printed circuit tape 100, thereby rapidly transferring heat generated when the semiconductor chip 150 is driven to the outside. There is an effect that can be released.

반도체 칩(Semiconductor Chip)(150)은 전도성 접착제(140)의 상면에 부착되어 있고, 각종 전자회로 및 배선 등이 집적되어 있으며, 그 표면에는 전도성 와이어(160)의 일단을 전기적으로 접속하기 위한 접속패드(미도시)가 형성되어 있다.The semiconductor chip 150 is attached to the upper surface of the conductive adhesive 140, and various electronic circuits and wirings are integrated, and a connection for electrically connecting one end of the conductive wire 160 to the surface thereof. A pad (not shown) is formed.

전도성 와이어(160)는 반도체 칩(150)과 회로패턴(101)을 전기적으로 접속시키기 위한 것으로써, 일단은 반도체 칩(150)의 표면에 형성된 접속패드에 연결되어 있으며, 그 타단은 회로패턴(101)의 표면에 형성된 금속(예컨대, Ni/Au 등) 단자(101a)에 연결되어 있다.The conductive wire 160 is for electrically connecting the semiconductor chip 150 and the circuit pattern 101, one end of which is connected to a connection pad formed on the surface of the semiconductor chip 150, and the other end thereof is a circuit pattern ( It is connected to a metal (eg, Ni / Au, etc.) terminal 101a formed on the surface of 101.

이러한 전도성 와이어(160)는 통상의 구리(Cu), 알루미늄(Al) 또는 금(Au) 중 어느 하나를 채용하는 바 바람직하게는 금(Au) 와이어를 채용함이 적합하다.The conductive wire 160 employs any one of ordinary copper (Cu), aluminum (Al), and gold (Au), and preferably employs gold (Au) wire.

패키지 몸체(170)는 반도체 칩(150), 전도성 와이어(160) 및 인쇄회로테이프(100)의 표면 일부를 외부 환경으로부터 보호하기 위하여 상기 소재들을 감싸도록 몰딩 형성되는 것으로서, 통상의 에폭시 몰딩 컴파운드(Epoxy Molding Compound, EMC)로 형성됨이 바람직하다.The package body 170 is formed by molding the semiconductor chip 150, the conductive wire 160, and the printed circuit tape 100 to surround the materials to protect a part of the surface from the external environment, and a conventional epoxy molding compound ( Epoxy Molding Compound (EMC).

전술한 바와 같이 구성된 반도체 패키지의 내부에서 발생되는 열을 방열판(130) 및 전도성 접착제(140)를 통해 인쇄회로테이프(100)의 회로패턴(101)에 직접적으로 전달되도록 함으로써, 반도체 칩(150)의 구동 시 내부에 발생된 열을 외부로 신속하게 방출할 수 있게 되어 신뢰성과 수명이 향상되는 효과가 있다.The semiconductor chip 150 may be directly transferred to the circuit pattern 101 of the printed circuit tape 100 through the heat sink 130 and the conductive adhesive 140 through the heat generated in the semiconductor package configured as described above. Since the heat generated inside can be quickly discharged to the outside during the operation of, the reliability and lifespan are improved.

(제2 실시예)(2nd Example)

도 2는 본 발명의 제2 실시예에 따른 반도체 패키지를 설명하기 위한 단면도로서, 인쇄회로테이프를 이용한 볼 그리드 어레이(BGA) 형태로 이루어진 것이며, 이는 본 발명의 제1 실시예에 따른 반도체 패키지의 구성과 유사하므로, 동일한 구성요소의 구체적인 설명은 본 발명의 제1 실시예를 참조하기로 한다.FIG. 2 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention, which is formed in the form of a ball grid array (BGA) using a printed circuit tape, which is a semiconductor package according to the first embodiment of the present invention. Since the configuration is similar, a detailed description of the same components will be referred to the first embodiment of the present invention.

도 2를 참조하면, 본 발명의 제2 실시예에 따른 반도체 패키지는, 인쇄회로테이프(200), 솔더마스크(210), 제1 전도성 접착제(220), 방열판(230), 제2 전도성 접착제(240), 반도체 칩(250) 및 전도성 와이어(260), 패키지 몸체(270) 등을 포함하여 이루어진다.2, the semiconductor package according to the second embodiment of the present invention may include a printed circuit tape 200, a solder mask 210, a first conductive adhesive 220, a heat sink 230, and a second conductive adhesive ( 240, the semiconductor chip 250, the conductive wire 260, the package body 270, and the like.

여기서, 인쇄회로테이프(200)의 상면에는 다수의 회로패턴(201)이 형성되어 있으며, 일정한 간격으로 형성된 비아홀(202)을 통해 저면에 다수의 외부 접속패드 예컨대, 도전성 솔더볼(203)이 회로패턴(201)과 전기적으로 연결되어 있다.Here, a plurality of circuit patterns 201 are formed on the upper surface of the printed circuit tape 200, and a plurality of external connection pads, for example, conductive solder balls 203, are formed on the bottom surface of the via holes 202 formed at regular intervals. It is electrically connected to 201.

솔더마스크(210)는 인쇄회로테이프(200)의 상면에 있는 회로패턴(201)의 소정영역만 노출되도록 형성되어 있다.The solder mask 210 is formed to expose only a predetermined region of the circuit pattern 201 on the upper surface of the printed circuit tape 200.

제1 전도성 접착제(220)는 솔더마스크(210)에 의해 노출된 회로패턴(201)을 비롯한 솔더마스크(210)의 상면에 직접 접촉되도록 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다.The first conductive adhesive 220 is formed to be in direct contact with the upper surface of the solder mask 210, including the circuit pattern 201 exposed by the solder mask 210, preferably made of a conventional epoxy resin (Epoxy) resin Do.

방열판(230)은 제1 전도성 접착제(220)의 상면에 부착되어 반도체 패키지의 방열 효과를 향상시키기 위한 것으로서, 제1 전도성 접착제(220)의 형태와 동일하거나 유사하게 형성됨이 바람직하다.The heat dissipation plate 230 is attached to the top surface of the first conductive adhesive 220 to improve the heat dissipation effect of the semiconductor package. The heat dissipation plate 230 may be formed to be the same as or similar to the shape of the first conductive adhesive 220.

제2 전도성 접착제(240)는 방열판(230)의 상면에 소정의 두께로 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다.The second conductive adhesive 240 is formed to a predetermined thickness on the upper surface of the heat sink 230, it is preferably made of a conventional epoxy (Epoxy) resin.

반도체 칩(250)은 제2 전도성 접착제(240)의 상면에 부착되어 있고, 각종 전자회로 및 배선 등이 집적되어 있으며, 그 표면에는 전도성 와이어(260)의 일단을 전기적으로 접속하기 위한 접속패드(미도시)가 형성되어 있다.The semiconductor chip 250 is attached to the upper surface of the second conductive adhesive 240, and various electronic circuits and wirings are integrated, and a connection pad for electrically connecting one end of the conductive wire 260 to the surface thereof ( Not shown) is formed.

전도성 와이어(260)는 반도체 칩(250)과 회로패턴(201)을 전기적으로 접속시키기 위한 것으로써, 일단은 반도체 칩(250)의 표면에 형성된 접속패드에 연결되어 있으며, 그 타단은 회로패턴(201)의 표면에 형성된 금속단자(201a)에 연결되 어 있다.The conductive wire 260 is for electrically connecting the semiconductor chip 250 and the circuit pattern 201, one end of which is connected to a connection pad formed on the surface of the semiconductor chip 250, and the other end thereof is a circuit pattern ( It is connected to the metal terminal 201a formed on the surface of 201).

패키지 몸체(270)는 반도체 칩(250), 전도성 와이어(260) 및 인쇄회로테이프(200)의 표면 일부를 외부 환경으로부터 보호하기 위하여 상기 소재들을 감싸도록 몰딩 형성되어 있다.The package body 270 is molded to enclose the materials to protect a part of the surface of the semiconductor chip 250, the conductive wire 260, and the printed circuit tape 200 from the external environment.

이와 같은 본 발명의 제2 실시예에 따른 반도체 패키지는 본 발명의 제1 실시예에 적용된 접착테이프(120, 도 1 참조)를 채용하지 않았으며, 방열판(230)의 상/하부에 각각 제1 및 제2 전도성 접착제(220 및 240)를 형성함과 아울러 제1 전도성 접착제(220)를 방열판(230) 및 인쇄회로테이프(200)의 회로패턴(201)에 직접적으로 접촉되도록 형성함으로써, 반도체 칩(250)의 구동 시 발생된 열을 보다 신속하게 외부로 방출할 수 있는 효과가 있다.The semiconductor package according to the second embodiment of the present invention does not employ the adhesive tape 120 (refer to FIG. 1) applied to the first embodiment of the present invention. And forming the second conductive adhesives 220 and 240 and forming the first conductive adhesive 220 to be in direct contact with the heat sink 230 and the circuit pattern 201 of the printed circuit tape 200. There is an effect that the heat generated during the operation of the 250 can be released more quickly to the outside.

(제3 실시예)(Third Embodiment)

도 3은 본 발명의 제3 실시예에 따른 반도체 패키지를 설명하기 위한 단면도로서, 인쇄회로기판(Printed Circuit Board, PCB)을 이용한 볼 그리드 어레이(Ball Grid Array, BGA) 형태로 이루어진 것이다.FIG. 3 is a cross-sectional view illustrating a semiconductor package according to a third embodiment of the present invention and is formed in a ball grid array (BGA) using a printed circuit board (PCB).

도 3을 참조하면, 본 발명의 제3 실시예에 따른 반도체 패키지는, 인쇄회로기판(300), 솔더마스크(310), 접착테이프(320), 방열판(330), 전도성 접착제(340), 반도체 칩(350) 및 전도성 와이어(360), 패키지 몸체(370) 등을 포함하여 이루어진다.Referring to FIG. 3, the semiconductor package according to the third embodiment of the present invention may include a printed circuit board 300, a solder mask 310, an adhesive tape 320, a heat sink 330, a conductive adhesive 340, and a semiconductor. The chip 350, the conductive wire 360, and the package body 370 may be formed.

여기서, 인쇄회로기판(300)은 예컨대, 열경화성 수지층 즉, 코어층(301)을 중심으로 그 상/하면에 각각 다수의 도전성 회로패턴(302)이 형성되어 있고, 상/하면의 회로패턴(302)은 도전성 비아(Via)(303)에 의해 상호 전기적으로 연결되어 있다. 또한, 코어층(301) 상면의 회로패턴(302)은 도전성 와이어(360)가 접속되는 금속(예컨대, Ni/Au 등)단자(302a)를 포함하고, 코어층(301) 하면의 회로패턴(302)은 다수의 도전성 솔더볼(304)이 융착되는 금속(예컨대, Ni/Au 등)단자(302b)를 포함한다.Here, the printed circuit board 300 has a plurality of conductive circuit patterns 302 formed on the upper and lower surfaces of the thermosetting resin layer, that is, the core layer 301, respectively, and the upper and lower circuit patterns ( 302 are electrically connected to each other by conductive vias 303. In addition, the circuit pattern 302 on the upper surface of the core layer 301 includes a metal (eg, Ni / Au, etc.) terminal 302a to which the conductive wire 360 is connected, and the circuit pattern (below the core layer 301) 302 includes a metal (eg Ni / Au) terminal 302b to which a plurality of conductive solder balls 304 are fused.

솔더마스크(Solder Mask)(310)는 통상의 절연성 물질로 이루어지는 바, 코어층(301)의 상/하면에 형성된 회로패턴(302)의 소정영역만 노출되도록 형성되어 있다.The solder mask 310 is made of a conventional insulating material, and is formed to expose only a predetermined region of the circuit pattern 302 formed on the upper and lower surfaces of the core layer 301.

즉, 솔더마스크(310)는 상/하면의 회로패턴(302)에 형성된 금속단자(302a 및 302b) 및 코어층(301)의 상면에 형성된 회로패턴(302)의 일부분이 노출되도록 코팅되어 외부 환경으로부터 보호되도록 되어 있다.That is, the solder mask 310 is coated to expose the metal terminals 302a and 302b formed on the upper and lower circuit patterns 302 and a portion of the circuit pattern 302 formed on the upper surface of the core layer 301 to expose the external environment. Protected from

접착테이프(Adhesive tape)(320)는 방열판(330)을 상면의 회로패턴(302)에 형성된 솔더마스크(310)의 상면에 부착시키기 위한 것으로서, 방열판(330)과 솔더마스크(310)의 사이에 개재되어 있다. 이러한 접착테이프(320)는 통상의 열경화성 접착테이프 또는 양면 접착테이프로 이루어질 수 있으며, 이는 통상적인 대기 온도 하에서는 접착력이 약하지만 제조 공정 중 예컨대, 와이어 본딩(bonding) 시 히터 블록(Heater Block) 등에 안착되어 고온을 제공받게 되면 접착력이 극대화되는 것을 사용함이 바람직하다.The adhesive tape 320 is for attaching the heat sink 330 to the top surface of the solder mask 310 formed on the circuit pattern 302 on the top surface. The adhesive tape 320 is disposed between the heat sink 330 and the solder mask 310. Intervened. The adhesive tape 320 may be formed of a conventional thermosetting adhesive tape or a double-sided adhesive tape. The adhesive tape 320 may have a weak adhesive force under a normal atmospheric temperature, but may be seated on a heater block during manufacturing, for example, during wire bonding. When the high temperature is provided, it is preferable to use the adhesive force is maximized.

방열판(330)은 접착테이프(320)를 통해 솔더마스크(310)의 상면에 부착되어 반도체 패키지의 방열 효과를 향상시키기 위한 것으로서, 솔더마스크(310)에 의해 노출된 회로패턴(301)이 계속 남아 있도록 솔더마스크(310) 또는 접착테이프(320)의 형태와 동일하거나 유사하게 형성됨이 바람직하며, 그 재료로는 알루미늄, 알루미늄 합금 또는 구리합금 등을 주로 사용할 수 있다.The heat sink 330 is attached to the upper surface of the solder mask 310 through the adhesive tape 320 to improve the heat dissipation effect of the semiconductor package, and the circuit pattern 301 exposed by the solder mask 310 remains. It is preferable that the solder mask 310 or the adhesive tape 320 be formed in the same or similar form, and as the material, aluminum, aluminum alloy or copper alloy may be mainly used.

전도성 접착제(340)는 솔더마스크(310)에 의해 노출된 회로패턴(302)을 비롯한 방열판(330)의 상부면에 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다. 이와 같이 전도성 접착제(340)를 방열판(330) 및 인쇄회로기판(300)의 회로패턴(302)에 직접적으로 접촉되도록 형성함으로써, 반도체 칩(350)의 구동 시 발생된 열을 보다 신속하게 외부로 방출할 수 있는 효과가 있다.The conductive adhesive 340 is formed on the upper surface of the heat sink 330 including the circuit pattern 302 exposed by the solder mask 310, and is preferably made of a conventional epoxy resin. As such, the conductive adhesive 340 is formed to be in direct contact with the heat dissipation plate 330 and the circuit pattern 302 of the printed circuit board 300, thereby rapidly transferring heat generated when the semiconductor chip 350 is driven to the outside. There is an effect that can be released.

반도체 칩(Semiconductor Chip)(350)은 전도성 접착제(340)의 상면에 부착되어 있고, 각종 전자회로 및 배선 등이 집적되어 있으며, 그 표면에는 전도성 와이어(360)의 일단을 전기적으로 접속하기 위한 접속패드(미도시)가 형성되어 있다.The semiconductor chip 350 is attached to the upper surface of the conductive adhesive 340, and various electronic circuits and wirings are integrated, and a connection for electrically connecting one end of the conductive wire 360 to the surface thereof. A pad (not shown) is formed.

전도성 와이어(360)는 반도체 칩(350)과 회로패턴(302)을 전기적으로 접속시키기 위한 것으로써, 일단은 반도체 칩(350)의 표면에 형성된 접속패드에 연결되어 있으며, 그 타단은 상면 회로패턴(302)의 표면에 형성된 금속(Ni/Au)단자(302a)에 연결되어 있다.The conductive wire 360 is for electrically connecting the semiconductor chip 350 and the circuit pattern 302, one end of which is connected to a connection pad formed on the surface of the semiconductor chip 350, and the other end thereof is an upper circuit pattern. It is connected to the metal (Ni / Au) terminal 302a formed on the surface of 302.

이러한 전도성 와이어(360)는 통상의 구리(Cu), 알루미늄(Al) 또는 금(Au) 중 어느 하나를 채용하는 바 바람직하게는 금(Au) 와이어를 채용함이 적합하다.The conductive wire 360 employs any one of ordinary copper (Cu), aluminum (Al) or gold (Au), and preferably adopts gold (Au) wire.

패키지 몸체(370)는 반도체 칩(350), 전도성 와이어(360) 및 인쇄회로기판(300)의 표면 일부를 외부 환경으로부터 보호하기 위하여 상기 소재들을 감싸도록 몰딩 형성되는 것으로서, 통상의 에폭시 몰딩 컴파운드(Epoxy Molding Compound, EMC)로 형성됨이 바람직하다.The package body 370 is formed by molding the semiconductor chip 350, the conductive wire 360 and the printed circuit board 300 to surround the materials to protect a part of the surface from the external environment, and a conventional epoxy molding compound ( Epoxy Molding Compound (EMC).

전술한 바와 같이 구성된 반도체 패키지의 내부에서 발생되는 열을 방열판(330) 및 전도성 접착제(340)를 통해 인쇄회로기판(300)의 회로패턴(302)에 직접적으로 전달되도록 함으로써, 반도체 칩(350)의 구동 시 발생된 열을 외부로 신속하게 방출할 수 있게 되어 신뢰성과 수명이 향상되는 효과가 있다.The semiconductor chip 350 may be directly transferred to the circuit pattern 302 of the printed circuit board 300 through the heat dissipation plate 330 and the conductive adhesive 340 through the heat generated in the semiconductor package configured as described above. It is possible to quickly release the heat generated during the operation of the outside to improve the reliability and lifespan.

(제4 실시예)(Example 4)

도 4는 본 발명의 제4 실시예에 따른 반도체 패키지를 설명하기 위한 단면도로서, 인쇄회로기판(PCB)을 이용한 볼 그리드 어레이(BGA) 형태로 이루어진 것이며, 이는 본 발명의 제3 실시예에 따른 반도체 패키지의 구성과 유사하므로, 동일한 구성요소의 구체적인 설명은 본 발명의 제3 실시예를 참조하기로 한다.FIG. 4 is a cross-sectional view illustrating a semiconductor package according to a fourth embodiment of the present invention, which is formed in the form of a ball grid array (BGA) using a printed circuit board (PCB), and according to the third embodiment of the present invention. Since the configuration of the semiconductor package is similar, a detailed description of the same components will be referred to the third embodiment of the present invention.

도 4를 참조하면, 본 발명의 제4 실시예에 따른 반도체 패키지는, 인쇄회로기판(400), 솔더마스크(410), 제1 전도성 접착제(420), 방열판(430), 제2 전도성 접착제(440), 반도체 칩(450) 및 전도성 와이어(460), 패키지 몸체(470) 등을 포함하여 이루어진다.Referring to FIG. 4, the semiconductor package according to the fourth exemplary embodiment of the present invention may include a printed circuit board 400, a solder mask 410, a first conductive adhesive 420, a heat sink 430, and a second conductive adhesive ( 440, the semiconductor chip 450, the conductive wire 460, the package body 470, and the like.

여기서, 인쇄회로기판(400)은 예컨대, 열경화성 수지층 즉, 코어층(401)을 중심으로 그 상/하면에 각각 다수의 도전성 회로패턴(402)이 형성되어 있고, 상/ 하면의 회로패턴(402)은 도전성 비아(Via)(403)에 의해 상호 전기적으로 연결되어 있다. 또한, 코어층(401) 상면의 회로패턴(402)은 도전성 와이어(460)가 접속되는 금속단자(402a)를 포함하고, 코어층(401) 하면의 회로패턴(402)은 다수의 도전성 솔더볼(404)이 융착되는 금속단자(402b)를 포함한다.Here, the printed circuit board 400 has a plurality of conductive circuit patterns 402 formed on the upper and lower surfaces of the thermosetting resin layer, that is, the core layer 401, respectively, and the upper and lower circuit patterns ( The 402 are electrically connected to each other by conductive vias 403. In addition, the circuit pattern 402 on the upper surface of the core layer 401 includes a metal terminal 402a to which the conductive wire 460 is connected, and the circuit pattern 402 on the lower surface of the core layer 401 includes a plurality of conductive solder balls ( 404 includes a metal terminal 402b to be fused.

솔더마스크(410)는 코어층(401)의 상/하면에 형성된 회로패턴(402)의 소정영역만 노출되도록 형성되어 있다.The solder mask 410 is formed to expose only a predetermined region of the circuit pattern 402 formed on the upper and lower surfaces of the core layer 401.

제1 전도성 접착제(420)는 솔더마스크(410)에 의해 노출된 회로패턴(402)을 비롯한 솔더마스크(410)의 상면에 직접 접촉되도록 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다.The first conductive adhesive 420 is formed to be in direct contact with the upper surface of the solder mask 410 including the circuit pattern 402 exposed by the solder mask 410, it is preferably made of a conventional epoxy resin (Epoxy) resin Do.

방열판(430)은 제1 전도성 접착제(420)의 상면에 부착되어 반도체 패키지의 방열 효과를 향상시키기 위한 것으로서, 제1 전도성 접착제(420)의 형태와 동일하거나 유사하게 형성됨이 바람직하다.The heat sink 430 is attached to the top surface of the first conductive adhesive 420 to improve the heat dissipation effect of the semiconductor package, and is preferably formed in the same or similar shape as that of the first conductive adhesive 420.

제2 전도성 접착제(440)는 방열판(430)의 상면에 소정의 두께로 형성되어 있으며, 통상의 에폭시(Epoxy) 수지로 이루어짐이 바람직하다.The second conductive adhesive 440 is formed to a predetermined thickness on the upper surface of the heat dissipation plate 430, it is preferably made of a conventional epoxy (Epoxy) resin.

반도체 칩(450)은 제2 전도성 접착제(440)의 상면에 부착되어 있고, 각종 전자회로 및 배선 등이 집적되어 있으며, 그 표면에는 전도성 와이어(460)의 일단을 전기적으로 접속하기 위한 접속패드(미도시)가 형성되어 있다.The semiconductor chip 450 is attached to the upper surface of the second conductive adhesive 440, and various electronic circuits and wirings are integrated, and a connection pad for electrically connecting one end of the conductive wire 460 to the surface thereof ( Not shown) is formed.

전도성 와이어(460)는 반도체 칩(450)과 회로패턴(402)을 전기적으로 접속시키기 위한 것으로써, 일단은 반도체 칩(450)의 표면에 형성된 접속패드에 연결되어 있으며, 그 타단은 상면 회로패턴(402)의 표면에 형성된 금속단자(402a)에 연결되어 있다.The conductive wire 460 is for electrically connecting the semiconductor chip 450 and the circuit pattern 402, one end of which is connected to a connection pad formed on the surface of the semiconductor chip 450, and the other end thereof is an upper circuit pattern. It is connected to the metal terminal 402a formed on the surface of 402.

패키지 몸체(470)는 반도체 칩(450), 전도성 와이어(460) 및 인쇄회로기판(400)의 표면 일부를 외부 환경으로부터 보호하기 위하여 상기 소재들을 감싸도록 몰딩 형성되어 있다.The package body 470 is molded to enclose the materials in order to protect a part of the surface of the semiconductor chip 450, the conductive wire 460, and the printed circuit board 400 from the external environment.

이와 같은 본 발명의 제4 실시예에 따른 반도체 패키지는 본 발명의 제3 실시예에 적용된 접착테이프(320, 도 3 참조)를 채용하지 않았으며, 방열판(430)의 상/하부에 각각 제1 및 제2 전도성 접착제(420 및 440)를 형성함과 아울러 제1 전도성 접착제(420)를 방열판(430) 및 인쇄회로기판(400)의 회로패턴(402)에 직접적으로 접촉되도록 형성함으로써, 반도체 칩(450)의 구동 시 발생된 열을 보다 신속하게 외부로 방출할 수 있는 효과가 있다.The semiconductor package according to the fourth embodiment of the present invention does not employ the adhesive tape 320 (refer to FIG. 3) applied to the third embodiment of the present invention. And forming the second conductive adhesives 420 and 440 and forming the first conductive adhesive 420 in direct contact with the heat sink 430 and the circuit pattern 402 of the printed circuit board 400. There is an effect that can be released to the outside heat generated during the operation of 450 more quickly.

전술한 바와 같이 본 발명의 실시예들에 따른 반도체 패키지는 멀티칩 및 시스템 인 패키지(System in Package, SiP)와 같이 집적도와 용량이 크고 동작 속도가 빠르며 전력 소모가 많은 패키지에서 특히 유용하다.As described above, the semiconductor package according to the embodiments of the present invention is particularly useful in packages with high integration, high capacity, high operation speed, and high power consumption, such as multi-chip and system in package (SiP).

전술한 본 발명에 따른 반도체 패키지에 대한 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 특허청구범위와 발명의 상세한 설명 및 첨부한 도면의 범위 안에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 본 발명에 속한다.While a preferred embodiment of the semiconductor package according to the present invention has been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. This also belongs to the present invention.

이상에서 설명한 바와 같은 본 발명의 반도체 패키지에 따르면, 에폭시와 같은 열 매개 물질인 전도성 접착제로 내장된 방열판과 인쇄회로테이프 또는 인쇄회로기판에 직접적으로 연결시킴으로써, 반도체 칩의 구동 시 발생한 열을 외부로 신속하게 방출하여 신뢰성과 수명이 향상되는 이점이 있다.According to the semiconductor package of the present invention as described above, by directly connecting to a heat sink and a printed circuit tape or a printed circuit board embedded with a conductive adhesive, a thermal medium such as epoxy, heat generated when driving the semiconductor chip to the outside It releases quickly, which improves reliability and lifespan.

Claims (7)

상면에 형성된 회로패턴과 저면에 형성된 다수의 외부 접속패드가 비아홀에 의해 전기적으로 접속되는 인쇄회로테이프;A printed circuit tape on which a circuit pattern formed on an upper surface and a plurality of external connection pads formed on a lower surface are electrically connected by via holes; 상기 인쇄회로테이프의 상면에 상기 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크;A solder mask formed on the upper surface of the printed circuit tape to expose a predetermined region of the circuit pattern; 상기 솔더마스크의 상면에 부착되는 방열판;A heat sink attached to an upper surface of the solder mask; 노출된 상기 회로패턴을 비롯한 상기 방열판의 상면에 형성된 전도성 접착제;A conductive adhesive formed on an upper surface of the heat sink including the exposed circuit pattern; 상기 전도성 접착제의 상면에 부착된 반도체 칩;A semiconductor chip attached to an upper surface of the conductive adhesive; 상기 반도체 칩과 상기 회로패턴을 접속시키는 전도성 와이어; 및A conductive wire connecting the semiconductor chip and the circuit pattern; And 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로테이프의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지.And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit tape from an external environment. 코어층을 중심으로 상/하면에 다수의 회로패턴이 형성되고, 상기 상/하면의 회로패턴은 도전성 비아로 상호 연결된 판 형상의 인쇄회로기판;A plurality of circuit patterns are formed on upper and lower surfaces of the core layer, and the upper and lower circuit patterns include a plate-shaped printed circuit board interconnected by conductive vias; 상기 상/하면의 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크;A solder mask formed to expose a predetermined region of the upper and lower circuit patterns; 상기 상면의 회로패턴에 형성된 솔더마스크의 상면에 부착되는 방열판;A heat sink attached to an upper surface of the solder mask formed on the upper circuit pattern; 노출된 상기 상면의 회로패턴을 비롯한 상기 방열판의 상면에 형성된 전도 성 접착제;A conductive adhesive formed on an upper surface of the heat sink including an exposed circuit pattern of the upper surface; 상기 전도성 접착제의 상면에 부착된 반도체 칩;A semiconductor chip attached to an upper surface of the conductive adhesive; 상기 반도체 칩과 상기 상면의 회로패턴을 접속시키는 전도성 와이어; 및A conductive wire connecting the semiconductor chip and the circuit pattern of the upper surface; And 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로기판의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지.And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit board from an external environment. 제 1 항 또는 제 2 항에 있어서, 상기 전도성 접착제는 에폭시(Epoxy) 수지로 이루어진 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1 or 2, wherein the conductive adhesive is made of epoxy resin. 제 1 항 또는 제 2 항에 있어서, 상기 솔더마스크와 상기 방열판은 일정두께의 접착테이프를 이용하여 부착되는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1 or 2, wherein the solder mask and the heat sink are attached using an adhesive tape having a predetermined thickness. 상면에 형성된 회로패턴과 저면에 형성된 다수의 외부 접속패드가 비아홀에 의해 전기적으로 접속되는 인쇄회로테이프;A printed circuit tape on which a circuit pattern formed on an upper surface and a plurality of external connection pads formed on a lower surface are electrically connected by via holes; 상기 인쇄회로테이프의 상면에 상기 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크;A solder mask formed on the upper surface of the printed circuit tape to expose a predetermined region of the circuit pattern; 노출된 상기 회로패턴을 비롯한 상기 솔더마스크의 상면에 형성된 제1 전도성 접착제;A first conductive adhesive formed on an upper surface of the solder mask including the exposed circuit pattern; 상기 제1 전도성 접착제의 상면에 부착되는 방열판;A heat sink attached to an upper surface of the first conductive adhesive; 상기 방열판의 상면에 형성된 제2 전도성 접착제;A second conductive adhesive formed on an upper surface of the heat sink; 상기 제2 전도성 접착제의 상면에 부착된 반도체 칩;A semiconductor chip attached to an upper surface of the second conductive adhesive; 상기 반도체 칩과 상기 회로패턴을 접속시키는 전도성 와이어; 및A conductive wire connecting the semiconductor chip and the circuit pattern; And 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로테이프의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지.And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit tape from an external environment. 코어층을 중심으로 상/하면에 다수의 회로패턴이 형성되고, 상기 상/하면의 회로패턴은 도전성 비아로 상호 연결된 판 형상의 인쇄회로기판;A plurality of circuit patterns are formed on upper and lower surfaces of the core layer, and the upper and lower circuit patterns include a plate-shaped printed circuit board interconnected by conductive vias; 상기 상/하면의 회로패턴의 소정영역이 노출되도록 형성된 솔더마스크;A solder mask formed to expose a predetermined region of the upper and lower circuit patterns; 노출된 상기 상면의 회로패턴을 비롯한 상기 솔더마스크의 상면에 형성된 제1 전도성 접착제;A first conductive adhesive formed on an upper surface of the solder mask including an exposed circuit pattern of the upper surface; 상기 제1 전도성 접착제의 상면에 부착되는 방열판;A heat sink attached to an upper surface of the first conductive adhesive; 상기 방열판의 상면에 형성된 제2 전도성 접착제;A second conductive adhesive formed on an upper surface of the heat sink; 상기 제2 전도성 접착제의 상면에 부착된 반도체 칩;A semiconductor chip attached to an upper surface of the second conductive adhesive; 상기 반도체 칩과 상기 상면의 회로패턴을 접속시키는 전도성 와이어; 및A conductive wire connecting the semiconductor chip and the circuit pattern of the upper surface; And 상기 반도체 칩, 상기 전도성 와이어 및 상기 인쇄회로기판의 표면 일부를 외부 환경으로부터 보호하기 위하여 몰딩 형성되는 패키지 몸체를 포함하는 반도체 패키지.And a package body molded to protect a portion of a surface of the semiconductor chip, the conductive wire, and the printed circuit board from an external environment. 제 5 항 또는 제 6 항에 있어서, 상기 제1 및 제2 전도성 접착제는 에폭시(Epoxy) 수지로 이루어진 것을 특징으로 하는 반도체 패키지.7. The semiconductor package of claim 5 or 6, wherein the first and second conductive adhesives are made of epoxy resin.
KR1020060047966A 2006-05-29 2006-05-29 Semiconductor package KR100727728B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060047966A KR100727728B1 (en) 2006-05-29 2006-05-29 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060047966A KR100727728B1 (en) 2006-05-29 2006-05-29 Semiconductor package

Publications (1)

Publication Number Publication Date
KR100727728B1 true KR100727728B1 (en) 2007-06-13

Family

ID=38359233

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060047966A KR100727728B1 (en) 2006-05-29 2006-05-29 Semiconductor package

Country Status (1)

Country Link
KR (1) KR100727728B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590460A (en) * 1991-09-26 1993-04-09 Sharp Corp Manufacture of semiconductor device
KR20040061860A (en) * 2002-12-31 2004-07-07 주식회사 칩팩코리아 Tecsp

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590460A (en) * 1991-09-26 1993-04-09 Sharp Corp Manufacture of semiconductor device
KR20040061860A (en) * 2002-12-31 2004-07-07 주식회사 칩팩코리아 Tecsp

Similar Documents

Publication Publication Date Title
KR100698526B1 (en) Substrate having heat spreading layer and semiconductor package using the same
US6265771B1 (en) Dual chip with heat sink
US7561436B2 (en) Circuit assembly with surface-mount IC package and heat sink
KR100632459B1 (en) Heat-dissipating semiconductor package and manufacturing method
KR20060100250A (en) Semiconductor device
US7361995B2 (en) Molded high density electronic packaging structure for high performance applications
JP2012015225A (en) Semiconductor device
US6819565B2 (en) Cavity-down ball grid array semiconductor package with heat spreader
US7564128B2 (en) Fully testable surface mount die package configured for two-sided cooling
KR20040059742A (en) Packaging method of multi chip module for semiconductor
US20040150098A1 (en) Multi-stack chip size packaging method
KR20030045950A (en) Multi chip package comprising heat sinks
US6784536B1 (en) Symmetric stack up structure for organic BGA chip carriers
US7235889B2 (en) Integrated heatspreader for use in wire bonded ball grid array semiconductor packages
JP2007036035A (en) Semiconductor device
KR100727728B1 (en) Semiconductor package
JP2010219554A (en) Semiconductor device and electronic controller using the same
KR200254077Y1 (en) A printed circuit board for a window chip scale package having copper lands for heat radiation
KR100203932B1 (en) BGA package having thermal emissive substrate attached to chip
KR100388211B1 (en) Multi chip package
US20230069969A1 (en) Package for several integrated circuits
KR20100066941A (en) Printed circuit board and semiconductor package using the same
TWI643297B (en) Semiconductor package having internal heat sink
KR20040061860A (en) Tecsp
KR100233865B1 (en) Ball grid array of heat sink mount and semiconductor package method for manufacture of the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130426

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20140602

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20150602

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20160517

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20170519

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee