KR100388211B1 - Multi chip package - Google Patents
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- KR100388211B1 KR100388211B1 KR10-2001-0038553A KR20010038553A KR100388211B1 KR 100388211 B1 KR100388211 B1 KR 100388211B1 KR 20010038553 A KR20010038553 A KR 20010038553A KR 100388211 B1 KR100388211 B1 KR 100388211B1
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Abstract
본 발명은 고밀도 실장이 가능하면서 전기적 특성 및 열방출 특성을 개선시킨 멀티 칩 패키지를 개시하며, 개시된 본 발명의 멀티 칩 패키지는, 본딩 패드 배치면이 마주 보도록 이격 배치된 상,하 반도체 칩; 상기 각 반도체 칩의 본딩 패드 배치면 상에 상기 본딩 패드를 노출시키도록 각각 형성된 제1절연층; 상기 하부 반도체 칩의 제1절연층 상에 형성되며, 타단에 범프 랜드와 와이어 본딩 랜드를 갖으면서 일단이 본딩 패드와 연결되는 제1금속패턴과 일단이 본딩 패드와 연결되지 않는 연결 패턴; 상기 상부 반도체 칩의 제1절연층 상에 일단이 본딩 패드와 연결되면서 타단에 범프 랜드를 갖는 제2금속패턴; 상기 각 반도체 칩의 제1절연층 상에 상기 범프 랜드 및 와이어 본딩 랜드를 노출시키도록 각각 형성된 제2절연층; 상기 대응하는 제1금속패턴 및 연결 패턴의 범프 랜드와 제2금속패턴의 범프 랜드 사이에 개재되어 그들간을 접속시키는 솔더 범프; 상기 하부 반도체 칩이 부착되며, 회로단자가 구비된 상측면과 볼 랜드가 구비된 하측면 및 상기 회로단자와 볼 랜드를 연결하는 회로패턴을 갖는 기판; 상기 제2금속패턴의 와이어 본딩 랜드와 상기 기판의 회로단자간을 연결하는 금속 와이어; 및 상기 상,하 반도체 칩들 및 금속 와이어를 포함한 기판의 상면을 봉지하는 봉지제를 포함한다.The present invention discloses a multi-chip package capable of high-density mounting and improving electrical characteristics and heat dissipation characteristics. The disclosed multi-chip package includes: upper and lower semiconductor chips spaced apart from each other so that bonding pad arrangement surfaces face each other; First insulating layers formed on the bonding pad arrangement surfaces of the semiconductor chips to expose the bonding pads; A first metal pattern formed on the first insulating layer of the lower semiconductor chip, the bump pattern and the wire bonding land at one end thereof, and one end of which is connected to the bonding pad and one end of which is not connected to the bonding pad; A second metal pattern having one end connected to a bonding pad on the first insulating layer of the upper semiconductor chip and having a bump land at the other end thereof; Second insulating layers respectively formed to expose the bump lands and the wire bonding lands on the first insulating layers of the semiconductor chips; Solder bumps interposed between the bump lands of the corresponding first metal pattern and the connection pattern and the bump lands of the second metal pattern to connect them; A substrate having the lower semiconductor chip attached thereto, the substrate having an upper side having a circuit terminal, a lower side having a ball land, and a circuit pattern connecting the circuit terminal and the ball land; A metal wire connecting the wire bonding land of the second metal pattern to a circuit terminal of the substrate; And an encapsulant encapsulating an upper surface of the substrate including the upper and lower semiconductor chips and the metal wire.
Description
본 발명은 멀티 칩 패키지에 관한 것으로, 보다 상세하게는, 고밀도 실장이 가능하면서 전기적 특성 및 열방출 특성이 개선된 멀티 칩 패키지에 관한 것이다.The present invention relates to a multi-chip package, and more particularly, to a multi-chip package capable of high-density mounting and improved electrical characteristics and heat dissipation characteristics.
주지된 바와 같이, 패키징 기술은 한정된 크기의 기판에 더 많은 수의 패키지를 실장할 수 있는 방향으로, 즉, 패키지의 크기를 줄이는 방향으로 진행되어 왔다. 그 예로, 패키지의 전체 크기에 대해서 반도체 칩의 크기가 80% 정도를 차지하는 칩 스케일 패키지(Chip Scale Package)가 제안되었으며, 최근에는, 패키지의 전체 크기가 반도체 칩의 크기와 동일하면서, 공정 상의 잇점을 얻을 수 있는 웨이퍼 레벨 패키지에 대한 연구가 진행되고 있다.As is well known, packaging techniques have been advanced in the direction of mounting a larger number of packages on a limited size substrate, i.e., reducing the size of the package. For example, a chip scale package has been proposed, in which a semiconductor chip occupies about 80% of the total size of the package. Recently, the overall size of the package is the same as the size of the semiconductor chip, and the advantages in the process are provided. Research is ongoing on wafer level packages that can be obtained.
그러나, 상기 칩 스케일 패키지는 그 크기 감소를 통해 실장 가능한 패키지의 수를 증대시킬 수 있다는 잇점은 있지만, 전형적인 반도체 패키지와 마찬가지로, 하나의 반도체 칩이 탑재되기 때문에 그 용량 증대에는 한계가 있고, 그래서, 대용량 시스템의 구현에 어려움이 있다.However, although the chip scale package has an advantage of increasing the number of packages that can be mounted by reducing the size thereof, as in a typical semiconductor package, there is a limit in increasing its capacity since one semiconductor chip is mounted. It is difficult to implement a large capacity system.
따라서, 패키지의 크기 감소와 더불어, 패키지의 용량 증대 측면을 고려하여하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 적층 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근들어 활발하게 진행되고 있다.Therefore, in consideration of the size reduction of the package and increasing the capacity of the package, a study on a stack package and a multi chip package that mounts two or three semiconductor chips of one package has been recently conducted. For example, it is actively progressing.
여기서, 상기 멀티 칩 패키지는 서로 다른 기능을 갖는 두 개 이상의 반도체 칩들을 하나의 패키지로 제작한 것이며, 통상, 2∼3개의 반도체 칩들을 기판 상에 단순 나열하는 방식으로 패키징한다.Here, the multi-chip package is made of two or more semiconductor chips having different functions into one package, and typically, two to three semiconductor chips are packaged by simply arranging them on a substrate.
도 1은 종래의 멀티 칩 패키지를 도시한 단면도이다. 도시된 바와 같이, 서로 다른 2개의 반도체 칩들(1a, 1b)이 접착제(6)를 매개로해서 회로패턴(도시안됨)이 구비된 기판(2) 상에 나란히 부착되고, 상기 반도체 칩들(1a, 1b)과 기판(2)은 금속와이어(3)에 의해 전기적으로 연결된다. 그리고, 상기 반도체 칩들(1a, 1b) 및 금속와이어(3)를 포함한 기판(2)의 상부면은 외부로부터 보호되도록 에폭시 몰딩 컴파운드(Epoxy Molding Compound : 이하, EMC)와 같은 봉지제(4)로 봉지되고, 상기 기판(2)의 하부면에는 외부와의 전기적 접속 수단으로서 기능하는 솔더 볼(5)이 부착된다.1 is a cross-sectional view showing a conventional multi-chip package. As shown, two different semiconductor chips 1a, 1b are attached side by side on a substrate 2 with a circuit pattern (not shown) via an adhesive 6, and the semiconductor chips 1a, 1b) and substrate 2 are electrically connected by metal wires 3. In addition, the upper surface of the substrate 2 including the semiconductor chips 1a and 1b and the metal wires 3 may be encapsulated with an encapsulant 4 such as an epoxy molding compound (EMC) so as to be protected from the outside. It is sealed, and the lower surface of the said board | substrate 2 is attached the solder ball 5 which functions as an electrical connection means with the outside.
그러나, 전술한 바와 같은 종래의 멀티 칩 패키지는 2개의 칩이 기판 상에 나란히 배열되는 것으로 인해 크기가 크며, 따라서, 인쇄회로기판(Printed Circuit Board : 이하, PCB)에의 실장시에 고밀도 실장이 어렵다는 문제점이 있다.However, the conventional multi-chip package as described above is large in size due to the two chips arranged side by side on the substrate, and therefore, it is difficult to mount a high density at the time of mounting on a printed circuit board (PCB). There is a problem.
또한, 종래의 멀티 칩 패키지는 칩과 기판간의 전기적 연결을 금속와이어를 사용하므로, 전기적 특성이 양호하지 못한 문제점이 있다.In addition, the conventional multi-chip package has a problem that the electrical characteristics are not good because the metal wire is used for the electrical connection between the chip and the substrate.
게다가, 종래의 멀티 칩 패키지는 EMC로 봉지되어 있으므로, 칩에서 발생하는 열을 외부로 방출하는데 용이하지 못한 문제점이 있다.In addition, since the conventional multi-chip package is encapsulated with EMC, there is a problem that it is not easy to dissipate heat generated from the chip to the outside.
따라서, 본 발명은 종래의 멀티 칩 패키지가 안고 있는 제반 문제점을 해소하기 위해 안출된 것으로서, 고밀도 실장이 가능하도록 한 멀티 칩 패키지를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a multi-chip package capable of high-density mounting, which is devised to solve various problems of the conventional multi-chip package.
또한, 본 발명은 전기적 특성을 확보한 멀티 칩 패키지를 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a multi-chip package having secured electrical characteristics.
게다가, 본 발명은 열방출 특성을 향상시킨 멀티 칩 패키지를 제공함에 그 또 다른 목적이 있다.In addition, another object of the present invention is to provide a multi-chip package having improved heat dissipation characteristics.
도 1은 종래의 멀티 칩 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional multi-chip package.
도 2a 내지 도 2g는 본 발명의 실시예 1에 따른 멀티 칩 패키지의 제조 공정 순서대로 도시한 단면도.2A through 2G are cross-sectional views sequentially illustrating a manufacturing process of a multi-chip package according to Embodiment 1 of the present invention.
도 3은 도 2a에 대응하는 하부 반도체 칩의 평면도.3 is a plan view of a lower semiconductor chip corresponding to FIG. 2A.
도 4는 도 2c에 대응하는 상부 반도체 칩의 평면도.4 is a plan view of an upper semiconductor chip corresponding to FIG. 2C.
도 5는 본 발명의 실시예 2에 따른 멀티 칩 패키지를 도시한 단면도.5 is a sectional view showing a multi-chip package according to a second embodiment of the present invention.
도 6은 본 발명의 실시예 3에 따른 멀티 칩 패키지를 도시한 단면도.6 is a cross-sectional view showing a multi-chip package according to a third embodiment of the present invention.
도 7은 본 발명의 실시예 4에 따른 멀티 칩 패키지를 도시한 단면도.7 is a sectional view showing a multi-chip package according to a fourth embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 하부 반도체 칩 11,21,71 : 본딩 패드10: lower semiconductor chip 11,21,71: bonding pad
12,22 : 제1절연층 13 : 제1금속패턴12,22: first insulating layer 13: first metal pattern
14 : 연결 패턴 13a,23a : 범프 랜드14: connection pattern 13a, 23a: bump land
13b : 와이어 본딩 랜드 15,25 : 제2절연층13b: wire bonding land 15, 25: second insulating layer
20,70 : 상부 반도체 칩 26 : 솔더 범프20,70: upper semiconductor chip 26: solder bump
31 : 베이스 기판 32,33 : 기판의 절연층31 base substrate 32,33 insulation layer of substrate
34 : 회로패턴 35 : 회로단자34: circuit pattern 35: circuit terminal
36 : 볼 랜드 40 : 기판36: Borland 40: Substrate
42,52 : 접착제 44 : 금속 와이어42,52: adhesive 44: metal wire
46 : 봉지제 48 : 솔더 볼46: sealing agent 48: solder ball
50 : 멀티 칩 패키지 60 : 방열판50: multi chip package 60: heat sink
상기와 같은 목적을 달성하기 위한 본 발명에 따른 멀티 칩 패키지는, 본딩 패드 배치면이 마주 보도록 이격 배치된 상,하 반도체 칩; 상기 각 반도체 칩의 본딩 패드 배치면 상에 상기 본딩 패드를 노출시키도록 각각 형성된 제1절연층; 상기 하부 반도체 칩의 제1절연층 상에 형성되며, 일단이 본딩 패드와 연결되면서 일측 및 타측 가장자리로 번갈아 연장 배치된 타단에 범프 랜드와 와이어 본딩 랜드를 갖는 제1금속패턴과, 상기 제1금속패턴이 연장되지 않은 가장자리 부분에 섬 형태로 형성되면서 범프 랜드와 와이어 본딩 랜드를 갖는 연결 패턴; 상기 상부 반도체 칩의 제1절연층 상에 일단이 본딩 패드와 연결되면서 일측 및 타측 가장자리로 번갈아 연장 배치되고, 타단에 범프 랜드를 갖는 제2금속패턴; 상기 각 반도체 칩의 제1절연층 상에 상기 범프 랜드 및 와이어 본딩 랜드를 노출시키도록 각각 형성된제2절연층; 상기 대응하는 제1금속패턴 및 연결 패턴의 범프 랜드와 제2금속패턴의 범프 랜드 사이에 개재되어 그들간을 접속시키는 솔더 범프; 상기 하부 반도체 칩이 부착되며, 회로단자가 구비된 상측면과 볼 랜드가 구비된 하측면 및 상기 회로단자와 볼 랜드를 연결하는 회로패턴을 갖는 기판; 상기 제2금속패턴의 와이어 본딩 랜드와 상기 기판의 회로단자간을 연결하는 금속 와이어; 및 상기 상,하 반도체 칩들 및 금속 와이어를 포함한 기판의 상면을 봉지하는 봉지제를 포함한다.Multi-chip package according to the present invention for achieving the above object, the upper and lower semiconductor chips spaced apart so that the bonding pad arrangement surface facing; First insulating layers formed on the bonding pad arrangement surfaces of the semiconductor chips to expose the bonding pads; A first metal pattern formed on the first insulating layer of the lower semiconductor chip, the first metal pattern having bump lands and wire bonding lands at the other ends of which one end is alternately extended to one side and the other edge and connected to a bonding pad; A connecting pattern having bump lands and wire bonding lands formed in an island shape at an edge portion where the pattern does not extend; A second metal pattern having one end connected to a bonding pad and alternately extending to one side and the other edge thereof on the first insulating layer of the upper semiconductor chip, and having bump lands at the other end thereof; A second insulating layer formed on the first insulating layer of each semiconductor chip to expose the bump land and the wire bonding land; Solder bumps interposed between the bump lands of the corresponding first metal pattern and the connection pattern and the bump lands of the second metal pattern to connect them; A substrate having the lower semiconductor chip attached thereto, the substrate having an upper side having a circuit terminal, a lower side having a ball land, and a circuit pattern connecting the circuit terminal and the ball land; A metal wire connecting the wire bonding land of the second metal pattern to a circuit terminal of the substrate; And an encapsulant encapsulating an upper surface of the substrate including the upper and lower semiconductor chips and the metal wire.
여기서, 본 발명의 멀티 칩 패키지는 상기 상부 반도체 칩의 표면이 상기 봉지제로부터 노출되는 것이 바람직하며, 더욱 바람직하게, 상기 노출된 상부 반도체 칩의 표면에 방열판이 부착된다.Here, in the multi-chip package of the present invention, it is preferable that the surface of the upper semiconductor chip is exposed from the encapsulant, and more preferably, a heat sink is attached to the exposed surface of the upper semiconductor chip.
본 발명에 따르면, 패키지의 전체 크기를 칩 크기에 해당하는 만큼으로 줄임으로써 패키지의 고밀도 실장이 가능하도록 할 수 있으며, 또한, 전기적 신호 전달 경로를 짧게 함으로써, 전기적 특성을 향상시킬 수 있고, 게다가, 반도체 칩의 표면을 외부로 노출시킴으로써 열방출 특성을 향상시킬 수 있다.According to the present invention, by reducing the overall size of the package as much as the chip size, it is possible to enable high-density packaging of the package, and also by shortening the electrical signal transmission path, it is possible to improve the electrical characteristics, The heat dissipation characteristics can be improved by exposing the surface of the semiconductor chip to the outside.
(실시예)(Example)
이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[실시예 1]Example 1
도 2a 내지 도 2g는 본 발명의 실시예 1에 따른 멀티 칩 패키지의 제조 공정을 순서대로 도시한 단면도이다.2A to 2G are cross-sectional views sequentially illustrating a manufacturing process of a multi-chip package according to Embodiment 1 of the present invention.
도 2a를 참조하면, 상부면 중심부에 일렬로 본딩 패드들(11)이 배열된 하부반도체 칩(10)을 마련한다. 그런다음, 상기 하부 반도체 칩(10) 상에 절연 성질을 갖는 용액을 일정 두께로 코팅한 후, 일정 온도에서 1차로 경화시켜 제1절연층(12)을 형성하고, 상기 본딩 패드들(11)이 노출되도록 상기 제1절연층(12)을 패터닝한 후, 2차로 경화시킨다.Referring to FIG. 2A, a lower semiconductor chip 10 having bonding pads 11 arranged in a row at a center of an upper surface thereof is provided. Then, after coating a solution having an insulating property on the lower semiconductor chip 10 to a predetermined thickness, and cured primarily at a predetermined temperature to form a first insulating layer 12, the bonding pads (11) The first insulating layer 12 is patterned so as to be exposed, and then cured secondarily.
그 다음, 상기 제1절연층(12) 상에 소정의 금속막을 증착한 후, 이를 패터닝하여 일단이 노출된 본딩 패드(11)와 콘택되면서 타단에 범프 랜드(13a) 및 와이어 본딩 랜드(13b)를 갖는 제1금속패턴(13)과, 상기 본딩 패드(11)와 연결됨이 없이 섬(island) 형태이면서 범프 랜드(13a) 및 와이어 랜드(13b)를 갖는 연결 패턴(14)을 형성한다.Next, a predetermined metal film is deposited on the first insulating layer 12, and then patterned and contacted with the bonding pad 11 exposed at one end thereof, and the bump land 13a and the wire bonding land 13b at the other end thereof. A first metal pattern 13 having a and a connection pattern 14 having bump lands 13a and wire lands 13b are formed in an island form without being connected to the bonding pads 11.
도 3은 상기 제1금속패턴(13)이 형성된 하부 반도체 칩(10)을 도시한 평면도로서, 도시된 바와 같이, 상기 제1금속패턴(13)은 그의 일단이 일렬로 배열된 각 본딩 패드(11)와 연결되며, 아울러, 좌,우 가장자리 부분으로 번갈아 연장 배치된다. 또한, 본딩 패드(11)와 연결되지 않은 섬(island) 형태의 연결 패턴(14)이 상기 제1금속패턴(13)이 연장 배치되지 않은 반대편의 가장자리 부분에 배치된다.FIG. 3 is a plan view illustrating the lower semiconductor chip 10 having the first metal pattern 13 formed thereon. As illustrated, the first metal pattern 13 may include the respective bonding pads having one end arranged in a line ( 11), and alternately extends to the left and right edges. In addition, an island-type connection pattern 14 that is not connected to the bonding pad 11 is disposed at an edge portion of the opposite side where the first metal pattern 13 is not extended.
도 2b를 참조하면, 제1금속패턴(13)이 형성된 제1절연층(12) 상에 액상의 절연 물질이 코팅되고, 이를 1차로 경화시키는 것에 의해서 제2절연층(15)이 형성된다. 그런다음, 상기 제2절연층(15)을 식각하여 상기 제1금속패턴(13) 및 연결 패턴(14)의 범프 랜드(13a) 및 와이어 본딩 랜드(13b)를 노출시킨다.Referring to FIG. 2B, a liquid insulating material is coated on the first insulating layer 12 on which the first metal pattern 13 is formed, and the second insulating layer 15 is formed by first curing the insulating material. Next, the second insulating layer 15 is etched to expose the bump lands 13a and the wire bonding lands 13b of the first metal pattern 13 and the connection pattern 14.
도 2c를 참조하면, 상부면 중심부에 일렬로 본딩 패드들(21)이 배열된 상부 반도체 칩(20)을 마련한다. 그런다음, 상기 상부 반도체 칩(20) 상에 액상의 절연물질을 코팅한 후, 일정 온도에서 1차로 경화시켜 제1절연층(22)을 형성하고, 상기 본딩 패드들(21)이 노출되도록 상기 제1절연층(22)을 패터닝한 후, 이를 2차로 경화시킨다. 이어서, 상기 제1절연층(22) 상에 소정의 금속막을 증착한 후, 이를 패터닝하여 일단이 상기 본딩 패드(21)와 콘택되고, 그리고, 타단에 범프 랜드(23a)를 갖는 제2금속패턴(23)을 형성한다.Referring to FIG. 2C, an upper semiconductor chip 20 in which bonding pads 21 are arranged in a line is provided at the center of the upper surface. Then, after coating a liquid insulating material on the upper semiconductor chip 20, the first insulating layer 22 is formed by first curing at a predetermined temperature to expose the bonding pads 21. After patterning the first insulating layer 22, it is cured secondarily. Subsequently, a predetermined metal film is deposited on the first insulating layer 22, and then patterned to form a second metal pattern having one end contacting the bonding pad 21 and a bump land 23a at the other end. (23) is formed.
도 4는 상기 제2금속패턴(23)이 형성된 상부 반도체 칩(10)을 도시한 평면도로서, 도시된 바와 같이, 상기 제2금속패턴(23)은 그의 일단이 일렬로 배열된 각 본딩 패드(11)와 연결되면서 좌,우 가장자리 부분으로 번갈아 연장 배치된다.FIG. 4 is a plan view illustrating the upper semiconductor chip 10 having the second metal pattern 23 formed thereon. As illustrated, the second metal pattern 23 may include the respective bonding pads having one end arranged in a line ( 11) and is alternately extended to the left and right edges.
도 2d를 참조하면, 제2금속패턴(23)이 형성된 제1절연층(22) 상에 액상의 절연 물질을 코팅한 후, 이를 1차로 경화시켜 제2절연층(25)을 형성하고, 그런다음, 상기 제2절연층(25)을 식각하여 상기 제2금속패턴(23)의 범프 랜드(23a)를 노출시킨다. 이어서, 노출된 범프 랜드(23a) 상에 솔더 범프(26)를 형성한다.Referring to FIG. 2D, after coating a liquid insulating material on the first insulating layer 22 on which the second metal pattern 23 is formed, the second insulating layer 25 is formed by first curing it. Next, the second insulating layer 25 is etched to expose the bump lands 23a of the second metal pattern 23. Subsequently, solder bumps 26 are formed on the exposed bump lands 23a.
상기에서, 하부 반도체 칩(10) 및 상부 반도체 칩(20)에 대한 전술한 공정들을 웨이퍼 레벨에서 수행하며, 아울러, 각 반도체 칩(10, 20)에 대한 전술한 공정을 완료한 후에는 웨이퍼 소잉(sawing) 공정을 수행하여 개별 반도체 칩들로 분리시킨다.In the above, the above-described processes for the lower semiconductor chip 10 and the upper semiconductor chip 20 are performed at the wafer level, and the wafer sawing after completing the above-described processes for the respective semiconductor chips 10 and 20 is completed. A sawing process is performed to separate the individual semiconductor chips.
도 2e를 참조하면, 회로패턴(34)이 구비된 베이스 기판(31)의 상,하부면에 회로단자(35)와 볼 랜드(36)를 노출시키도록 각각 절연층(32, 33)이 형성된 구조의 기판(40)을 마련한다. 그런다음, 상기 기판(40) 상에 접착 테이프 또는 에폭시 계열의 수지로 이루어진 접착제(42)를 이용해서 도 2b에 도시된 하부 반도체 칩(10)을 접착시키고, 이어서, 와이어 본딩 공정을 통해 상기 하부 반도체 칩(10)의 와이어 본딩 패드(13b)와 상기 기판(40)의 회로단자(35)간을 금속 와이어(44)로 연결시킨다.Referring to FIG. 2E, insulating layers 32 and 33 are formed on the upper and lower surfaces of the base substrate 31 having the circuit patterns 34 to expose the circuit terminals 35 and the ball lands 36, respectively. A substrate 40 having a structure is prepared. Then, the lower semiconductor chip 10 shown in FIG. 2B is bonded to the substrate 40 by using an adhesive 42 made of an adhesive tape or an epoxy resin, and then, the lower portion is connected through a wire bonding process. The metal wire 44 is connected between the wire bonding pad 13b of the semiconductor chip 10 and the circuit terminal 35 of the substrate 40.
도 2f를 참조하면, 상기 하부 반도체 칩(10)의 상부에 도 2d에 도시된 바와 같은 상부 반도체 칩(20)을 각 칩(10, 2)의 본딩 패드 형성면이 마주 보면서, 상기 상부 반도체 칩(20)에 형성된 솔더 범프(26)가 상기 하부 반도체 칩(10)의 범프 랜드(13a)와 맞닿도록 배치시킨 상태에서, 열압착을 통해 상기 상부 반도체 칩(20)을 상기 하부 반도체 칩(10) 상에 부착시킨다.Referring to FIG. 2F, the upper semiconductor chip 20 as shown in FIG. 2D is placed on the upper surface of the lower semiconductor chip 10 while the bonding pad forming surfaces of the chips 10 and 2 face each other. In the state where the solder bumps 26 formed in the 20 are in contact with the bump lands 13a of the lower semiconductor chip 10, the upper semiconductor chip 20 is thermally pressed to form the lower semiconductor chip 10. ) On the
이렇게 되면, 상기 하부 반도체 칩(10)은 그의 본딩 패드(11)와 콘택된 제1금속패턴(13) 및 금속 와이어(44)를 경유해서 기판(40)의 회로패턴(34)과 전기적으로 연결되는 반면, 상기 상부 반도체 칩(20)은 그의 본딩 패드(21)와 콘택된 제2금속패턴(23)과 하부 반도체 칩(10)의 연결 패턴(14) 및 금속 와이어(44)를 경유해서 기판(40)의 회로패턴(34)과 전기적으로 연결된다.In this case, the lower semiconductor chip 10 is electrically connected to the circuit pattern 34 of the substrate 40 via the first metal pattern 13 and the metal wire 44 in contact with the bonding pad 11 thereof. On the other hand, the upper semiconductor chip 20 is a substrate via the second metal pattern 23 and the connection pattern 14 of the lower semiconductor chip 10 and the metal wire 44 contacted with the bonding pad 21 thereof. It is electrically connected to the circuit pattern 34 of 40.
계속해서, 상기 반도체 칩들(10, 20) 및 금속 와이어(44)를 포함한 기판(40)의 상부면을 봉지제(46)로 봉지하여 상기 금속 와이어(44) 및 반도체 칩들(10, 20)이 외부 충격으로부터 보호되도록 한다.Subsequently, the upper surface of the substrate 40 including the semiconductor chips 10 and 20 and the metal wire 44 is encapsulated with an encapsulant 46 so that the metal wire 44 and the semiconductor chips 10 and 20 are sealed. Ensure protection from external shocks.
도 2g를 참조하면, 기판(40)의 볼 랜드(36)에 실장 수단으로서 기능하는 솔더 볼(48)을 형성함으로써, 본 발명의 실시예 1에 따른 멀티 칩 패키지(50)를 완성한다.Referring to FIG. 2G, the multi-chip package 50 according to Embodiment 1 of the present invention is completed by forming solder balls 48 that function as mounting means on the ball lands 36 of the substrate 40.
상기와 같은 공정순으로 제조되는 본 발명의 멀티 칩 패키지는 2개의 반도체칩을 적층식으로 배치시키기 때문에 패키지의 전체 크기를 칩의 크기와 유사하게 만들 수 있으며, 따라서, 고용량을 얻으면서도 실장 면적을 줄일 수 있게 되어 고밀도 실장이 가능하다.Since the multi-chip package of the present invention manufactured in the above-described process order, two semiconductor chips are arranged in a stacked manner, the overall size of the package can be made similar to the size of the chip, thereby reducing the mounting area while obtaining high capacity. It becomes possible, and high density mounting is possible.
또한, 본 발명의 멀티 칩 패키지는 하부 반도체 칩과 상부 반도체 칩의 전기적 연결이 짧은 신호 전달 경로를 제공하는 솔더 범프에 의해 이루어지므로, 개선된 전기적 특성을 갖는다.In addition, the multi-chip package of the present invention has improved electrical characteristics because the electrical connection between the lower semiconductor chip and the upper semiconductor chip is made by solder bumps that provide a short signal transmission path.
[실시예 2]Example 2
도 5는 본 발명의 실시예 2에 따른 멀티 칩 패키지를 도시한 단면도이다. 본 실시예 2에 따른 멀티 칩 패키지의 구조는 전술한 실시예 1과 거의 동일하고, 다만, 상부 반도체 칩(20)의 표면이 봉지제(46)로부터 노출된 점이 상이하다.5 is a cross-sectional view illustrating a multi-chip package according to Embodiment 2 of the present invention. The structure of the multi-chip package according to the second embodiment is almost the same as that of the first embodiment described above, except that the surface of the upper semiconductor chip 20 is exposed from the encapsulant 46.
이 경우에는 상부 반도체 칩(20)의 표면이 외부에 노출됨으로써, 각 반도체 칩(10,20)의 구동중에 발생되는 열을 외부로 방출시키는 열방출 특성이 향상되는 잇점이 있다.In this case, the surface of the upper semiconductor chip 20 is exposed to the outside, so that the heat dissipation characteristic of dissipating heat generated during the driving of the semiconductor chips 10 and 20 to the outside is improved.
[실시예 3]Example 3
도 6은 본 발명의 실시예 3에 따른 멀티 칩 패키지를 도시한 단면도이다. 본 실시예 3에서는 열방출 특성을 더욱 높이기 위해, 노출된 상부 반도체 칩(20)의 표면에 요철 구조의 방열판(60)이 접착제(52)에 의해 부착된다.6 is a cross-sectional view illustrating a multi-chip package according to Embodiment 3 of the present invention. In the third embodiment, in order to further improve the heat dissipation characteristics, the heat sink 60 having the uneven structure is attached to the exposed surface of the upper semiconductor chip 20 by the adhesive 52.
[실시예 4]Example 4
도 7은 본 발명의 실시예 4에 따른 멀티 칩 패키지를 도시한 단면도이다. 본 실시예 4에 따른 멀티 칩 패키지의 구조는 전술한 실시예 1과 전체적인 구조는 유사하고, 다만, 상부 반도체 칩(70)의 구조가 상이하다.7 is a cross-sectional view showing a multi-chip package according to a fourth embodiment of the present invention. The structure of the multi-chip package according to the fourth embodiment is similar to that of the above-described first embodiment, except that the structure of the upper semiconductor chip 70 is different.
이 실시예 4에 있어서, 상기 상부 반도체 칩(70)은 본딩 패드(71)가 가장자리 부분에 배열되는 구조이며, 특히, 배선의 재배열 공정을 수행함이 없이, 본딩 패드(71) 상에 바로 솔더 범프(26)가 형성되고, 이러한 솔더 범프(26)를 통해서 그의 본딩 패드들(71)이 하부 반도체 칩(10)의 제1금속패턴(13) 및 연결 패턴(14)과 전기적으로 연결된다.In the fourth embodiment, the upper semiconductor chip 70 has a structure in which the bonding pads 71 are arranged at edge portions, and in particular, solder is directly on the bonding pads 71 without performing a rearrangement process of the wirings. A bump 26 is formed, and the bonding pads 71 are electrically connected to the first metal pattern 13 and the connection pattern 14 of the lower semiconductor chip 10 through the solder bumps 26.
이상에서와 같이, 본 발명의 멀티 칩 패키지는 2개의 반도체 칩들을 적층 구조를 갖도록 배치시키기 때문에, 패키지의 전체 크기를 반도체 칩의 크기와 유사하도록 만들 수 있으며, 따라서, 고밀도 실장을 실현할 수 있다.As described above, since the multi-chip package of the present invention arranges two semiconductor chips to have a stacked structure, the overall size of the package can be made similar to that of the semiconductor chip, and thus high density mounting can be realized.
또한, 본 발명의 멀티 칩 패키지는 반도체 칩들간의 전기적 접속이 솔더 범프를 통해 이루어지는 것으로 인해 전기적 특성을 개선시킬 수 있다.In addition, the multi-chip package of the present invention can improve the electrical characteristics due to the electrical connection between the semiconductor chips through the solder bumps.
게다가, 본 발명의 멀티 칩 패키지는 상부 반도체 칩의 표면을 외부로 노출시키고, 아울러, 노출된 상부 반도체 칩의 표면에 방열판을 부착시킴으로써, 열방출 특성을 향상시킬 수 있다.In addition, the multi-chip package of the present invention may improve the heat dissipation characteristics by exposing the surface of the upper semiconductor chip to the outside and attaching a heat sink to the exposed surface of the upper semiconductor chip.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| KR101601793B1 (en) * | 2009-10-08 | 2016-03-09 | 삼성전자주식회사 | Improved electrical connections for multichip modules |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03231450A (en) * | 1990-02-07 | 1991-10-15 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH11195746A (en) * | 1997-10-08 | 1999-07-21 | Lucent Technol Inc | Integrated circuit package |
| KR20010004562A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | chip size stack package and method of fabricating the same |
| KR20010061791A (en) * | 1999-12-29 | 2001-07-07 | 박종섭 | Wafer level stack package |
| KR20010068514A (en) * | 2000-01-06 | 2001-07-23 | 윤종용 | Stack package stacking chip scale package(CSP) |
| KR20020056662A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Stack type Multi Chip Package and Manufacture Method the same |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03231450A (en) * | 1990-02-07 | 1991-10-15 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH11195746A (en) * | 1997-10-08 | 1999-07-21 | Lucent Technol Inc | Integrated circuit package |
| KR20010004562A (en) * | 1999-06-29 | 2001-01-15 | 김영환 | chip size stack package and method of fabricating the same |
| KR20010061791A (en) * | 1999-12-29 | 2001-07-07 | 박종섭 | Wafer level stack package |
| KR20010068514A (en) * | 2000-01-06 | 2001-07-23 | 윤종용 | Stack package stacking chip scale package(CSP) |
| KR20020056662A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Stack type Multi Chip Package and Manufacture Method the same |
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