JPH065641A - Chip carrier type semiconductor device - Google Patents
Chip carrier type semiconductor deviceInfo
- Publication number
- JPH065641A JPH065641A JP4156614A JP15661492A JPH065641A JP H065641 A JPH065641 A JP H065641A JP 4156614 A JP4156614 A JP 4156614A JP 15661492 A JP15661492 A JP 15661492A JP H065641 A JPH065641 A JP H065641A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip carrier
- semiconductor device
- type semiconductor
- carrier type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップキャリア型半導
体装置に関し、特に有機系基板上に半導体素子が搭載さ
れて形成されるパッケージ構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier type semiconductor device, and more particularly to a package structure formed by mounting a semiconductor element on an organic substrate.
【０００２】[0002]
【従来の技術】従来の表面実装タイプのチップキャリア
型半導体装置は、図２（ａ），（ｂ）に示すようにガラ
スエポキシ基板１に凹形状の座ぐりが設けらており、こ
の座ぐり部分に半導体ＩＣペレット３が搭載されてい
る。半導体ＩＣペレット３はガラスエポキシ基板１の所
望部分に形成されたボンディングパッド４とＡｕワイヤ
５で接続されている。また、ボンディングパッド４はガ
ラスエポキシ基板１上で配線により電極６に接続されて
いる。さらにガラスエポキシ基板１の周辺部には樹脂枠
８が設けられており、樹脂枠８の内側にはエポキシ樹脂
７が充填されている。2. Description of the Related Art A conventional surface mounting type chip carrier type semiconductor device has a recessed counterbore provided on a glass epoxy substrate 1 as shown in FIGS. 2 (a) and 2 (b). A semiconductor IC pellet 3 is mounted on the portion. The semiconductor IC pellet 3 is connected to a bonding pad 4 formed on a desired portion of the glass epoxy substrate 1 by an Au wire 5. The bonding pad 4 is connected to the electrode 6 by wiring on the glass epoxy substrate 1. Further, a resin frame 8 is provided in the peripheral portion of the glass epoxy substrate 1, and an epoxy resin 7 is filled inside the resin frame 8.
【０００３】[0003]
【発明が解決しようとする課題】この従来のチップキャ
リア型半導体装置では、信頼性上、特に耐湿性において
次のような問題点があった。すなわち、半導体素子の素
子面は樹脂により保護されているものの、有機系基材の
繊維層を通じて外部からの水分又は湿気の浸入により、
良好な耐湿性を確保することが困難であった。The conventional chip carrier type semiconductor device has the following problems in terms of reliability, particularly in moisture resistance. That is, although the element surface of the semiconductor element is protected by the resin, by the infiltration of moisture or humidity from the outside through the fiber layer of the organic base material,
It was difficult to secure good moisture resistance.
【０００４】上記問題点は、例えばチップキャリア型半
導体装置をハンダリフロー装置によりプリント配線基板
上に実装する場合、リフロー前の混成集積回路装置の保
管状態をより厳格に管理しなければならないというよう
な、表面実装部品管理面に影響していた。また、湿気の
浸入により電気的なリーク不良が発生し易く性能面にも
影響していた。The above problem is that, for example, when a chip carrier type semiconductor device is mounted on a printed wiring board by a solder reflow device, the storage state of the hybrid integrated circuit device before reflow must be controlled more strictly. , It had an influence on the management of surface mount components. In addition, the infiltration of moisture is apt to cause an electrical leak defect, which also affects the performance.
【０００５】[0005]
【課題を解決するための手段】本発明のチップキャリア
型半導体装置は、有機系基材と樹脂からなる積層構造の
基板において、基材面側に凹形状の座ぐりを設け、この
座ぐり部分に半導体素子を配置することにより、外部か
らの水分又は湿気の浸入をより少なくすることが可能と
なり、耐湿性が向上した。A chip carrier type semiconductor device of the present invention is a substrate having a laminated structure composed of an organic base material and a resin, and a concave counterbore is provided on the base material surface side, and the counterbore portion is provided. By arranging the semiconductor element in the above, it becomes possible to further reduce intrusion of moisture or humidity from the outside, and the moisture resistance is improved.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）は本発明の一実施例を示す平面図で、
（ｂ）は（ａ）のＡ−Ａ′線の断面図である。ガラスエ
ポキシ基板１は、エポキシ樹脂層２と積層構造になって
おり、半導体ＩＣペレット３が搭載される部分が凹形状
にくり抜かれている。ガラスエポキシ基板１に半導体Ｉ
Ｃペレット３を搭載し、ガラスエポキシ基板３に形成さ
れたボンディングパッド４と半導体ＩＣペレット３とを
ワイヤ５で接続する。ボンディングパッド４はガラスエ
ポキシ基板１上の配線により、外部との接続に使用され
る電極６に引き出されている。エポキシ樹脂７は、電極
６と同じ高さで、かつ表面が平らになるように充填され
ている。The present invention will be described below with reference to the drawings. FIG. 1A is a plan view showing an embodiment of the present invention.
(B) is a sectional view taken along the line AA 'in (a). The glass epoxy substrate 1 has a laminated structure with the epoxy resin layer 2, and a portion where the semiconductor IC pellet 3 is mounted is hollowed out in a concave shape. Semiconductor I on glass epoxy substrate 1
The C pellet 3 is mounted, and the bonding pad 4 formed on the glass epoxy substrate 3 and the semiconductor IC pellet 3 are connected by the wire 5. The bonding pad 4 is drawn out to the electrode 6 used for connection with the outside by the wiring on the glass epoxy substrate 1. The epoxy resin 7 is filled at the same height as the electrode 6 so that the surface becomes flat.
【０００７】[0007]
【発明の効果】以上説明したように、本発明は半導体素
子が搭載される部分を有機系基材と樹脂からなる積層構
造にすることにより、半導体素子裏面側より浸入してく
る水分又は湿気を少なくすることができるため、耐湿性
を向上させることができる。As described above, according to the present invention, the portion on which the semiconductor element is mounted has a laminated structure composed of the organic base material and the resin, so that the moisture or the moisture entering from the back surface side of the semiconductor element can be prevented. Since it can be reduced, the moisture resistance can be improved.
【図１】（ａ）は本発明による一実施例を示す平面図，
（ｂ）は（ａ）のＡ−Ａ′線の断面図である。FIG. 1A is a plan view showing an embodiment according to the present invention,
(B) is a sectional view taken along the line AA 'in (a).
【図２】（ａ）は従来例を示す平面図，（ｂ）は（ａ）
のＡ−Ａ′線の断面図である。FIG. 2 (a) is a plan view showing a conventional example, and FIG. 2 (b) is (a).
3 is a cross-sectional view taken along the line AA ′ of FIG.
１ ガラスエポキシ基板 ２ エポキシ樹脂層 ３ 半導体ＩＣペレット ４ ボンディングパッド ５ Ａｕワイヤ ６ 電極 ７ エポキシ樹脂 ８ 樹脂枠 1 Glass Epoxy Substrate 2 Epoxy Resin Layer 3 Semiconductor IC Pellet 4 Bonding Pad 5 Au Wire 6 Electrode 7 Epoxy Resin 8 Resin Frame
Claims (1)
板において、基材面側に凹形状の座ぐりを設け、この座
ぐり部分に半導体素子を配置し、基板端面の所望部分に
形成された電極と半導体素子をボンディング線で接続
し、半導体素子およびボンディング線を樹脂で被覆する
ことを特徴とするチップキャリア型半導体装置。1. A substrate having a laminated structure composed of an organic base material and a resin is provided with a concave counterbore on the base material surface side, and a semiconductor element is arranged in the counterbore portion, and formed on a desired portion of the substrate end surface. A chip carrier type semiconductor device, characterized in that the formed electrode and the semiconductor element are connected with a bonding wire, and the semiconductor element and the bonding wire are covered with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4156614A JPH065641A (en) | 1992-06-16 | 1992-06-16 | Chip carrier type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4156614A JPH065641A (en) | 1992-06-16 | 1992-06-16 | Chip carrier type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065641A true JPH065641A (en) | 1994-01-14 |
Family
ID=15631585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4156614A Withdrawn JPH065641A (en) | 1992-06-16 | 1992-06-16 | Chip carrier type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065641A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4948972A (en) * | 1986-10-14 | 1990-08-14 | Fuji Photo Film Co., Ltd. | Read-out device for radiation image storage panel |
| JPH08255850A (en) * | 1995-03-16 | 1996-10-01 | Nec Corp | Semiconductor device |
-
1992
- 1992-06-16 JP JP4156614A patent/JPH065641A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4948972A (en) * | 1986-10-14 | 1990-08-14 | Fuji Photo Film Co., Ltd. | Read-out device for radiation image storage panel |
| JPH08255850A (en) * | 1995-03-16 | 1996-10-01 | Nec Corp | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |