JP2001237366A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001237366A
JP2001237366A JP2000042695A JP2000042695A JP2001237366A JP 2001237366 A JP2001237366 A JP 2001237366A JP 2000042695 A JP2000042695 A JP 2000042695A JP 2000042695 A JP2000042695 A JP 2000042695A JP 2001237366 A JP2001237366 A JP 2001237366A
Authority
JP
Japan
Prior art keywords
insulating member
semiconductor device
mounting portion
element mounting
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000042695A
Other languages
Japanese (ja)
Other versions
JP4060020B2 (en
Inventor
Takanobu Yoshida
貴信 吉田
Toshiaki Shinohara
利彰 篠原
Hisashi Kawato
寿 川藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000042695A priority Critical patent/JP4060020B2/en
Publication of JP2001237366A publication Critical patent/JP2001237366A/en
Application granted granted Critical
Publication of JP4060020B2 publication Critical patent/JP4060020B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】 【課題】 封止部の形成不具合を有さず絶縁性及び放熱
性が確保された半導体装置を提供する。 【解決手段】 半導体装置101は、電極フレーム2
と、電力用半導体素子1と、セラミックから成る絶縁部
材7と、エポキシ樹脂から成る封止部5とを備える。電
極フレーム2の素子搭載部2Dの表面2S1上に電力用
半導体素子1が搭載されている。素子搭載部2Dの表面
2S2に対面する絶縁部材7の表面7S1は、当該表面
7S1の周縁が素子搭載部2Dの表面2S2の周縁を取
り囲みうる寸法・形状を有しており、表面7S1の周縁
が素子搭載部2Dの表面2S2の周縁を取り囲んで配置
されている。封止部5は、電力用半導体素子1及び素子
搭載部2D等を覆って、且つ、絶縁部材7の表面7S
1,7S3に接して形成されている。絶縁部材7の表面
7S2は封止部5で覆われておらず、当該表面7S2の
全面が露出している。
(57) [Problem] To provide a semiconductor device in which insulation properties and heat dissipation properties are secured without forming defects of a sealing portion. A semiconductor device includes an electrode frame.
And a power semiconductor element 1, an insulating member 7 made of ceramic, and a sealing portion 5 made of epoxy resin. The power semiconductor element 1 is mounted on the surface 2S1 of the element mounting portion 2D of the electrode frame 2. The surface 7S1 of the insulating member 7 facing the surface 2S2 of the element mounting portion 2D has such a size and shape that the periphery of the surface 7S1 can surround the periphery of the surface 2S2 of the element mounting portion 2D. It is arranged so as to surround the periphery of the surface 2S2 of the element mounting portion 2D. The sealing part 5 covers the power semiconductor element 1 and the element mounting part 2D and the like, and has a surface 7S of the insulating member 7.
It is formed in contact with 1,7S3. The surface 7S2 of the insulating member 7 is not covered with the sealing portion 5, and the entire surface 7S2 is exposed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関する
ものであり、特に、発熱の大きい半導体素子を備えた半
導体装置における封止ないしはパッケージの形成及び絶
縁性の確保、更には放熱の各技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique of sealing or forming a package and securing insulation properties in a semiconductor device having a semiconductor element generating a large amount of heat, and furthermore, a heat radiation technique.

【0002】[0002]

【従来の技術】図10に、従来の電力用半導体装置10
1P(以下、単に半導体装置101Pとも呼ぶ)を説明
するための縦断面図を示す。図10に示すように、電極
フレーム2の素子搭載部ないしはダイパッド2D上に電
力用半導体素子1がろう材3により接合されており、電
力用半導体素子1と電極フレーム2のリード部2Lとの
間等が金属細線4で接続されている。電力用半導体素子
1及び素子搭載部2Dは封止樹脂5Pで以て封止されて
おり、封止樹脂5Pにより半導体装置101Pの絶縁性
を確保している。封止樹脂5Pは例えばポッティング法
やトランスファモールド法により形成される。
2. Description of the Related Art FIG. 10 shows a conventional power semiconductor device 10.
1P (hereinafter, also simply referred to as a semiconductor device 101P) is shown in a longitudinal sectional view. As shown in FIG. 10, the power semiconductor element 1 is joined to the element mounting portion of the electrode frame 2 or the die pad 2D by the brazing material 3, and the space between the power semiconductor element 1 and the lead portion 2L of the electrode frame 2 is formed. Are connected by a thin metal wire 4. The power semiconductor element 1 and the element mounting portion 2D are sealed with a sealing resin 5P, and the insulating property of the semiconductor device 101P is ensured by the sealing resin 5P. The sealing resin 5P is formed by, for example, a potting method or a transfer molding method.

【0003】[0003]

【発明が解決しようとする課題】上述のように、従来の
半導体装置101Pの素子搭載部2Dは封止樹脂5Pで
覆われている。このとき、電力用半導体素子1の素子搭
載部2D側の絶縁性を高めるためには、素子搭載部2D
下方の封止樹脂5P(封止樹脂5PP参照)をより厚く
する必要がある(厚さt参照)。しかしながら、一般的
に封止樹脂5Pの熱伝導率は低いため、厚さtを増大さ
せると熱抵抗が大きくなってしまう。即ち、電力用半導
体素子1の発熱に対する放熱性が低下してしまう。
As described above, the element mounting portion 2D of the conventional semiconductor device 101P is covered with the sealing resin 5P. At this time, in order to enhance the insulation on the element mounting portion 2D side of the power semiconductor element 1, the element mounting portion 2D
It is necessary to make the lower sealing resin 5P (see the sealing resin 5PP) thicker (see the thickness t). However, since the thermal conductivity of the sealing resin 5P is generally low, increasing the thickness t increases the thermal resistance. That is, the heat radiation of the power semiconductor element 1 against heat generation is reduced.

【0004】他方、放熱性を向上させるために厚さtを
減少させると上述の絶縁性を確保できないばかりでな
く、封止樹脂5PPの形成不具合及び当該不具合に起因
した絶縁性の低下が惹起される。即ち、封止樹脂5Pを
例えばポッティング法やトランスファモールド法により
形成する場合、厚さtが小さいと、素子搭載部2Dと金
型(図示せず)との隙間へ封止樹脂を注入ないしは充填
しにくくなる。このため、封止樹脂の充填不足等によっ
て封止樹脂5PPの形成不具合が生じ、かかる形成不具
合が封止樹脂5PPにおける絶縁性を低下させてしま
う。
On the other hand, if the thickness t is reduced in order to improve the heat radiation, not only the above-mentioned insulation property cannot be ensured, but also the formation failure of the sealing resin 5PP and the decrease in insulation property caused by the failure are caused. You. That is, when the sealing resin 5P is formed by, for example, a potting method or a transfer molding method, if the thickness t is small, the sealing resin is injected or filled into a gap between the element mounting portion 2D and a mold (not shown). It becomes difficult. For this reason, formation failure of the sealing resin 5PP occurs due to insufficient filling of the sealing resin, and the formation failure reduces the insulating property of the sealing resin 5PP.

【0005】本発明はかかる問題点に鑑みてなされたも
のであり、封止部の形成不具合を有さず絶縁性が確保さ
れた半導体装置を提供することを第1の目的とする。
The present invention has been made in view of the above problems, and it is a first object of the present invention to provide a semiconductor device which does not have a defect in forming a sealing portion and has an insulating property.

【0006】また、本発明は、上記第1の目的を実現し
うる半導体装置を低コスト・低価格で提供することを第
2の目的とする。
A second object of the present invention is to provide a semiconductor device which can realize the first object at low cost and low cost.

【0007】更に、本発明は、上記第1及び第2の目的
の実現と共に放熱性の安定化及び向上が図られた半導体
装置を提供することを第3の目的とする。
Further, a third object of the present invention is to provide a semiconductor device in which the first and second objects are realized and the heat dissipation is stabilized and improved.

【0008】[0008]

【課題を解決するための手段】(1)請求項1に記載の
発明に係る半導体装置は、素子搭載部及びリード部を有
する電極フレームと、前記素子搭載部の一方の表面上に
搭載された半導体素子と、その周縁が前記素子搭載部の
他方の表面の周縁を取り囲んで前記他方の表面に対面す
る第1表面と、前記第1表面に対向する第2表面とを有
し、前記素子搭載部に固定された絶縁部材と、前記絶縁
部材の前記第2表面の全面を露出させた状態で前記絶縁
部材に接すると共に前記半導体素子を覆って形成された
封止部とを備えることを特徴とする。
(1) A semiconductor device according to the first aspect of the present invention is mounted on an electrode frame having an element mounting portion and a lead portion, and on one surface of the element mounting portion. A semiconductor element having a first surface surrounding the periphery of the other surface of the element mounting portion and facing the other surface, and a second surface facing the first surface; An insulating member fixed to the portion, and a sealing portion formed in contact with the insulating member while covering the entire surface of the second surface of the insulating member and covering the semiconductor element. I do.

【0009】(2)請求項2に記載の発明に係る半導体
装置は、請求項1に記載の半導体装置であって、前記第
2表面と前記封止部の外表面とが平坦を成すことを特徴
とする。
(2) The semiconductor device according to the second aspect of the present invention is the semiconductor device according to the first aspect, wherein the second surface and the outer surface of the sealing portion are flat. Features.

【0010】(3)請求項3に記載の発明に係る半導体
装置は、請求項1に記載の半導体装置であって、前記絶
縁部材は前記第1表面と前記第2表面との間で側面を成
す第3表面を有し、前記第3表面が更に露出しているこ
とを特徴とする。
(3) A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the insulating member has a side surface between the first surface and the second surface. A third surface, wherein the third surface is further exposed.

【0011】(4)請求項4に記載の発明に係る半導体
装置は、請求項1乃至3のいずれかに記載の半導体装置
であって、前記絶縁部材は接着材で以て前記素子搭載部
に固定されていることを特徴とする。
(4) A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the insulating member is formed of an adhesive on the element mounting portion. It is characterized by being fixed.

【0012】(5)請求項5に記載の発明に係る半導体
装置は、請求項1乃至4のいずれかに記載の半導体装置
であって、前記絶縁部材は前記封止部と比較して熱伝導
率が高いことを特徴とする。
(5) A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the insulating member has a higher heat conduction than the sealing portion. It is characterized by a high rate.

【0013】[0013]

【発明の実施の形態】<実施の形態1>図1及び図2に
それぞれ実施の形態1に係る電力用半導体装置(半導体
装置)101を説明するための縦断面図及び上面図を示
す。図2中のI−I線における縦断面図が図1にあた
る。また、図2では、絶縁部材7及び封止部5をそれぞ
れ太線及び破線で図示している。電力用半導体装置10
1(以下、単に半導体装置101のように呼ぶ)は、い
わゆるDIP(Dual Inline Package)タイプにあた
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIGS. 1 and 2 are a vertical sectional view and a top view, respectively, for explaining a power semiconductor device (semiconductor device) 101 according to a first embodiment. FIG. 1 is a longitudinal sectional view taken along line II in FIG. Further, in FIG. 2, the insulating member 7 and the sealing portion 5 are illustrated by thick lines and broken lines, respectively. Power semiconductor device 10
1 (hereinafter simply referred to as the semiconductor device 101) corresponds to a so-called DIP (Dual Inline Package) type.

【0014】図1及び図2に示すように、半導体装置1
01は、電極フレーム2と、電力用半導体素子1(図1
及び図2では2個を図示している)と、(予めに所定の
形状に形成されている)絶縁部材7と、封止部5とを備
える。詳細には、電極フレーム2は素子搭載部ないしは
ダイパッド2D及びリード部2Lを有しており、素子搭
載部2Dの一方の表面2S1上に電力用半導体素子1が
搭載されている。電力用半導体素子1はろう材3によっ
て素子搭載部2Dに固定されている。そして、電力用半
導体素子1とリード部2Lとの間等が金属細線4で接続
されている。
As shown in FIG. 1 and FIG.
Reference numeral 01 denotes an electrode frame 2 and a power semiconductor element 1 (FIG. 1).
And two are shown in FIG. 2), an insulating member 7 (formed in a predetermined shape in advance), and a sealing portion 5. More specifically, the electrode frame 2 has an element mounting portion or die pad 2D and a lead portion 2L, and the power semiconductor element 1 is mounted on one surface 2S1 of the element mounting portion 2D. The power semiconductor element 1 is fixed to the element mounting portion 2D by the brazing material 3. The thin metal wire 4 connects between the power semiconductor element 1 and the lead 2L.

【0015】絶縁部材7は、(a)素子搭載部2Dの他
方の表面2S2に対面する表面(第1表面)7S1と、
(b)表面7S1に対向する表面(第2表面)7S2
と、(c)表面7S1,7S2の双方に結合して両表面
7S1,7S2と共に絶縁部材7の外表面を成す表面な
いしは側面(第3表面)7S3とを有している。
The insulating member 7 includes (a) a surface (first surface) 7S1 facing the other surface 2S2 of the element mounting portion 2D;
(B) Surface (second surface) 7S2 facing surface 7S1
And (c) a surface or side surface (third surface) 7S3 which is connected to both surfaces 7S1 and 7S2 and forms an outer surface of insulating member 7 together with both surfaces 7S1 and 7S2.

【0016】特に、表面7S1は、当該表面7S1の周
縁7Aが素子搭載部2Dの表面2S2の周縁2DAを取
り囲みうる寸法・形状を有しており、表面7S1の周縁
7Aが素子搭載部2Dの表面2S2の周縁2DAを取り
囲んで配置されている。このとき、両表面7S1,7S
2は同じ寸法・形状でなくとも良く、例えば図1におけ
る縦断面が台形状であっても構わない。絶縁部材7は例
えば0.5mm程度の厚さのAl2O3,AlN,Si
3N4等のセラミック板から成る。
In particular, the surface 7S1 has such a size and shape that the peripheral edge 7A of the surface 7S1 can surround the peripheral edge 2DA of the surface 2S2 of the element mounting portion 2D, and the peripheral edge 7A of the surface 7S1 corresponds to the surface of the element mounting portion 2D. It is arranged so as to surround the peripheral edge 2DA of 2S2. At this time, both surfaces 7S1, 7S
2 do not have to have the same size and shape. For example, the longitudinal section in FIG. 1 may be trapezoidal. The insulating member 7 is made of, for example, Al2O3, AlN, Si having a thickness of about 0.5 mm.
It is made of a ceramic plate such as 3N4.

【0017】絶縁部材7はろう材(接着材)6によって
素子搭載部2Dに固定されている。ろう材6及び上記ろ
う材3として、鉛成分を含まない材料、例えばエポキシ
樹脂中に硬化剤ないしは添加剤,銀(Ag)等を添加し
た樹脂系ろう材を用いている。
The insulating member 7 is fixed to the element mounting portion 2D by a brazing material (adhesive material) 6. As the brazing material 6 and the brazing material 3, a material containing no lead component, for example, a resin-based brazing material obtained by adding a curing agent or an additive, silver (Ag), or the like to an epoxy resin is used.

【0018】封止部5は、電力用半導体素子1及び素子
搭載部2D等を覆って、且つ、絶縁部材7の表面7S
1,7S3に接して形成されている。特に、絶縁部材7
の表面7S2は封止部5で覆われておらず全面が露出し
ている。また、絶縁部材7の表面7S2と封止部5の外
表面5Sとが平坦に繋がっている。即ち、半導体装置1
01の外表面において絶縁部材7の表面7S2は凹部を
形成していない。
The sealing section 5 covers the power semiconductor element 1 and the element mounting section 2D and the like, and has a surface 7S of the insulating member 7.
It is formed in contact with 1,7S3. In particular, the insulating member 7
The surface 7S2 is not covered with the sealing portion 5 and the entire surface is exposed. The surface 7S2 of the insulating member 7 and the outer surface 5S of the sealing portion 5 are connected flat. That is, the semiconductor device 1
In the outer surface of No. 01, the surface 7S2 of the insulating member 7 does not have a concave portion.

【0019】封止部5は例えばエポキシ樹脂等の材料か
ら成る。かかるエポキシ樹脂等の熱伝導率は2W/(m
・K)程度である一方、絶縁部材7を成すアルミナ(A
l2O3)等の熱伝導率は20W/(m・K)程度であ
る。即ち、絶縁部材7は封止部5と比較して熱伝導率が
高い。
The sealing portion 5 is made of, for example, a material such as an epoxy resin. The thermal conductivity of such an epoxy resin is 2 W / (m
.K), but alumina (A) forming the insulating member 7
The thermal conductivity of (12O3) is about 20 W / (m · K). That is, the insulating member 7 has a higher thermal conductivity than the sealing portion 5.

【0020】半導体装置101によれば、以下の効果を
得ることができる。まず、予めに所定の形状に形成され
ている絶縁部材7が素子搭載部2Dの表面2S2側に配
置されている。このとき、絶縁部材7の表面7S1の周
縁7Aは素子搭載部2Dの表面2S2の周縁2DAを取
り囲んでいる。このため、当該絶縁部材7によって素子
搭載部2Dの表面2S1側の絶縁性を確保することがで
きる。
According to the semiconductor device 101, the following effects can be obtained. First, an insulating member 7 formed in a predetermined shape in advance is arranged on the surface 2S2 side of the element mounting portion 2D. At this time, the periphery 7A of the surface 7S1 of the insulating member 7 surrounds the periphery 2DA of the surface 2S2 of the element mounting portion 2D. For this reason, the insulating property on the surface 2S1 side of the element mounting portion 2D can be ensured by the insulating member 7.

【0021】絶縁部材7は封止部5と比較して熱伝導率
が高いので、従来の半導体装置101Pと比較して高い
放熱性を得ることができる。
Since the insulating member 7 has a higher thermal conductivity than the sealing portion 5, it is possible to obtain higher heat dissipation than the conventional semiconductor device 101P.

【0022】ここで、上述の絶縁性と放熱性に関して具
体例を挙げて説明する。図10の従来の半導体装置10
1Pにおいて、封止樹脂5Pを成すエポキシ樹脂の耐圧
が10kV/mmであり厚さtが0.1mmの場合、封
止樹脂5PPの耐圧は1kVである。上述のようにエポ
キシ樹脂の熱伝導率は2W/(m・K)程度である一
方、絶縁部材7を成すセラミックの熱伝導率は20W/
(m・K)程度であるので、封止樹脂5PPと同じ熱伝
導性ないしは放熱性を得る場合、絶縁部材7を約1mm
の厚さに設定することができる。このとき、絶縁部材7
としてエポキシ樹脂と同じ10kV/mm程度の耐圧を
有するセラミックを用いるとすれば、約10kVの耐圧
を確保することができる。逆に耐圧を同じにするときに
は、絶縁部材7によって優れた放熱性が得られる。更に
は、絶縁部材7によれば、従来の半導体装置101Pと
比較して、絶縁性及び放熱性を同時に向上することがで
きる。
Here, the above-mentioned insulation and heat dissipation will be described with reference to specific examples. Conventional semiconductor device 10 of FIG.
In 1P, when the withstand voltage of the epoxy resin forming the sealing resin 5P is 10 kV / mm and the thickness t is 0.1 mm, the withstand voltage of the sealing resin 5PP is 1 kV. As described above, the thermal conductivity of the epoxy resin is about 2 W / (m · K), while the thermal conductivity of the ceramic forming the insulating member 7 is 20 W / (m · K).
(M · K), when the same thermal conductivity or heat radiation as the sealing resin 5PP is to be obtained, the insulating member 7 must be about 1 mm
Thickness can be set. At this time, the insulating member 7
If a ceramic having a withstand voltage of about 10 kV / mm, which is the same as that of the epoxy resin, is used, a withstand voltage of about 10 kV can be secured. Conversely, when the breakdown voltage is the same, excellent heat radiation can be obtained by the insulating member 7. Further, according to the insulating member 7, the insulating property and the heat radiation property can be simultaneously improved as compared with the conventional semiconductor device 101P.

【0023】次に、絶縁部材7の表面7S2の全面が露
出しており封止部5で覆われていないことによって、以
下の効果が得られる。即ち、半導体装置101によれ
ば、従来の半導体装置101P(図10参照)とは異な
り、例えばトランスファモールド法等により封止部5を
形成する場合に素子搭載部2Dの表面2S2側に封止部
5の材料を充填する必要が無い。従って、素子搭載部2
Dの表面2S2側において封止部5の形成不具合が発生
することが無い。加えて、そのような封止部の形成不具
合に起因する絶縁性の低下が惹起されないので、かかる
点からも高い絶縁性が得られる。
Next, since the entire surface 7S2 of the insulating member 7 is exposed and not covered with the sealing portion 5, the following effects can be obtained. That is, according to the semiconductor device 101, unlike the conventional semiconductor device 101P (see FIG. 10), for example, when the sealing portion 5 is formed by the transfer molding method or the like, the sealing portion is formed on the surface 2S2 side of the element mounting portion 2D. There is no need to fill the material of No. 5. Therefore, the element mounting part 2
The formation failure of the sealing portion 5 does not occur on the surface 2S2 side of D. In addition, since a decrease in insulation due to such a formation failure of the sealing portion is not caused, high insulation can be obtained from this point.

【0024】更に、上述のように素子搭載部2Dの表面
2S2側に封止部5の材料を充填する必要が無いので、
封止部5の材料に求められる流動性の条件を緩和するこ
とができる。また、従来の半導体装置101Pとは異な
り、素子搭載部2Dの表面2S2側からの放熱は絶縁部
材を介して行われる。このため、封止部5の材料に求め
られる熱伝導性(放熱性)の条件を緩和することができ
る。従って、従来の封止部5P(図10参照)よりも安
価な材料を用いることができるので、半導体装置の低コ
スト化・低価格化を図ることができる。
Further, since it is not necessary to fill the material of the sealing portion 5 on the surface 2S2 side of the element mounting portion 2D as described above,
Fluidity requirements for the material of the sealing portion 5 can be relaxed. Further, unlike the conventional semiconductor device 101P, heat radiation from the surface 2S2 side of the element mounting portion 2D is performed via an insulating member. For this reason, the condition of thermal conductivity (heat dissipation) required for the material of the sealing portion 5 can be relaxed. Therefore, since a material that is less expensive than the conventional sealing portion 5P (see FIG. 10) can be used, the cost and price of the semiconductor device can be reduced.

【0025】更に、半導体装置101では、絶縁部材7
の表面7S2の全面が露出しており、上記表面7S2と
封止部5の外表面5Sとが平坦を成している。このた
め、絶縁部材7に接して、放熱フィン等の放熱部材(後
述の図6の放熱部材20を参照)を設ける場合、絶縁部
材7の表面7S2と放熱部材とを確実に接触させること
ができるし、絶縁部材7の表面7S2全体を介して放熱
部材へ熱伝導することができる。従って、放熱の安定化
及び向上を図ることができる。また、半導体装置101
の外表面において絶縁部材7の表面7S2が凹部を成す
場合と比較して、上記放熱部材の形状の自由度が大き
い。
Further, in the semiconductor device 101, the insulating member 7
The entire surface of the surface 7S2 is exposed, and the surface 7S2 and the outer surface 5S of the sealing portion 5 are flat. Therefore, when a heat radiating member such as a heat radiating fin (see a heat radiating member 20 in FIG. 6 described later) is provided in contact with the insulating member 7, the surface 7S2 of the insulating member 7 and the heat radiating member can be reliably brought into contact. Then, heat can be conducted to the heat radiating member through the entire surface 7S2 of the insulating member 7. Therefore, heat radiation can be stabilized and improved. Further, the semiconductor device 101
As compared with the case where the surface 7S2 of the insulating member 7 forms a concave portion on the outer surface of the above, the degree of freedom of the shape of the heat radiating member is greater.

【0026】また、絶縁部材7の表面7S2はろう材6
で以て素子搭載部2Dに固定されている。このため、絶
縁部材7と素子搭載部2Dとを隙間無く接合することが
できるので、放熱の安定化及び向上を図ることができ
る。
The surface 7S2 of the insulating member 7 is
Thus, it is fixed to the element mounting portion 2D. For this reason, since the insulating member 7 and the element mounting portion 2D can be joined without a gap, the heat radiation can be stabilized and improved.

【0027】ところで、絶縁部材7ではなく金属絶縁基
板を備えた半導体装置が特開平7−45765号公報に
開示されている。上記金属絶縁板は、ヒートシンクとな
る金属板と、当該金属板上に接合した絶縁層と、当該絶
縁層上に形成されてダイパッド等に接する導体パターン
とから成る。ここで、金属絶縁基板の絶縁層の耐圧−時
間特性の概略を図11に示す。図11に示すように、金
属絶縁基板の絶縁層は、電圧が長時間かかると耐圧が低
下するという傾向を有する。これに対して、半導体装置
101の絶縁部材7はセラミックから成るので、そのよ
うな傾向は見られない。
A semiconductor device provided with a metal insulating substrate instead of the insulating member 7 is disclosed in Japanese Patent Application Laid-Open No. 7-45765. The metal insulating plate includes a metal plate serving as a heat sink, an insulating layer bonded on the metal plate, and a conductor pattern formed on the insulating layer and in contact with a die pad or the like. Here, FIG. 11 schematically shows the withstand voltage-time characteristics of the insulating layer of the metal insulating substrate. As shown in FIG. 11, the insulating layer of the metal insulating substrate has a tendency that the withstand voltage decreases when a voltage is applied for a long time. On the other hand, since the insulating member 7 of the semiconductor device 101 is made of ceramic, such a tendency is not observed.

【0028】また、一般的に、金属絶縁基板の絶縁層は
0.1〜0.2mm程度の厚さであり熱伝導率は1〜3
W/(m・K)程度である。これに対して、半導体装置
101の絶縁部材7は0.5mm程度の厚さであり熱伝
導率は20W/(m・K)程度である。つまり、絶縁部
材7によれば、上記絶縁層と比較して、厚さは約2.5
〜5倍になるものの、放熱性は約10〜20倍大きいと
いう利点がある。
Generally, the insulating layer of the metal insulating substrate has a thickness of about 0.1 to 0.2 mm and a thermal conductivity of 1 to 3 mm.
It is about W / (m · K). On the other hand, the insulating member 7 of the semiconductor device 101 has a thickness of about 0.5 mm and a thermal conductivity of about 20 W / (m · K). In other words, according to the insulating member 7, the thickness is about 2.5 in comparison with the insulating layer.
There is an advantage that the heat dissipation is about 10 to 20 times greater, although it is up to 5 times.

【0029】また、絶縁材を備えた半導体装置が特開平
6−209054号公報に開示されている。しかしなが
ら、当該公報に開示される絶縁材は載置部(素子搭載部
2Dに対応する)よりも小さいという点において、絶縁
部材7とは異なる。詳細には、上記公報に開示される半
導体装置の封止材(封止部5に対応する)は載置部の下
面において額縁状に形成されており、かかる額縁状の開
口から露出した載置部の下面に接して絶縁材が配置され
ている。このため、絶縁部材7とは逆に、上記絶縁材の
周縁は載置部の周縁よりも内側に配置されている。
A semiconductor device provided with an insulating material is disclosed in Japanese Patent Application Laid-Open No. 6-209054. However, the insulating material disclosed in the publication is different from the insulating member 7 in that the insulating material is smaller than the mounting portion (corresponding to the element mounting portion 2D). In detail, the sealing material (corresponding to the sealing portion 5) of the semiconductor device disclosed in the above publication is formed in a frame shape on the lower surface of the mounting portion, and the mounting portion exposed from the frame-shaped opening. An insulating material is disposed in contact with the lower surface of the portion. Therefore, contrary to the insulating member 7, the peripheral edge of the insulating material is disposed inside the peripheral edge of the mounting portion.

【0030】更に、上記絶縁材の露出表面(表面7S2
に対応する)は半導体装置の外表面において凹部を成し
ている点で、半導体装置101とは異なる。
Further, the exposed surface of the insulating material (surface 7S2
Is different from the semiconductor device 101 in that a concave portion is formed on the outer surface of the semiconductor device.

【0031】<実施の形態1の変形例1>図3に本変形
例1に係る第1の半導体装置101Aを説明するための
縦断面図を示す。なお、以下の説明において、既述の構
成要素と同等のものには同一の符号を付して、その説明
を援用する。図3と既述の図1とを比較すれば分かるよ
うに、半導体装置101Aでは絶縁部材7の側面7S3
の一部が封止部5に覆われずに露出している。
<First Modification of First Embodiment> FIG. 3 is a longitudinal sectional view illustrating a first semiconductor device 101A according to the first modification. In the following description, the same reference numerals are given to the same components as those described above, and the description is used. As can be seen by comparing FIG. 3 with FIG. 1 described above, in the semiconductor device 101A, the side surface 7S3 of the insulating member 7 is formed.
Are exposed without being covered by the sealing portion 5.

【0032】なお、絶縁部材7の側面7S3の全部が露
出していても構わない。このとき、図4及び図5の各縦
断面図に示す本変形例1に係る第2及び第3の各半導体
装置101B,101Cのように、絶縁部材7の大きさ
を図1の半導体装置101等よりも大きくしても構わな
い。半導体装置101Cでは絶縁部材7の表面7S1の
周縁部も露出している。
The entire side surface 7S3 of the insulating member 7 may be exposed. At this time, as in the second and third semiconductor devices 101B and 101C according to the first modification shown in the vertical sectional views of FIGS. 4 and 5, the size of the insulating member 7 is changed to the semiconductor device 101 of FIG. It may be larger than etc. In the semiconductor device 101C, the periphery of the surface 7S1 of the insulating member 7 is also exposed.

【0033】半導体装置101A〜101Cによれば、
絶縁部材7の側面7S3が更に露出しているので、封止
部5を介さずに側面7S3から直接に放熱が可能であ
る。従って、上述の半導体装置101と比較して、更な
る放熱の安定化及び向上を図ることができる。また、半
導体装置101と同様に、絶縁部材7に接して放熱部材
を設ける場合において放熱部材の形状の自由度が大き
い。
According to the semiconductor devices 101A to 101C,
Since the side surface 7S3 of the insulating member 7 is further exposed, heat can be radiated directly from the side surface 7S3 without passing through the sealing portion 5. Therefore, the heat radiation can be further stabilized and improved as compared with the above-described semiconductor device 101. Also, as in the case of the semiconductor device 101, when a heat radiating member is provided in contact with the insulating member 7, the degree of freedom of the shape of the heat radiating member is large.

【0034】<実施の形態1の変形例2>なお、絶縁部
材の表面7S1上に薄い金属層(図示せず)を設けても
良い。かかる金属層は、金属ペーストを塗布し、これを
焼成することにより形成される。このとき、当該金属層
を表面7S1上の全面に形成しても構わないし、種々の
形状にパターン形成しても構わない。
<Modification 2 of First Embodiment> A thin metal layer (not shown) may be provided on the surface 7S1 of the insulating member. Such a metal layer is formed by applying a metal paste and firing it. At this time, the metal layer may be formed on the entire surface on the surface 7S1, or may be formed into a pattern in various shapes.

【0035】当該金属層によればろう材6と絶縁部材7
との密着性が更に向上するので、絶縁部材7と素子搭載
部2Dとを良好に密着することができる。これにより、
素子搭載部2Dと絶縁部材7と間の接触熱抵抗が低減す
るので、絶縁部材7を介した放熱の安定化及び向上を図
ることができる。
According to the metal layer, the brazing material 6 and the insulating member 7
Therefore, the insulating member 7 and the element mounting portion 2D can be satisfactorily adhered to each other. This allows
Since the contact thermal resistance between the element mounting portion 2D and the insulating member 7 is reduced, the heat radiation via the insulating member 7 can be stabilized and improved.

【0036】ところで、絶縁部材7がセラミックの場合
(局所的な)うねりを有することがある。このような場
合、上記金属層を適切にパターニングすることによっ
て、そのようなうねりを軽減・解消することができる。
このとき、絶縁部材7の表面7S2にも金属層を設ける
ことによって、また、各表面7S1,7S2上の各金属
層の厚さを制御することによって、より効果的にうねり
を軽減・解消することができる。
When the insulating member 7 is made of ceramic, it may have a (local) undulation. In such a case, by appropriately patterning the metal layer, such undulation can be reduced or eliminated.
At this time, by providing a metal layer also on the surface 7S2 of the insulating member 7 and by controlling the thickness of each metal layer on each surface 7S1 and 7S2, it is possible to more effectively reduce and eliminate the undulation. Can be.

【0037】<実施の形態2>図6に、実施の形態2に
係る半導体装置102を説明するための縦断面図を示
す。なお、図6では半導体装置102に放熱部材20、
例えば放熱フィンが設けられた場合を図示している。図
6と既述の図1とを比較すれば分かるように、絶縁部材
7に代えて半導体装置102は、凸形状ないしは山型の
絶縁部材17を備える。
<Second Preferred Embodiment> FIG. 6 is a longitudinal sectional view illustrating a semiconductor device 102 according to a second preferred embodiment. In FIG. 6, the heat dissipation member 20 is provided on the semiconductor device 102.
For example, a case where a radiation fin is provided is illustrated. As can be seen by comparing FIG. 6 with FIG. 1 described above, the semiconductor device 102 includes a convex or mountain-shaped insulating member 17 instead of the insulating member 7.

【0038】詳細には、絶縁部材17は既述の各表面7
S1,7S2,7S3(図1参照)に相当する各表面1
7S1,17S2,17S3を有し、表面17S2,1
7S1の中央がその周縁に対して凸形状を成している。
特に、絶縁部材17は素子搭載部2Dとは反対側に向か
って、換言すれば半導体装置102の外側に向かって突
出する凸形状を有している。そして、絶縁部材17の表
面17S2は放熱グリス(熱伝導率は1W/(m・K)
程度)21を介して放熱部材20に接触している。
In detail, the insulating member 17 is provided on each of the surfaces 7 described above.
Each surface 1 corresponding to S1, 7S2, 7S3 (see FIG. 1)
7S1, 17S2, 17S3 and the surface 17S2,1
The center of 7S1 has a convex shape with respect to its periphery.
In particular, the insulating member 17 has a convex shape protruding toward the side opposite to the element mounting portion 2D, in other words, toward the outside of the semiconductor device 102. The surface 17S2 of the insulating member 17 is provided with heat-radiating grease (thermal conductivity is 1 W / (m · K)).
(Degree) 21 is in contact with the heat radiation member 20.

【0039】絶縁部材17の凸形状は例えば既述の絶縁
部材7を用いて以下のようにして形成される。即ち、平
板状の絶縁部材7の中央に荷重を加えた状態で、例えば
表面17S1上におもりを載せた状態で熱処理を施すこ
とによって、絶縁部材17の凸形状を形成することがで
きる。また、実施の形態1の変形例2で述べた金属層に
よって、かかる凸形状を形成することも可能である。
The convex shape of the insulating member 17 is formed, for example, by using the above-described insulating member 7 as follows. That is, the convex shape of the insulating member 17 can be formed by applying a heat treatment in a state where a load is applied to the center of the flat insulating member 7, for example, with a weight placed on the surface 17S1. Further, such a convex shape can be formed by the metal layer described in the second modification of the first embodiment.

【0040】ここで、図7に、実施の形態2に係る他の
半導体装置102Aを説明するための縦断面図を示す。
図7と図6とを比較すれば分かるように、半導体装置1
02Aは、絶縁部材17に代えて、当該絶縁部材17と
は逆方向に凸形状を成した絶縁部材17Aを備える。
FIG. 7 is a longitudinal sectional view for explaining another semiconductor device 102A according to the second embodiment.
As can be seen by comparing FIG. 7 and FIG.
02A includes, instead of the insulating member 17, an insulating member 17A having a convex shape in a direction opposite to the insulating member 17.

【0041】両半導体装置102,102Aによっても
既述の半導体装置101が奏する効果を得ることができ
る。特に、半導体装置102によれば、以下の効果をも
得ることができる。
With the two semiconductor devices 102 and 102A, the effect of the semiconductor device 101 described above can be obtained. In particular, according to the semiconductor device 102, the following effects can also be obtained.

【0042】半導体装置102,102Aと放熱部材2
0を接触させる際、絶縁部材17,17A及び/又は放
熱部材20に放熱グリス21を塗布した後に両者を接触
させる。このとき、半導体装置102Aでは、絶縁部材
17Aと放熱部材20との間に放熱グリス21が留まっ
てしまい、絶縁部材17Aと放熱部材20とが接触しな
い場合が生じうる。また、放熱グリス21が少量の場
合、絶縁部材17Aと放熱部材20との間に隙間が、即
ち空気の層が残ってしまう場合がある。
Semiconductor devices 102 and 102A and heat radiating member 2
When contacting 0, heat insulating grease 21 is applied to insulating members 17, 17A and / or heat radiating member 20, and then both are brought into contact. At this time, in the semiconductor device 102A, the heat dissipation grease 21 may remain between the insulating member 17A and the heat dissipation member 20, and the insulating member 17A and the heat dissipation member 20 may not contact with each other. When the amount of the heat radiation grease 21 is small, a gap between the insulating member 17A and the heat radiation member 20, that is, an air layer may remain.

【0043】これに対して、半導体装置102の絶縁部
材17は外側に向かって凸形状を成しているので、半導
体装置102と放熱部材20とを接触させる際に絶縁部
材17が余分な放熱グリス21を横に押し退ける。この
ため、放熱グリス21の塗布量に関わらず、絶縁部材1
7の凸形状の頂部を放熱部材20に確実に接触させるこ
とができるし、適量の換言すれば不必要に厚くない放熱
グリス21を配置することができる。
On the other hand, since the insulating member 17 of the semiconductor device 102 has a convex shape toward the outside, when the semiconductor device 102 and the heat radiating member 20 are brought into contact with each other, the insulating member 17 becomes unnecessary heat radiating grease. Push 21 sideways. Therefore, regardless of the amount of the heat radiation grease 21, the insulating member 1
7 can be reliably brought into contact with the heat dissipating member 20, and the heat dissipating grease 21 that is not unnecessarily thick can be disposed in an appropriate amount.

【0044】このとき、絶縁部材と放熱部材とが接して
いる方が放熱性がより高い点及び一般的に放熱グリス2
1の方が空気よりも熱伝導率が高い点に鑑みれば、半導
体装置102A,101等と比較して、半導体装置10
2の方が放熱部材20との間の熱抵抗を低減することが
できる。従って、放熱の安定化及び向上を図ることがで
きる。
At this time, when the insulating member and the heat radiating member are in contact with each other, the heat radiating property is higher and the heat radiating grease 2 is generally used.
Considering that the thermal conductivity of the semiconductor device 10 is higher than that of the air, the semiconductor device 10 has a higher thermal conductivity than the semiconductor devices 102A, 101 and the like.
2 can reduce the thermal resistance between itself and the heat radiating member 20. Therefore, heat radiation can be stabilized and improved.

【0045】このとき、絶縁部材17の少なくとも表面
17S2が半導体装置102の外側に向かって凸形状を
成していれば、かかる効果を得ることができる。また、
絶縁部材(の表面17S2に相当する表面)が円筒の一
部にあたる形状であっても構わない。
At this time, if at least the surface 17S2 of the insulating member 17 has a convex shape toward the outside of the semiconductor device 102, such an effect can be obtained. Also,
The insulating member (the surface corresponding to the surface 17S2) may have a shape corresponding to a part of a cylinder.

【0046】<実施の形態3>図8及び図9にそれぞれ
実施の形態3に係る半導体装置103を説明するための
縦断面図及び上面図を示す。図9中のI−I線における
縦断面図が図8にあたる。また、図9では、絶縁部材7
及び封止部5をそれぞれ太線及び破線で図示している。
Third Embodiment FIGS. 8 and 9 are a vertical sectional view and a top view, respectively, for explaining a semiconductor device 103 according to a third embodiment. FIG. 8 is a longitudinal sectional view taken along the line II in FIG. Also, in FIG.
And the sealing part 5 are shown by a thick line and a broken line, respectively.

【0047】図8及び図9に示すように、半導体装置1
03は、図1の半導体装置101の構成に加えて、電力
用半導体素子1を制御するための制御回路8を更に備え
る。半導体装置103は、いわゆるDIPタイプのIP
M(Intelligent Power Module)にあたる。
As shown in FIGS. 8 and 9, the semiconductor device 1
Reference numeral 03 further includes a control circuit 8 for controlling the power semiconductor element 1 in addition to the configuration of the semiconductor device 101 of FIG. The semiconductor device 103 is a so-called DIP type IP.
M (Intelligent Power Module).

【0048】制御回路8は、いわゆるプリント回路板
(Printed Circuit Board;PCB)から成り、所定の
配線を有する例えばガラスエポキシ樹脂基板と上記配線
に接続された半導体チップや抵抗、コンデンサ等の部品
とを含む。このとき、抵抗等の部品をエポキシ樹脂基板
上にプリント部品として形成しても構わない。なお、図
面の煩雑化を避けるため、図8及び図9では制御回路8
の詳細な図示化を省略している。
The control circuit 8 is composed of a so-called printed circuit board (PCB) and includes, for example, a glass epoxy resin substrate having predetermined wiring and components such as a semiconductor chip, a resistor, and a capacitor connected to the wiring. Including. At this time, components such as resistors may be formed as printed components on the epoxy resin substrate. In order to avoid complication of the drawings, FIGS.
Are omitted from the illustration.

【0049】制御回路8は電極フレーム2の制御回路8
用の素子搭載部2D2にろう材9によって固定されてお
り、制御回路8とリード部2Lとの間等が金属細線4で
接続されている。
The control circuit 8 controls the control circuit 8 of the electrode frame 2.
Is fixed to the element mounting portion 2D2 for use with a brazing material 9, and a thin metal wire 4 connects between the control circuit 8 and the lead portion 2L.

【0050】このように、半導体装置103は半導体素
子1及び制御回路8を備えるので、半導体装置101等
と比較して高機能化を図ることができる。
As described above, since the semiconductor device 103 includes the semiconductor element 1 and the control circuit 8, it is possible to achieve a higher function than the semiconductor device 101 and the like.

【0051】<まとめ>なお、電力用半導体素子1の代
わりに電力用ではないが発熱の比較的大きい半導体素子
を備えた半導体装置においても既述の効果を得ることが
できる。
<Summary> It should be noted that the above-described effects can be obtained also in a semiconductor device having a semiconductor element which is not for power but generates relatively large heat instead of the power semiconductor element 1.

【0052】[0052]

【発明の効果】(1)請求項1に係る発明によれば、
(予めに所定の形状に形成されている)絶縁部材が素子
搭載部の他方の表面側に配置されており、絶縁部材の第
1表面の周縁は素子搭載部の上記他方の表面の周縁を取
り囲んでいる。このため、当該絶縁部材によって素子搭
載部の他方の表面側の絶縁性を確保することができる。
(1) According to the first aspect of the present invention,
An insulating member (preformed in a predetermined shape) is disposed on the other surface side of the element mounting portion, and a periphery of the first surface of the insulating member surrounds a periphery of the other surface of the element mounting portion. In. Therefore, the insulating property on the other surface side of the element mounting portion can be ensured by the insulating member.

【0053】更に、絶縁部材の第2表面の全面が露出し
ており封止部に覆われていない。即ち、当該絶縁部材を
有さず、電極フレームの素子搭載部の他方の表面を覆っ
て封止部が形成されている従来の半導体装置とは異な
り、例えばトランスファモールド法等により封止部を形
成する場合に素子搭載部の他方の表面側に封止部の材料
を充填する必要が無い。従って、素子搭載部の他方の表
面側において封止部の形成不具合が発生することが無
い。加えて、そのような封止部の形成不具合に起因する
絶縁性の低下が惹起されないので、かかる点からも高い
絶縁性が得られる。
Further, the entire surface of the second surface of the insulating member is exposed and is not covered by the sealing portion. That is, unlike the conventional semiconductor device in which the sealing member is formed so as to cover the other surface of the element mounting portion of the electrode frame without the insulating member, the sealing portion is formed by, for example, a transfer molding method. In this case, it is not necessary to fill the other surface side of the element mounting portion with the material of the sealing portion. Therefore, there is no occurrence of a failure in forming the sealing portion on the other surface side of the element mounting portion. In addition, since a decrease in insulation due to such a formation failure of the sealing portion is not caused, high insulation can be obtained from this point.

【0054】更に、上述のように素子搭載部の他方の表
面側に封止部の材料を充填する必要が無いので、封止部
の材料に求められる流動性の条件を緩和することができ
る。また、従来の半導体装置とは異なり、素子搭載部の
他方の表面側からの放熱は絶縁部材を介して行われる。
このため、封止部の材料に求められる熱伝導性(放熱
性)の条件を緩和することができる。従って、従来の封
止部よりも安価な材料を用いることができるので、半導
体装置の低コスト化・低価格化を図ることができる。
Further, as described above, it is not necessary to fill the other surface side of the element mounting portion with the material of the sealing portion, so that the fluidity condition required for the material of the sealing portion can be relaxed. Further, unlike the conventional semiconductor device, heat radiation from the other surface side of the element mounting portion is performed via the insulating member.
For this reason, the condition of thermal conductivity (heat dissipation) required for the material of the sealing portion can be relaxed. Therefore, since a material that is less expensive than the conventional sealing portion can be used, the cost and price of the semiconductor device can be reduced.

【0055】(2)請求項2に係る発明によれば、第2
表面と封止部の外表面とが平坦を成す。このため、絶縁
部材に接して放熱部材を設ける場合、絶縁部材の第2表
面と放熱部材とを確実に接触させることができるし、絶
縁部材の第2表面全体を介して放熱部材へ熱伝導するこ
とができる。従って、放熱の安定化及び向上を図ること
ができる。また、半導体装置の外表面において絶縁部材
の第2表面が凹部を成す場合と比較して、上記放熱部材
の形状の自由度が大きい。
(2) According to the second aspect of the invention, the second
The surface and the outer surface of the sealing part are flat. For this reason, when the heat radiating member is provided in contact with the insulating member, the second surface of the insulating member and the heat radiating member can be reliably brought into contact with each other, and heat is transmitted to the heat radiating member through the entire second surface of the insulating member. be able to. Therefore, heat radiation can be stabilized and improved. In addition, the degree of freedom of the shape of the heat radiating member is greater than when the second surface of the insulating member forms a concave portion on the outer surface of the semiconductor device.

【0056】(3)請求項3に係る発明によれば、絶縁
部材の第3表面が更に露出しているので、第3表面から
直接に放熱が可能である。従って、放熱の安定化及び向
上を図ることができる。また、絶縁部材に接して放熱部
材を設ける際に、半導体装置の外表面において絶縁部材
の第2表面が凹部を成す場合と比較して、上記放熱部材
の形状の自由度が大きい。
(3) According to the third aspect of the present invention, since the third surface of the insulating member is further exposed, heat can be directly radiated from the third surface. Therefore, heat radiation can be stabilized and improved. Further, when the heat radiating member is provided in contact with the insulating member, the degree of freedom of the shape of the heat radiating member is greater than when the second surface of the insulating member forms a concave portion on the outer surface of the semiconductor device.

【0057】(4)請求項4に係る発明によれば、絶縁
部材は接着材で以て素子搭載部に固定されている。この
ため、絶縁部材と素子搭載部とを隙間無く接合すること
ができるので、放熱の安定化及び向上を図ることができ
る。
(4) According to the invention of claim 4, the insulating member is fixed to the element mounting portion with an adhesive. For this reason, since the insulating member and the element mounting portion can be joined without a gap, the heat radiation can be stabilized and improved.

【0058】(5)請求項5に係る発明によれば、絶縁
部材は封止部と比較して熱伝導率が高い。このため、上
記従来の半導体装置と比較して高い放熱性を得ることが
できる。
(5) According to the fifth aspect of the invention, the thermal conductivity of the insulating member is higher than that of the sealing portion. Therefore, higher heat dissipation can be obtained as compared with the conventional semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施の形態1に係る半導体装置を説明するた
めの縦断面図である。
FIG. 1 is a longitudinal sectional view illustrating a semiconductor device according to a first embodiment.

【図2】 実施の形態1に係る半導体装置を説明するた
めの上面図である。
FIG. 2 is a top view illustrating the semiconductor device according to the first embodiment;

【図3】 実施の形態1の変形例1に係る第1の半導体
装置を説明するための縦断面図である。
FIG. 3 is a longitudinal sectional view for explaining a first semiconductor device according to a first modification of the first embodiment;

【図4】 実施の形態1の変形例1に係る第2の半導体
装置を説明するための縦断面図である。
FIG. 4 is a longitudinal sectional view illustrating a second semiconductor device according to a first modification of the first embodiment;

【図5】 実施の形態1の変形例1に係る第3の半導体
装置を説明するための縦断面図である。
FIG. 5 is a longitudinal sectional view for explaining a third semiconductor device according to a first modification of the first embodiment;

【図6】 実施の形態2に係る半導体装置を説明するた
めの縦断面図である。
FIG. 6 is a longitudinal sectional view illustrating a semiconductor device according to a second embodiment.

【図7】 実施の形態2に係る他の半導体装置を説明す
るための縦断面図である。
FIG. 7 is a longitudinal sectional view for explaining another semiconductor device according to the second embodiment.

【図8】 実施の形態3に係る半導体装置を説明するた
めの縦断面図である。
FIG. 8 is a longitudinal sectional view illustrating a semiconductor device according to a third embodiment.

【図9】 実施の形態3に係る半導体装置を説明するた
めの上面図である。
FIG. 9 is a top view illustrating a semiconductor device according to a third embodiment.

【図10】 従来の半導体装置を説明するための縦断面
図である。
FIG. 10 is a longitudinal sectional view illustrating a conventional semiconductor device.

【図11】 金属絶縁基板の絶縁層の耐圧−時間特性を
説明するための模式図である。
FIG. 11 is a schematic diagram for explaining a withstand voltage-time characteristic of an insulating layer of a metal insulating substrate.

【符号の説明】[Explanation of symbols]

1 電力用半導体素子(半導体素子)、2 電極フレー
ム、2D 素子搭載部、2DA,7A 周縁、2L リ
ード部、2S1 表面(一方の表面)、2S2表面(他
方の表面)、5 封止部、5S 外表面、6 ろう材
(接着材)、7,17,17A 絶縁部材、7S1,1
7S1 表面(第1表面)、7S2,17S2 表面
(第2表面)、7S3,17S3 表面(第3表面)、
101〜103,101A〜101C,102A 電力
用半導体装置(半導体装置)。
1 Power semiconductor element (semiconductor element), 2 electrode frame, 2D element mounting section, 2DA, 7A peripheral edge, 2L lead section, 2S1 surface (one surface), 2S2 surface (other surface), 5 sealing portion, 5S Outer surface, 6 brazing material (adhesive), 7, 17, 17A insulating member, 7S1, 1
7S1 surface (first surface), 7S2, 17S2 surface (second surface), 7S3, 17S3 surface (third surface),
101 to 103, 101A to 101C, 102A Power semiconductor device (semiconductor device).

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 素子搭載部及びリード部を有する電極フ
レームと、 前記素子搭載部の一方の表面上に搭載された半導体素子
と、 その周縁が前記素子搭載部の他方の表面の周縁を取り囲
んで前記他方の表面に対面する第1表面と、前記第1表
面に対向する第2表面とを有し、前記素子搭載部に固定
された絶縁部材と、 前記絶縁部材の前記第2表面の全面を露出させた状態で
前記絶縁部材に接すると共に前記半導体素子を覆って形
成された封止部とを備えることを特徴とする、半導体装
置。
An electrode frame having an element mounting portion and a lead portion; a semiconductor element mounted on one surface of the element mounting portion; and a peripheral edge surrounding a peripheral edge of the other surface of the element mounting portion. An insulating member having a first surface facing the other surface and a second surface facing the first surface, the insulating member being fixed to the element mounting portion; and an entire surface of the second surface of the insulating member. A semiconductor device comprising: a sealing portion formed in contact with the insulating member in an exposed state and covering the semiconductor element.
【請求項2】 請求項1に記載の半導体装置であって、 前記第2表面と前記封止部の外表面とが平坦を成すこと
を特徴とする、半導体装置。
2. The semiconductor device according to claim 1, wherein the second surface and an outer surface of the sealing portion are flat.
【請求項3】 請求項1に記載の半導体装置であって、 前記絶縁部材は前記第1表面と前記第2表面との間で側
面を成す第3表面を有し、 前記第3表面が更に露出していることを特徴とする、半
導体装置。
3. The semiconductor device according to claim 1, wherein the insulating member has a third surface forming a side surface between the first surface and the second surface, and the third surface further comprises: A semiconductor device, which is exposed.
【請求項4】 請求項1乃至3のいずれかに記載の半導
体装置であって、 前記絶縁部材は接着材で以て前記素子搭載部に固定され
ていることを特徴とする、半導体装置。
4. The semiconductor device according to claim 1, wherein the insulating member is fixed to the element mounting portion with an adhesive.
【請求項5】 請求項1乃至4のいずれかに記載の半導
体装置であって、 前記絶縁部材は前記封止部と比較して熱伝導率が高いこ
とを特徴とする、半導体装置。
5. The semiconductor device according to claim 1, wherein said insulating member has a higher thermal conductivity than said sealing portion.
JP2000042695A 2000-02-21 2000-02-21 Semiconductor device Expired - Lifetime JP4060020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000042695A JP4060020B2 (en) 2000-02-21 2000-02-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000042695A JP4060020B2 (en) 2000-02-21 2000-02-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2001237366A true JP2001237366A (en) 2001-08-31
JP4060020B2 JP4060020B2 (en) 2008-03-12

Family

ID=18565735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000042695A Expired - Lifetime JP4060020B2 (en) 2000-02-21 2000-02-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4060020B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066559A (en) * 2004-08-26 2006-03-09 Fuji Electric Fa Components & Systems Co Ltd Semiconductor module and manufacturing method thereof
JP2008060256A (en) * 2006-08-30 2008-03-13 Renesas Technology Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066559A (en) * 2004-08-26 2006-03-09 Fuji Electric Fa Components & Systems Co Ltd Semiconductor module and manufacturing method thereof
JP2008060256A (en) * 2006-08-30 2008-03-13 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JP4060020B2 (en) 2008-03-12

Similar Documents

Publication Publication Date Title
JP3627738B2 (en) Semiconductor device
CN109637983B (en) Chip packaging
KR100902766B1 (en) Discrete Packages with Insulated Ceramic Heat Sink
CN110914975B (en) power semiconductor module
JPH09260550A (en) Semiconductor device
JP7107295B2 (en) electronic device
JP5126201B2 (en) Semiconductor module and manufacturing method thereof
JP2611671B2 (en) Semiconductor device
JP4046623B2 (en) Power semiconductor module and fixing method thereof
CN117480602A (en) Semiconductor module
CN111834307B (en) Semiconductor Module
JP2008141140A (en) Semiconductor device
JP4060020B2 (en) Semiconductor device
JPH0382060A (en) Semiconductor device
KR20060105403A (en) Package structure with hybrid circuit and composite board
JP2736161B2 (en) Semiconductor device
JPS63190363A (en) Power package
JP2006128571A (en) Semiconductor device
JP2904154B2 (en) Electronic circuit device including semiconductor element
JPH0613487A (en) Multi-chip module
JP3048707B2 (en) Hybrid integrated circuit
JPH07235633A (en) Multi-chip module
JPH11121640A (en) Element package and mounting structure thereof
JPH06104309A (en) Semiconductor device
JPH04320052A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050829

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060131

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070313

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070420

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070626

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070726

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070726

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070925

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071022

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20071130

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071219

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101228

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4060020

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111228

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111228

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121228

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121228

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131228

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term