JP4060020B2

JP4060020B2 - Semiconductor device

Info

Publication number: JP4060020B2
Application number: JP2000042695A
Authority: JP
Inventors: 貴信吉田; 利彰篠原; 寿川藤
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2000-02-21
Filing date: 2000-02-21
Publication date: 2008-03-12
Anticipated expiration: 2020-02-21
Also published as: JP2001237366A

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which does not have the forming inconvenience of a sealing part and whose insulating property and heat radiation property are secured. SOLUTION: A semiconductor device 101 is provided with an electrode frame 2, power semiconductor elements 1, an insulating member 7 constituted of ceramic and a sealing part 5 constituted of epoxy resin. The power semiconductor elements 1 are loaded on the surface 2S1 of the element loading part 2D of the electrode frame 2. The peripheral edge of the surface 7S1 of the insulating member 7 facing the surface 2S2 of the element loading part 2D has a size and a shape large enough to surround the peripheral edge of the surface 2S2 of the element loading part 2D. The peripheral edge of the surface 7S1 is arranged by surrounding the peripheral edge of the surface 2S2 of the element loading part 2D. The sealing part 5 is formed so that it covers the power semiconductor elements 1 and the element loading part 2D and it is brought into contact with the surfaces 7S1 and 7S3 of the insulating member 7. The surface 7S2 of the insulating member 7 is not covered by the sealing part 5 and the whole surface 7S2 is exposed.

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関するものであり、特に、発熱の大きい半導体素子を備えた半導体装置における封止ないしはパッケージの形成及び絶縁性の確保、更には放熱の各技術に関する。
【０００２】
【従来の技術】
図１０に、従来の電力用半導体装置１０１Ｐ（以下、単に半導体装置１０１Ｐとも呼ぶ）を説明するための縦断面図を示す。図１０に示すように、電極フレーム２の素子搭載部ないしはダイパッド２Ｄ上に電力用半導体素子１がろう材３により接合されており、電力用半導体素子１と電極フレーム２のリード部２Ｌとの間等が金属細線４で接続されている。電力用半導体素子１及び素子搭載部２Ｄは封止樹脂５Ｐで以て封止されており、封止樹脂５Ｐにより半導体装置１０１Ｐの絶縁性を確保している。封止樹脂５Ｐは例えばポッティング法やトランスファモールド法により形成される。
【０００３】
【発明が解決しようとする課題】
上述のように、従来の半導体装置１０１Ｐの素子搭載部２Ｄは封止樹脂５Ｐで覆われている。このとき、電力用半導体素子１の素子搭載部２Ｄ側の絶縁性を高めるためには、素子搭載部２Ｄ下方の封止樹脂５Ｐ（封止樹脂５ＰＰ参照）をより厚くする必要がある（厚さｔ参照）。しかしながら、一般的に封止樹脂５Ｐの熱伝導率は低いため、厚さｔを増大させると熱抵抗が大きくなってしまう。即ち、電力用半導体素子１の発熱に対する放熱性が低下してしまう。
【０００４】
他方、放熱性を向上させるために厚さｔを減少させると上述の絶縁性を確保できないばかりでなく、封止樹脂５ＰＰの形成不具合及び当該不具合に起因した絶縁性の低下が惹起される。即ち、封止樹脂５Ｐを例えばポッティング法やトランスファモールド法により形成する場合、厚さｔが小さいと、素子搭載部２Ｄと金型（図示せず）との隙間へ封止樹脂を注入ないしは充填しにくくなる。このため、封止樹脂の充填不足等によって封止樹脂５ＰＰの形成不具合が生じ、かかる形成不具合が封止樹脂５ＰＰにおける絶縁性を低下させてしまう。
【０００５】
本発明はかかる問題点に鑑みてなされたものであり、封止部の形成不具合を有さず絶縁性が確保された半導体装置を提供することを第１の目的とする。
【０００６】
また、本発明は、上記第１の目的を実現しうる半導体装置を低コスト・低価格で提供することを第２の目的とする。
【０００７】
更に、本発明は、上記第１及び第２の目的の実現と共に放熱性の安定化及び向上が図られた半導体装置を提供することを第３の目的とする。
【０００８】
【課題を解決するための手段】
（１）請求項１に記載の発明に係る半導体装置は、素子搭載部及びリード部を有する電極フレームと、前記素子搭載部の一方の表面上に搭載された半導体素子と、その周縁が前記素子搭載部の他方の表面の周縁を取り囲んで前記他方の表面に対面する第１表面と、前記第１表面に対向する第２表面とを有し、前記素子搭載部に固定された絶縁部材と、前記絶縁部材の前記第２表面の全面及び前記第１表面と前記第２表面との間で側面を成す第３表面の少なくとも一部を露出させた状態で前記絶縁部材に接すると共に前記半導体素子を覆って形成された封止部とを備え、前記絶縁部材は、前記第２表面の中央がその周縁に対して凸形状又は凹形状を成していることを特徴とする。
【０００９】
（２）請求項２に記載の発明に係る半導体装置は、請求項１に記載の半導体装置であって、前記封止部は、前記絶縁部材の前記第３表面を全面及び前記第１表面の一部をさらに露出させるように形成されていることを特徴とする。
【００１０】
（３）請求項３に記載の発明に係る半導体装置は、請求項１又は請求項２に記載の半導体装置であって、前記絶縁部材は、少なくとも前記第２表面上に金属層を備えることを特徴とする。
【００１２】
（４）請求項４に記載の発明に係る半導体装置は、素子搭載部及びリード部を有する電極フレームと、前記素子搭載部の一方の表面上に搭載された半導体素子と、その周縁が前記素子搭載部の他方の表面の周縁を取り囲んで前記他方の表面に対面する第１表面と、前記第１表面に対向する第２表面とを有し、前記素子搭載部に固定された絶縁部材と、前記絶縁部材の前記第２表面の全面を露出させた状態で前記絶縁部材に接すると共に前記半導体素子を覆って形成された封止部とを備え、前記絶縁部材は、前記第２表面の中央がその周縁に対して凸形状又は凹形状を成していることを特徴とする。
【００１３】
【発明の実施の形態】
＜実施の形態１＞
図１及び図２にそれぞれ実施の形態１に係る電力用半導体装置（半導体装置）１０１を説明するための縦断面図及び上面図を示す。図２中のＩ−Ｉ線における縦断面図が図１にあたる。また、図２では、絶縁部材７及び封止部５をそれぞれ太線及び破線で図示している。電力用半導体装置１０１（以下、単に半導体装置１０１のように呼ぶ）は、いわゆるＤＩＰ（Dual Inline Package）タイプにあたる。
【００１４】
図１及び図２に示すように、半導体装置１０１は、電極フレーム２と、電力用半導体素子１（図１及び図２では２個を図示している）と、（予めに所定の形状に形成されている）絶縁部材７と、封止部５とを備える。詳細には、電極フレーム２は素子搭載部ないしはダイパッド２Ｄ及びリード部２Ｌを有しており、素子搭載部２Ｄの一方の表面２Ｓ１上に電力用半導体素子１が搭載されている。電力用半導体素子１はろう材３によって素子搭載部２Ｄに固定されている。そして、電力用半導体素子１とリード部２Ｌとの間等が金属細線４で接続されている。
【００１５】
絶縁部材７は、（ａ）素子搭載部２Ｄの他方の表面２Ｓ２に対面する表面（第１表面）７Ｓ１と、（ｂ）表面７Ｓ１に対向する表面（第２表面）７Ｓ２と、（ｃ）表面７Ｓ１，７Ｓ２の双方に結合して両表面７Ｓ１，７Ｓ２と共に絶縁部材７の外表面を成す表面ないしは側面（第３表面）７Ｓ３とを有している。
【００１６】
特に、表面７Ｓ１は、当該表面７Ｓ１の周縁７Ａが素子搭載部２Ｄの表面２Ｓ２の周縁２ＤＡを取り囲みうる寸法・形状を有しており、表面７Ｓ１の周縁７Ａが素子搭載部２Ｄの表面２Ｓ２の周縁２ＤＡを取り囲んで配置されている。このとき、両表面７Ｓ１，７Ｓ２は同じ寸法・形状でなくとも良く、例えば図１における縦断面が台形状であっても構わない。絶縁部材７は例えば０．５ｍｍ程度の厚さのＡｌ２Ｏ３，ＡｌＮ，Ｓｉ３Ｎ４等のセラミック板から成る。
【００１７】
絶縁部材７はろう材（接着材）６によって素子搭載部２Ｄに固定されている。ろう材６及び上記ろう材３として、鉛成分を含まない材料、例えばエポキシ樹脂中に硬化剤ないしは添加剤，銀（Ａｇ）等を添加した樹脂系ろう材を用いている。
【００１８】
封止部５は、電力用半導体素子１及び素子搭載部２Ｄ等を覆って、且つ、絶縁部材７の表面７Ｓ１，７Ｓ３に接して形成されている。特に、絶縁部材７の表面７Ｓ２は封止部５で覆われておらず全面が露出している。また、絶縁部材７の表面７Ｓ２と封止部５の外表面５Ｓとが平坦に繋がっている。即ち、半導体装置１０１の外表面において絶縁部材７の表面７Ｓ２は凹部を形成していない。
【００１９】
封止部５は例えばエポキシ樹脂等の材料から成る。かかるエポキシ樹脂等の熱伝導率は２Ｗ／（ｍ・Ｋ）程度である一方、絶縁部材７を成すアルミナ（Ａｌ２Ｏ３）等の熱伝導率は２０Ｗ／（ｍ・Ｋ）程度である。即ち、絶縁部材７は封止部５と比較して熱伝導率が高い。
【００２０】
半導体装置１０１によれば、以下の効果を得ることができる。
まず、予めに所定の形状に形成されている絶縁部材７が素子搭載部２Ｄの表面２Ｓ２側に配置されている。このとき、絶縁部材７の表面７Ｓ１の周縁７Ａは素子搭載部２Ｄの表面２Ｓ２の周縁２ＤＡを取り囲んでいる。このため、当該絶縁部材７によって素子搭載部２Ｄの表面２Ｓ１側の絶縁性を確保することができる。
【００２１】
絶縁部材７は封止部５と比較して熱伝導率が高いので、従来の半導体装置１０１Ｐと比較して高い放熱性を得ることができる。
【００２２】
ここで、上述の絶縁性と放熱性に関して具体例を挙げて説明する。図１０の従来の半導体装置１０１Ｐにおいて、封止樹脂５Ｐを成すエポキシ樹脂の耐圧が１０ｋＶ／ｍｍであり厚さｔが０．１ｍｍの場合、封止樹脂５ＰＰの耐圧は１ｋＶである。上述のようにエポキシ樹脂の熱伝導率は２Ｗ／（ｍ・Ｋ）程度である一方、絶縁部材７を成すセラミックの熱伝導率は２０Ｗ／（ｍ・Ｋ）程度であるので、封止樹脂５ＰＰと同じ熱伝導性ないしは放熱性を得る場合、絶縁部材７を約１ｍｍの厚さに設定することができる。このとき、絶縁部材７としてエポキシ樹脂と同じ１０ｋＶ／ｍｍ程度の耐圧を有するセラミックを用いるとすれば、約１０ｋＶの耐圧を確保することができる。逆に耐圧を同じにするときには、絶縁部材７によって優れた放熱性が得られる。更には、絶縁部材７によれば、従来の半導体装置１０１Ｐと比較して、絶縁性及び放熱性を同時に向上することができる。
【００２３】
次に、絶縁部材７の表面７Ｓ２の全面が露出しており封止部５で覆われていないことによって、以下の効果が得られる。即ち、半導体装置１０１によれば、従来の半導体装置１０１Ｐ（図１０参照）とは異なり、例えばトランスファモールド法等により封止部５を形成する場合に素子搭載部２Ｄの表面２Ｓ２側に封止部５の材料を充填する必要が無い。従って、素子搭載部２Ｄの表面２Ｓ２側において封止部５の形成不具合が発生することが無い。加えて、そのような封止部の形成不具合に起因する絶縁性の低下が惹起されないので、かかる点からも高い絶縁性が得られる。
【００２４】
更に、上述のように素子搭載部２Ｄの表面２Ｓ２側に封止部５の材料を充填する必要が無いので、封止部５の材料に求められる流動性の条件を緩和することができる。また、従来の半導体装置１０１Ｐとは異なり、素子搭載部２Ｄの表面２Ｓ２側からの放熱は絶縁部材を介して行われる。このため、封止部５の材料に求められる熱伝導性（放熱性）の条件を緩和することができる。従って、従来の封止部５Ｐ（図１０参照）よりも安価な材料を用いることができるので、半導体装置の低コスト化・低価格化を図ることができる。
【００２５】
更に、半導体装置１０１では、絶縁部材７の表面７Ｓ２の全面が露出しており、上記表面７Ｓ２と封止部５の外表面５Ｓとが平坦を成している。このため、絶縁部材７に接して、放熱フィン等の放熱部材（後述の図６の放熱部材２０を参照）を設ける場合、絶縁部材７の表面７Ｓ２と放熱部材とを確実に接触させることができるし、絶縁部材７の表面７Ｓ２全体を介して放熱部材へ熱伝導することができる。従って、放熱の安定化及び向上を図ることができる。また、半導体装置１０１の外表面において絶縁部材７の表面７Ｓ２が凹部を成す場合と比較して、上記放熱部材の形状の自由度が大きい。
【００２６】
また、絶縁部材７の表面７Ｓ２はろう材６で以て素子搭載部２Ｄに固定されている。このため、絶縁部材７と素子搭載部２Ｄとを隙間無く接合することができるので、放熱の安定化及び向上を図ることができる。
【００２７】
ところで、絶縁部材７ではなく金属絶縁基板を備えた半導体装置が特開平７−４５７６５号公報に開示されている。上記金属絶縁板は、ヒートシンクとなる金属板と、当該金属板上に接合した絶縁層と、当該絶縁層上に形成されてダイパッド等に接する導体パターンとから成る。ここで、金属絶縁基板の絶縁層の耐圧−時間特性の概略を図１１に示す。図１１に示すように、金属絶縁基板の絶縁層は、電圧が長時間かかると耐圧が低下するという傾向を有する。これに対して、半導体装置１０１の絶縁部材７はセラミックから成るので、そのような傾向は見られない。
【００２８】
また、一般的に、金属絶縁基板の絶縁層は０．１〜０．２ｍｍ程度の厚さであり熱伝導率は１〜３Ｗ／（ｍ・Ｋ）程度である。これに対して、半導体装置１０１の絶縁部材７は０．５ｍｍ程度の厚さであり熱伝導率は２０Ｗ／（ｍ・Ｋ）程度である。つまり、絶縁部材７によれば、上記絶縁層と比較して、厚さは約２．５〜５倍になるものの、放熱性は約１０〜２０倍大きいという利点がある。
【００２９】
また、絶縁材を備えた半導体装置が特開平６−２０９０５４号公報に開示されている。しかしながら、当該公報に開示される絶縁材は載置部（素子搭載部２Ｄに対応する）よりも小さいという点において、絶縁部材７とは異なる。詳細には、上記公報に開示される半導体装置の封止材（封止部５に対応する）は載置部の下面において額縁状に形成されており、かかる額縁状の開口から露出した載置部の下面に接して絶縁材が配置されている。このため、絶縁部材７とは逆に、上記絶縁材の周縁は載置部の周縁よりも内側に配置されている。
【００３０】
更に、上記絶縁材の露出表面（表面７Ｓ２に対応する）は半導体装置の外表面において凹部を成している点で、半導体装置１０１とは異なる。
【００３１】
＜実施の形態１の変形例１＞
図３に本変形例１に係る第１の半導体装置１０１Ａを説明するための縦断面図を示す。なお、以下の説明において、既述の構成要素と同等のものには同一の符号を付して、その説明を援用する。図３と既述の図１とを比較すれば分かるように、半導体装置１０１Ａでは絶縁部材７の側面７Ｓ３の一部が封止部５に覆われずに露出している。
【００３２】
なお、絶縁部材７の側面７Ｓ３の全部が露出していても構わない。このとき、図４及び図５の各縦断面図に示す本変形例１に係る第２及び第３の各半導体装置１０１Ｂ，１０１Ｃのように、絶縁部材７の大きさを図１の半導体装置１０１等よりも大きくしても構わない。半導体装置１０１Ｃでは絶縁部材７の表面７Ｓ１の周縁部も露出している。
【００３３】
半導体装置１０１Ａ〜１０１Ｃによれば、絶縁部材７の側面７Ｓ３が更に露出しているので、封止部５を介さずに側面７Ｓ３から直接に放熱が可能である。従って、上述の半導体装置１０１と比較して、更なる放熱の安定化及び向上を図ることができる。また、半導体装置１０１と同様に、絶縁部材７に接して放熱部材を設ける場合において放熱部材の形状の自由度が大きい。
【００３４】
＜実施の形態１の変形例２＞
なお、絶縁部材の表面７Ｓ１上に薄い金属層（図示せず）を設けても良い。かかる金属層は、金属ペーストを塗布し、これを焼成することにより形成される。このとき、当該金属層を表面７Ｓ１上の全面に形成しても構わないし、種々の形状にパターン形成しても構わない。
【００３５】
当該金属層によればろう材６と絶縁部材７との密着性が更に向上するので、絶縁部材７と素子搭載部２Ｄとを良好に密着することができる。これにより、素子搭載部２Ｄと絶縁部材７と間の接触熱抵抗が低減するので、絶縁部材７を介した放熱の安定化及び向上を図ることができる。
【００３６】
ところで、絶縁部材７がセラミックの場合（局所的な）うねりを有することがある。このような場合、上記金属層を適切にパターニングすることによって、そのようなうねりを軽減・解消することができる。このとき、絶縁部材７の表面７Ｓ２にも金属層を設けることによって、また、各表面７Ｓ１，７Ｓ２上の各金属層の厚さを制御することによって、より効果的にうねりを軽減・解消することができる。
【００３７】
＜実施の形態２＞
図６に、実施の形態２に係る半導体装置１０２を説明するための縦断面図を示す。なお、図６では半導体装置１０２に放熱部材２０、例えば放熱フィンが設けられた場合を図示している。図６と既述の図１とを比較すれば分かるように、絶縁部材７に代えて半導体装置１０２は、凸形状ないしは山型の絶縁部材１７を備える。
【００３８】
詳細には、絶縁部材１７は既述の各表面７Ｓ１，７Ｓ２，７Ｓ３（図１参照）に相当する各表面１７Ｓ１，１７Ｓ２，１７Ｓ３を有し、表面１７Ｓ２，１７Ｓ１の中央がその周縁に対して凸形状を成している。特に、絶縁部材１７は素子搭載部２Ｄとは反対側に向かって、換言すれば半導体装置１０２の外側に向かって突出する凸形状を有している。そして、絶縁部材１７の表面１７Ｓ２は放熱グリス（熱伝導率は１Ｗ／（ｍ・Ｋ）程度）２１を介して放熱部材２０に接触している。
【００３９】
絶縁部材１７の凸形状は例えば既述の絶縁部材７を用いて以下のようにして形成される。即ち、平板状の絶縁部材７の中央に荷重を加えた状態で、例えば表面１７Ｓ１上におもりを載せた状態で熱処理を施すことによって、絶縁部材１７の凸形状を形成することができる。また、実施の形態１の変形例２で述べた金属層によって、かかる凸形状を形成することも可能である。
【００４０】
ここで、図７に、実施の形態２に係る他の半導体装置１０２Ａを説明するための縦断面図を示す。図７と図６とを比較すれば分かるように、半導体装置１０２Ａは、絶縁部材１７に代えて、当該絶縁部材１７とは逆方向に凸形状を成した絶縁部材１７Ａを備える。
【００４１】
両半導体装置１０２，１０２Ａによっても既述の半導体装置１０１が奏する効果を得ることができる。特に、半導体装置１０２によれば、以下の効果をも得ることができる。
【００４２】
半導体装置１０２，１０２Ａと放熱部材２０を接触させる際、絶縁部材１７，１７Ａ及び／又は放熱部材２０に放熱グリス２１を塗布した後に両者を接触させる。このとき、半導体装置１０２Ａでは、絶縁部材１７Ａと放熱部材２０との間に放熱グリス２１が留まってしまい、絶縁部材１７Ａと放熱部材２０とが接触しない場合が生じうる。また、放熱グリス２１が少量の場合、絶縁部材１７Ａと放熱部材２０との間に隙間が、即ち空気の層が残ってしまう場合がある。
【００４３】
これに対して、半導体装置１０２の絶縁部材１７は外側に向かって凸形状を成しているので、半導体装置１０２と放熱部材２０とを接触させる際に絶縁部材１７が余分な放熱グリス２１を横に押し退ける。このため、放熱グリス２１の塗布量に関わらず、絶縁部材１７の凸形状の頂部を放熱部材２０に確実に接触させることができるし、適量の換言すれば不必要に厚くない放熱グリス２１を配置することができる。
【００４４】
このとき、絶縁部材と放熱部材とが接している方が放熱性がより高い点及び一般的に放熱グリス２１の方が空気よりも熱伝導率が高い点に鑑みれば、半導体装置１０２Ａ，１０１等と比較して、半導体装置１０２の方が放熱部材２０との間の熱抵抗を低減することができる。従って、放熱の安定化及び向上を図ることができる。
【００４５】
このとき、絶縁部材１７の少なくとも表面１７Ｓ２が半導体装置１０２の外側に向かって凸形状を成していれば、かかる効果を得ることができる。また、絶縁部材（の表面１７Ｓ２に相当する表面）が円筒の一部にあたる形状であっても構わない。
【００４６】
＜実施の形態３＞
図８及び図９にそれぞれ実施の形態３に係る半導体装置１０３を説明するための縦断面図及び上面図を示す。図９中のＩ−Ｉ線における縦断面図が図８にあたる。また、図９では、絶縁部材７及び封止部５をそれぞれ太線及び破線で図示している。
【００４７】
図８及び図９に示すように、半導体装置１０３は、図１の半導体装置１０１の構成に加えて、電力用半導体素子１を制御するための制御回路８を更に備える。半導体装置１０３は、いわゆるＤＩＰタイプのＩＰＭ（Intelligent Power Module）にあたる。
【００４８】
制御回路８は、いわゆるプリント回路板（Printed Circuit Board；ＰＣＢ）から成り、所定の配線を有する例えばガラスエポキシ樹脂基板と上記配線に接続された半導体チップや抵抗、コンデンサ等の部品とを含む。このとき、抵抗等の部品をエポキシ樹脂基板上にプリント部品として形成しても構わない。なお、図面の煩雑化を避けるため、図８及び図９では制御回路８の詳細な図示化を省略している。
【００４９】
制御回路８は電極フレーム２の制御回路８用の素子搭載部２Ｄ２にろう材９によって固定されており、制御回路８とリード部２Ｌとの間等が金属細線４で接続されている。
【００５０】
このように、半導体装置１０３は半導体素子１及び制御回路８を備えるので、半導体装置１０１等と比較して高機能化を図ることができる。
【００５１】
＜まとめ＞
なお、電力用半導体素子１の代わりに電力用ではないが発熱の比較的大きい半導体素子を備えた半導体装置においても既述の効果を得ることができる。
【００５２】
【発明の効果】
（１）請求項１に係る発明によれば、（予めに所定の形状に形成されている）絶縁部材が素子搭載部の他方の表面側に配置されており、絶縁部材の第１表面の周縁は素子搭載部の上記他方の表面の周縁を取り囲んでいる。このため、当該絶縁部材によって素子搭載部の他方の表面側の絶縁性を確保することができる。
【００５３】
更に、絶縁部材の第２表面の全面及び前記第１表面と前記第２表面との間で側面を成す第３表面の少なくとも一部が露出しており封止部に覆われていない。即ち、当該絶縁部材を有さず、電極フレームの素子搭載部の他方の表面を覆って封止部が形成されている従来の半導体装置とは異なり、例えばトランスファモールド法等により封止部を形成する場合に素子搭載部の他方の表面側に封止部の材料を充填する必要が無い。従って、素子搭載部の他方の表面側において封止部の形成不具合が発生することが無い。加えて、そのような封止部の形成不具合に起因する絶縁性の低下が惹起されないので、かかる点からも高い絶縁性が得られる。
【００５４】
更に、上述のように素子搭載部の他方の表面側に封止部の材料を充填する必要が無いので、封止部の材料に求められる流動性の条件を緩和することができる。また、従来の半導体装置とは異なり、素子搭載部の他方の表面側からの放熱は絶縁部材を介して行われる。このため、封止部の材料に求められる熱伝導性（放熱性）の条件を緩和することができる。従って、従来の封止部よりも安価な材料を用いることができるので、半導体装置の低コスト化・低価格化を図ることができる。
【００５５】
（２）請求項２に係る発明によれば、絶縁部材の第３表面を全面及び第１表面の一部をさらに露出させるよう形成されている。このため、絶縁部材に接して放熱部材を設ける場合、絶縁部材の第２表面と放熱部材とを確実に接触させることができるし、絶縁部材の第２表面全体及び第３表面全体、第１表面の一部を介して放熱部材へ熱伝導することができる。従って、放熱の安定化及び向上を図ることができる。また、半導体装置の外表面において絶縁部材の第２表面が凹部を成す場合と比較して、上記放熱部材の形状の自由度が大きい。
【００５６】
（３）請求項３に係る発明によれば、絶縁部材は、少なくとも前記第２表面上に金属層を備えるので、絶縁部材の局所的なうねりを軽減・解消することができる。
【００５７】
（４）請求項１に係る発明によれば、絶縁部材は、第２表面の中央がその周縁に対して凸形状又は凹形状を成している。このため、絶縁部材に放熱グリス２１を塗布した放熱部材２０に接触させる場合、放熱グリス２１の塗布量に関わらず、絶縁部材の凸形状の頂部又は凹形状を放熱部材２０に確実に接触させることができ、適量の換言すれば不必要に厚くない放熱グリス２１を配置することができる。
【００５８】
（５）請求項４に係る発明によれば、絶縁部材は、第２表面の中央がその周縁に対して凸形状又は凹形状を成している。このため、絶縁部材に放熱グリス２１を塗布した放熱部材２０に接触させる場合、放熱グリス２１の塗布量に関わらず、絶縁部材の凸形状の頂部又は凹形状を放熱部材２０に確実に接触させることができ、適量の換言すれば不必要に厚くない放熱グリス２１を配置することができる。
【図面の簡単な説明】
【図１】実施の形態１に係る半導体装置を説明するための縦断面図である。
【図２】実施の形態１に係る半導体装置を説明するための上面図である。
【図３】実施の形態１の変形例１に係る第１の半導体装置を説明するための縦断面図である。
【図４】実施の形態１の変形例１に係る第２の半導体装置を説明するための縦断面図である。
【図５】実施の形態１の変形例１に係る第３の半導体装置を説明するための縦断面図である。
【図６】実施の形態２に係る半導体装置を説明するための縦断面図である。
【図７】実施の形態２に係る他の半導体装置を説明するための縦断面図である。
【図８】実施の形態３に係る半導体装置を説明するための縦断面図である。
【図９】実施の形態３に係る半導体装置を説明するための上面図である。
【図１０】従来の半導体装置を説明するための縦断面図である。
【図１１】金属絶縁基板の絶縁層の耐圧−時間特性を説明するための模式図である。
【符号の説明】
１電力用半導体素子（半導体素子）、２電極フレーム、２Ｄ素子搭載部、２ＤＡ，７Ａ周縁、２Ｌリード部、２Ｓ１表面（一方の表面）、２Ｓ２表面（他方の表面）、５封止部、５Ｓ外表面、６ろう材（接着材）、７，１７，１７Ａ絶縁部材、７Ｓ１，１７Ｓ１表面（第１表面）、７Ｓ２，１７Ｓ２表面（第２表面）、７Ｓ３，１７Ｓ３表面（第３表面）、１０１〜１０３，１０１Ａ〜１０１Ｃ，１０２Ａ電力用半導体装置（半導体装置）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a technology for sealing or forming a package and ensuring insulation in a semiconductor device provided with a semiconductor element generating a large amount of heat, and further to heat dissipation.
[0002]
[Prior art]
FIG. 10 is a longitudinal sectional view for explaining a conventional power semiconductor device 101P (hereinafter also simply referred to as a semiconductor device 101P). As shown in FIG. 10, the power semiconductor element 1 is joined to the element mounting portion or the die pad 2 D of the electrode frame 2 by the brazing material 3, and between the power semiconductor element 1 and the lead portion 2 L of the electrode frame 2. Are connected by a thin metal wire 4. The power semiconductor element 1 and the element mounting portion 2D are sealed with a sealing resin 5P, and the insulating property of the semiconductor device 101P is secured by the sealing resin 5P. The sealing resin 5P is formed by, for example, a potting method or a transfer mold method.
[0003]
[Problems to be solved by the invention]
As described above, the element mounting portion 2D of the conventional semiconductor device 101P is covered with the sealing resin 5P. At this time, in order to improve the insulation on the element mounting portion 2D side of the power semiconductor element 1, it is necessary to make the sealing resin 5P below the element mounting portion 2D (see the sealing resin 5PP) thicker (thickness). t). However, since the thermal conductivity of the sealing resin 5P is generally low, increasing the thickness t increases the thermal resistance. In other words, the heat dissipation of the power semiconductor element 1 against heat generation is reduced.
[0004]
On the other hand, if the thickness t is decreased in order to improve heat dissipation, not only the above-described insulation cannot be ensured, but also the formation failure of the sealing resin 5PP and the insulation deterioration due to the failure are caused. That is, when the sealing resin 5P is formed by, for example, the potting method or the transfer molding method, if the thickness t is small, the sealing resin is injected or filled into the gap between the element mounting portion 2D and the mold (not shown). It becomes difficult. For this reason, the formation malfunction of sealing resin 5PP arises by the insufficient filling of sealing resin, etc., and this formation malfunction will reduce the insulation in sealing resin 5PP.
[0005]
The present invention has been made in view of such problems, and a first object of the present invention is to provide a semiconductor device in which insulation is ensured without forming a sealing portion.
[0006]
A second object of the present invention is to provide a semiconductor device capable of realizing the first object at low cost and low price.
[0007]
Furthermore, a third object of the present invention is to provide a semiconductor device in which the heat radiation performance is stabilized and improved while realizing the first and second objects.
[0008]
[Means for Solving the Problems]
(1) According to a first aspect of the present invention, there is provided a semiconductor device comprising: an electrode frame having an element mounting portion and a lead portion; a semiconductor element mounted on one surface of the element mounting portion; An insulating member having a first surface surrounding the periphery of the other surface of the mounting portion and facing the other surface, and a second surface facing the first surface, and fixed to the element mounting portion; The semiconductor element is in contact with the insulating member in a state in which the entire surface of the second surface of the insulating member and at least a part of the third surface forming a side surface between the first surface and the second surface are exposed. The insulating member is characterized in that the center of the second surface has a convex shape or a concave shape with respect to the periphery thereof.
[0009]
(2) The semiconductor device according to the invention described in claim 2 is the semiconductor device according to claim 1, wherein the sealing portion covers the entire third surface of the insulating member and the first surface. It is formed so that a part is further exposed.
[0010]
(3) The semiconductor device according to claim 3 is the semiconductor device according to claim 1 or 2 , wherein the insulating member includes a metal layer on at least the second surface. Features.
[0012]
(4) A semiconductor device according to a fourth aspect of the invention includes an electrode frame having an element mounting portion and a lead portion, a semiconductor element mounted on one surface of the element mounting portion, and a peripheral edge of the semiconductor device. An insulating member having a first surface surrounding the periphery of the other surface of the mounting portion and facing the other surface, and a second surface facing the first surface, and fixed to the element mounting portion; A sealing portion formed so as to be in contact with the insulating member and covering the semiconductor element in a state where the entire surface of the second surface of the insulating member is exposed, and the insulating member has a central portion of the second surface. A convex shape or a concave shape is formed with respect to the peripheral edge.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
1 and 2 are a longitudinal sectional view and a top view, respectively, for explaining a power semiconductor device (semiconductor device) 101 according to the first embodiment. A vertical sectional view taken along line II in FIG. 2 corresponds to FIG. Moreover, in FIG. 2, the insulating member 7 and the sealing part 5 are shown by the thick line and the broken line, respectively. The power semiconductor device 101 (hereinafter simply referred to as the semiconductor device 101) corresponds to a so-called DIP (Dual Inline Package) type.
[0014]
As shown in FIGS. 1 and 2, a semiconductor device 101 includes an electrode frame 2, a power semiconductor element 1 (two are shown in FIGS. 1 and 2), and formed in a predetermined shape in advance. Insulating member 7 and sealing portion 5 are provided. Specifically, the electrode frame 2 has an element mounting portion or die pad 2D and a lead portion 2L, and the power semiconductor element 1 is mounted on one surface 2S1 of the element mounting portion 2D. The power semiconductor element 1 is fixed to the element mounting portion 2D by a brazing material 3. The power semiconductor element 1 and the lead portion 2L are connected by a thin metal wire 4.
[0015]
The insulating member 7 includes (a) a surface (first surface) 7S1 facing the other surface 2S2 of the element mounting portion 2D, (b) a surface (second surface) 7S2 facing the surface 7S1, and (c) a surface. 7S1 and 7S2 are combined with both surfaces 7S1 and 7S2 to form an outer surface of the insulating member 7 or a side surface (third surface) 7S3.
[0016]
In particular, the surface 7S1 has a size and shape that allows the periphery 7A of the surface 7S1 to surround the periphery 2DA of the surface 2S2 of the element mounting portion 2D, and the periphery 7A of the surface 7S1 is the periphery of the surface 2S2 of the element mounting portion 2D. It is arranged around 2DA. At this time, both surfaces 7S1 and 7S2 do not have to have the same size and shape. For example, the longitudinal section in FIG. 1 may have a trapezoidal shape. The insulating member 7 is made of a ceramic plate made of Al2O3, AlN, Si3N4 or the like having a thickness of about 0.5 mm.
[0017]
The insulating member 7 is fixed to the element mounting portion 2D by a brazing material (adhesive material) 6. As the brazing material 6 and the brazing material 3, a material that does not contain a lead component, for example, a resin brazing material in which a curing agent or additive, silver (Ag), or the like is added to an epoxy resin is used.
[0018]
The sealing portion 5 is formed so as to cover the power semiconductor element 1, the element mounting portion 2 D, and the like and in contact with the surfaces 7 S 1 and 7 S 3 of the insulating member 7. In particular, the surface 7S2 of the insulating member 7 is not covered with the sealing portion 5, and the entire surface is exposed. Further, the surface 7S2 of the insulating member 7 and the outer surface 5S of the sealing portion 5 are connected flatly. That is, on the outer surface of the semiconductor device 101, the surface 7S2 of the insulating member 7 does not form a recess.
[0019]
The sealing part 5 is made of a material such as an epoxy resin. The thermal conductivity of the epoxy resin or the like is about 2 W / (m · K), while the thermal conductivity of alumina (Al 2 O 3) or the like constituting the insulating member 7 is about 20 W / (m · K). That is, the insulating member 7 has a higher thermal conductivity than the sealing portion 5.
[0020]
According to the semiconductor device 101, the following effects can be obtained.
First, the insulating member 7 formed in a predetermined shape in advance is disposed on the surface 2S2 side of the element mounting portion 2D. At this time, the peripheral edge 7A of the surface 7S1 of the insulating member 7 surrounds the peripheral edge 2DA of the surface 2S2 of the element mounting portion 2D. For this reason, the insulating member 7 can ensure the insulation on the surface 2S1 side of the element mounting portion 2D.
[0021]
Since the insulating member 7 has a higher thermal conductivity than the sealing portion 5, a higher heat dissipation can be obtained as compared with the conventional semiconductor device 101 P.
[0022]
Here, a specific example is given and demonstrated about the above-mentioned insulation and heat dissipation. In the conventional semiconductor device 101P of FIG. 10, when the withstand voltage of the epoxy resin constituting the sealing resin 5P is 10 kV / mm and the thickness t is 0.1 mm, the withstand voltage of the sealing resin 5PP is 1 kV. As described above, the thermal conductivity of the epoxy resin is about 2 W / (m · K), while the thermal conductivity of the ceramic forming the insulating member 7 is about 20 W / (m · K). When the same thermal conductivity or heat dissipation is obtained, the insulating member 7 can be set to a thickness of about 1 mm. At this time, if a ceramic having a breakdown voltage of about 10 kV / mm, which is the same as that of the epoxy resin, is used as the insulating member 7, a breakdown voltage of about 10 kV can be secured. On the other hand, when the withstand voltage is the same, the insulating member 7 provides excellent heat dissipation. Furthermore, according to the insulating member 7, compared with the conventional semiconductor device 101P, insulation and heat dissipation can be improved at the same time.
[0023]
Next, since the entire surface 7S2 of the insulating member 7 is exposed and not covered with the sealing portion 5, the following effects are obtained. That is, according to the semiconductor device 101, unlike the conventional semiconductor device 101P (see FIG. 10), the sealing portion is formed on the surface 2S2 side of the element mounting portion 2D when the sealing portion 5 is formed by, for example, transfer molding. There is no need to fill 5 materials. Therefore, the formation failure of the sealing portion 5 does not occur on the surface 2S2 side of the element mounting portion 2D. In addition, since a decrease in insulation caused by such a formation defect of the sealing portion is not caused, high insulation can be obtained from this point.
[0024]
Furthermore, since it is not necessary to fill the surface 2S2 side of the element mounting portion 2D with the material of the sealing portion 5 as described above, the fluidity condition required for the material of the sealing portion 5 can be relaxed. Further, unlike the conventional semiconductor device 101P, the heat radiation from the surface 2S2 side of the element mounting portion 2D is performed via an insulating member. For this reason, the conditions of thermal conductivity (heat dissipation) required for the material of the sealing portion 5 can be relaxed. Therefore, since a material cheaper than the conventional sealing portion 5P (see FIG. 10) can be used, the cost and cost of the semiconductor device can be reduced.
[0025]
Further, in the semiconductor device 101, the entire surface 7S2 of the insulating member 7 is exposed, and the surface 7S2 and the outer surface 5S of the sealing portion 5 are flat. Therefore, when a heat radiating member such as a heat radiating fin (see heat radiating member 20 in FIG. 6 described later) is provided in contact with the insulating member 7, the surface 7S2 of the insulating member 7 and the heat radiating member can be reliably brought into contact with each other. In addition, heat can be conducted to the heat radiating member through the entire surface 7S2 of the insulating member 7. Therefore, stabilization and improvement of heat dissipation can be achieved. In addition, the degree of freedom of the shape of the heat radiating member is greater than when the surface 7S2 of the insulating member 7 forms a recess on the outer surface of the semiconductor device 101.
[0026]
The surface 7S2 of the insulating member 7 is fixed to the element mounting portion 2D with a brazing material 6. For this reason, since insulating member 7 and element mounting part 2D can be joined without a gap, stabilization and improvement of heat dissipation can be aimed at.
[0027]
Incidentally, a semiconductor device provided with a metal insulating substrate instead of the insulating member 7 is disclosed in Japanese Patent Laid-Open No. 7-45765. The metal insulating plate includes a metal plate serving as a heat sink, an insulating layer bonded onto the metal plate, and a conductor pattern formed on the insulating layer and in contact with a die pad or the like. Here, FIG. 11 shows an outline of the breakdown voltage-time characteristics of the insulating layer of the metal insulating substrate. As shown in FIG. 11, the insulating layer of the metal insulating substrate has a tendency that the withstand voltage decreases when a voltage is applied for a long time. On the other hand, since the insulating member 7 of the semiconductor device 101 is made of ceramic, such a tendency is not seen.
[0028]
In general, the insulating layer of the metal insulating substrate has a thickness of about 0.1 to 0.2 mm and a thermal conductivity of about 1 to 3 W / (m · K). In contrast, the insulating member 7 of the semiconductor device 101 has a thickness of about 0.5 mm and a thermal conductivity of about 20 W / (m · K). That is, according to the insulating member 7, the thickness is about 2.5 to 5 times that of the insulating layer, but there is an advantage that the heat dissipation is about 10 to 20 times larger.
[0029]
A semiconductor device provided with an insulating material is disclosed in Japanese Patent Laid-Open No. 6-209054. However, the insulating material disclosed in the publication is different from the insulating member 7 in that it is smaller than the mounting portion (corresponding to the element mounting portion 2D). In detail, the sealing material (corresponding to the sealing portion 5) of the semiconductor device disclosed in the above publication is formed in a frame shape on the lower surface of the mounting portion, and the mounting exposed from the frame-shaped opening An insulating material is disposed in contact with the lower surface of the part. For this reason, contrary to the insulating member 7, the peripheral edge of the insulating material is arranged on the inner side of the peripheral edge of the mounting portion.
[0030]
Further, the exposed surface of the insulating material (corresponding to the surface 7S2) is different from the semiconductor device 101 in that a concave portion is formed on the outer surface of the semiconductor device.
[0031]
<Modification 1 of Embodiment 1>
FIG. 3 is a longitudinal sectional view for explaining the first semiconductor device 101A according to the first modification. In addition, in the following description, the same code | symbol is attached | subjected to the thing equivalent to the above-mentioned component, and the description is used. As can be seen from a comparison between FIG. 3 and FIG. 1 described above, in the semiconductor device 101 A, a part of the side surface 7 S 3 of the insulating member 7 is exposed without being covered by the sealing portion 5.
[0032]
Note that the entire side surface 7S3 of the insulating member 7 may be exposed. At this time, like the second and third semiconductor devices 101B and 101C according to the first modification shown in the longitudinal sectional views of FIGS. 4 and 5, the size of the insulating member 7 is set to the semiconductor device 101 of FIG. It may be larger than. In the semiconductor device 101C, the peripheral portion of the surface 7S1 of the insulating member 7 is also exposed.
[0033]
According to the semiconductor devices 101A to 101C, since the side surface 7S3 of the insulating member 7 is further exposed, heat can be directly radiated from the side surface 7S3 without the sealing portion 5 interposed therebetween. Therefore, as compared with the semiconductor device 101 described above, further stabilization and improvement of heat dissipation can be achieved. Similarly to the semiconductor device 101, when the heat dissipation member is provided in contact with the insulating member 7, the degree of freedom of the shape of the heat dissipation member is large.
[0034]
<Modification 2 of Embodiment 1>
A thin metal layer (not shown) may be provided on the surface 7S1 of the insulating member. Such a metal layer is formed by applying a metal paste and firing it. At this time, the metal layer may be formed on the entire surface of the surface 7S1, or may be patterned in various shapes.
[0035]
According to the metal layer, the adhesiveness between the brazing material 6 and the insulating member 7 is further improved, so that the insulating member 7 and the element mounting portion 2D can be satisfactorily adhered. Thereby, since the contact thermal resistance between element mounting part 2D and the insulating member 7 reduces, the stabilization and improvement of the thermal radiation through the insulating member 7 can be aimed at.
[0036]
By the way, when the insulating member 7 is a ceramic, it may have a (local) waviness. In such a case, such undulation can be reduced or eliminated by appropriately patterning the metal layer. At this time, by providing a metal layer also on the surface 7S2 of the insulating member 7, and by controlling the thickness of each metal layer on each surface 7S1, 7S2, the waviness can be reduced and eliminated more effectively. Can do.
[0037]
<Embodiment 2>
FIG. 6 is a longitudinal sectional view for explaining the semiconductor device 102 according to the second embodiment. Note that FIG. 6 illustrates a case where the semiconductor device 102 is provided with a heat dissipation member 20, for example, a heat dissipation fin. As can be seen from a comparison between FIG. 6 and FIG. 1 described above, the semiconductor device 102 includes a convex or mountain-shaped insulating member 17 instead of the insulating member 7.
[0038]
Specifically, the insulating member 17 has surfaces 17S1, 17S2, and 17S3 corresponding to the surfaces 7S1, 7S2, and 7S3 (see FIG. 1) described above, and the centers of the surfaces 17S2 and 17S1 are convex with respect to the periphery. It has a shape. In particular, the insulating member 17 has a convex shape that protrudes toward the side opposite to the element mounting portion 2 D, in other words, toward the outside of the semiconductor device 102. The surface 17S2 of the insulating member 17 is in contact with the heat radiating member 20 via the heat radiating grease (thermal conductivity is about 1 W / (m · K)) 21.
[0039]
The convex shape of the insulating member 17 is formed as follows using the insulating member 7 described above, for example. That is, the convex shape of the insulating member 17 can be formed by performing heat treatment in a state where a load is applied to the center of the flat insulating member 7 and a weight is placed on the surface 17S1, for example. Further, such a convex shape can be formed by the metal layer described in the second modification of the first embodiment.
[0040]
Here, FIG. 7 shows a longitudinal sectional view for explaining another semiconductor device 102A according to the second embodiment. As can be seen from a comparison between FIG. 7 and FIG. 6, the semiconductor device 102 A includes an insulating member 17 A having a convex shape in a direction opposite to the insulating member 17 instead of the insulating member 17.
[0041]
The effects produced by the semiconductor device 101 described above can also be obtained by both the semiconductor devices 102 and 102A. In particular, according to the semiconductor device 102, the following effects can be obtained.
[0042]
When the semiconductor devices 102 and 102A and the heat radiating member 20 are brought into contact with each other, the insulating members 17 and 17A and / or the heat radiating member 20 are coated with the heat radiating grease 21 and then brought into contact with each other. At this time, in the semiconductor device 102A, the heat radiation grease 21 may remain between the insulating member 17A and the heat radiating member 20, and the insulating member 17A and the heat radiating member 20 may not contact each other. Further, when the heat radiation grease 21 is small, a gap, that is, an air layer may remain between the insulating member 17A and the heat radiation member 20.
[0043]
On the other hand, since the insulating member 17 of the semiconductor device 102 has a convex shape toward the outside, when the semiconductor device 102 and the heat dissipation member 20 are brought into contact with each other, the insulating member 17 laterally displaces excess heat dissipation grease 21. Push away. For this reason, irrespective of the application amount of the heat radiation grease 21, the convex top portion of the insulating member 17 can be brought into contact with the heat radiation member 20 reliably. In other words, the heat radiation grease 21 that is not unnecessarily thick is disposed. can do.
[0044]
At this time, in view of the point that the insulating member and the heat dissipating member are in contact with each other, the heat dissipating property is higher, and the heat dissipating grease 21 generally has the heat conductivity higher than that of air. In comparison with the semiconductor device 102, the thermal resistance between the semiconductor device 102 and the heat dissipation member 20 can be reduced. Therefore, stabilization and improvement of heat dissipation can be achieved.
[0045]
At this time, if at least the surface 17S2 of the insulating member 17 is convex toward the outside of the semiconductor device 102, such an effect can be obtained. Further, the insulating member (the surface corresponding to the surface 17S2 thereof) may have a shape corresponding to a part of the cylinder.
[0046]
<Embodiment 3>
8 and 9 are a longitudinal sectional view and a top view, respectively, for explaining the semiconductor device 103 according to the third embodiment. FIG. 8 is a longitudinal sectional view taken along line II in FIG. Moreover, in FIG. 9, the insulating member 7 and the sealing part 5 are shown with the thick line and the broken line, respectively.
[0047]
As shown in FIGS. 8 and 9, the semiconductor device 103 further includes a control circuit 8 for controlling the power semiconductor element 1 in addition to the configuration of the semiconductor device 101 of FIG. 1. The semiconductor device 103 corresponds to a so-called DIP type IPM (Intelligent Power Module).
[0048]
The control circuit 8 is formed of a so-called printed circuit board (PCB), and includes, for example, a glass epoxy resin substrate having predetermined wiring and components such as a semiconductor chip, a resistor, and a capacitor connected to the wiring. At this time, components such as resistors may be formed as printed components on the epoxy resin substrate. In addition, in order to avoid complication of drawing, detailed illustration of the control circuit 8 is abbreviate | omitted in FIG.8 and FIG.9.
[0049]
The control circuit 8 is fixed to the element mounting portion 2D2 for the control circuit 8 of the electrode frame 2 by a brazing material 9, and the control circuit 8 and the lead portion 2L are connected by a thin metal wire 4.
[0050]
Thus, since the semiconductor device 103 includes the semiconductor element 1 and the control circuit 8, higher functionality can be achieved as compared with the semiconductor device 101 and the like.
[0051]
<Summary>
Note that the above-described effects can be obtained also in a semiconductor device provided with a semiconductor element which is not for power but has a relatively large heat generation instead of the power semiconductor element 1.
[0052]
【The invention's effect】
(1) According to the invention of claim 1, the insulating member (formed in a predetermined shape in advance) is disposed on the other surface side of the element mounting portion, and the peripheral edge of the first surface of the insulating member Surrounds the periphery of the other surface of the element mounting portion. For this reason, the insulation of the other surface side of an element mounting part is securable by the said insulating member.
[0053]
Further, the entire second surface of the insulating member and at least a part of the third surface forming a side surface between the first surface and the second surface are exposed and not covered with the sealing portion. That is, unlike the conventional semiconductor device that does not have the insulating member and covers the other surface of the element mounting portion of the electrode frame, the sealing portion is formed by, for example, a transfer mold method. In this case, it is not necessary to fill the material of the sealing portion on the other surface side of the element mounting portion. Therefore, the formation defect of the sealing portion does not occur on the other surface side of the element mounting portion. In addition, since a decrease in insulation caused by such a formation defect of the sealing portion is not caused, high insulation can be obtained from this point.
[0054]
Furthermore, since there is no need to fill the other surface side of the element mounting portion with the material of the sealing portion as described above, the fluidity condition required for the material of the sealing portion can be relaxed. Further, unlike the conventional semiconductor device, heat radiation from the other surface side of the element mounting portion is performed via an insulating member. For this reason, the conditions of thermal conductivity (heat dissipation) required for the material of the sealing portion can be relaxed. Accordingly, since a material cheaper than the conventional sealing portion can be used, the cost and cost of the semiconductor device can be reduced.
[0055]
(2) According to the second aspect of the present invention, the third surface of the insulating member is formed so as to expose the entire surface and a part of the first surface . For this reason, when providing a heat radiating member in contact with the insulating member, the second surface of the insulating member and the heat radiating member can be reliably brought into contact with each other, and the second surface, the third surface, and the first surface of the insulating member. It is possible to conduct heat to the heat radiating member through a part of Therefore, stabilization and improvement of heat dissipation can be achieved. In addition, the degree of freedom of the shape of the heat radiating member is greater than when the second surface of the insulating member forms a recess on the outer surface of the semiconductor device.
[0056]
(3) According to the invention of claim 3, since the insulating member includes the metal layer on at least the second surface, local swell of the insulating member can be reduced or eliminated.
[0057]
(4) According to the invention of claim 1 , the center of the second surface of the insulating member is convex or concave with respect to the periphery. For this reason, when making it contact with the heat radiating member 20 which apply | coated the thermal radiation grease 21 to the insulating member, regardless of the application quantity of the thermal radiation grease 21, make the convex top part or concave shape of an insulating member contact the thermal radiation member 20 reliably. In other words, an appropriate amount of the heat dissipating grease 21 that is not unnecessarily thick can be disposed.
[0058]
(5) According to the invention of 請 Motomeko 4, the insulating member, the center of the second surface is a convex shape or a concave shape with respect to its periphery. For this reason, when making it contact with the heat radiating member 20 which apply | coated the thermal radiation grease 21 to the insulating member, regardless of the application quantity of the thermal radiation grease 21, make the convex top part or concave shape of an insulating member contact the thermal radiation member 20 reliably. In other words, an appropriate amount of the heat dissipating grease 21 that is not unnecessarily thick can be disposed.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view for explaining a semiconductor device according to a first embodiment;
FIG. 2 is a top view for explaining the semiconductor device according to the first embodiment;
3 is a longitudinal sectional view for explaining a first semiconductor device according to a first modification of the first embodiment. FIG.
4 is a longitudinal sectional view for explaining a second semiconductor device according to a first modification of the first embodiment. FIG.
5 is a longitudinal sectional view for explaining a third semiconductor device according to a first modification of the first embodiment. FIG.
6 is a longitudinal sectional view for explaining a semiconductor device according to a second embodiment; FIG.
7 is a longitudinal sectional view for explaining another semiconductor device according to the second embodiment; FIG.
FIG. 8 is a longitudinal sectional view for explaining a semiconductor device according to a third embodiment.
FIG. 9 is a top view for explaining the semiconductor device according to the third embodiment.
FIG. 10 is a longitudinal sectional view for explaining a conventional semiconductor device.
FIG. 11 is a schematic diagram for explaining the breakdown voltage-time characteristics of an insulating layer of a metal insulating substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Power semiconductor element (semiconductor element), 2 electrode frame, 2D element mounting part, 2DA, 7A periphery, 2L lead part, 2S1 surface (one surface), 2S2 surface (the other surface), 5 sealing part, 5S Outer surface, 6 brazing material (adhesive), 7, 17, 17A insulating member, 7S1, 17S1 surface (first surface), 7S2, 17S2 surface (second surface), 7S3, 17S3 surface (third surface), 101 -103,101A-101C, 102A Power semiconductor device (semiconductor device).

Claims

An electrode frame having an element mounting portion and a lead portion;
A semiconductor element mounted on one surface of the element mounting portion;
The peripheral surface has a first surface that surrounds the peripheral surface of the other surface of the element mounting portion and faces the other surface, and a second surface that faces the first surface, and is fixed to the element mounting portion. An insulating member;
The semiconductor element is in contact with the insulating member in a state in which the entire surface of the second surface of the insulating member and at least a part of the third surface forming a side surface between the first surface and the second surface are exposed. A sealing portion formed to cover ,
The insulating member is characterized in that the center of the second surface is convex or concave with respect to the periphery thereof.
Semiconductor device.

The semiconductor device according to claim 1,
The sealing portion is formed to further expose the entire third surface of the insulating member and a part of the first surface,
Semiconductor device.

The semiconductor device according to claim 1 or 2, wherein
The insulating member includes a metal layer on at least the second surface,
Semiconductor device.

An electrode frame having an element mounting portion and a lead portion;
  A semiconductor element mounted on one surface of the element mounting portion;
  The peripheral edge has a first surface that surrounds the peripheral edge of the other surface of the element mounting portion and faces the other surface, and a second surface that faces the first surface, and is fixed to the element mounting portion. An insulating member;
  A sealing portion formed in contact with the insulating member in a state where the entire surface of the second surface of the insulating member is exposed, and covering the semiconductor element;
  The insulating member is characterized in that the center of the second surface is convex or concave with respect to the periphery thereof.
Semiconductor device.