JP2006066559A - Semiconductor module and its manufacturing method - Google Patents

Semiconductor module and its manufacturing method Download PDF

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JP2006066559A
JP2006066559A JP2004246061A JP2004246061A JP2006066559A JP 2006066559 A JP2006066559 A JP 2006066559A JP 2004246061 A JP2004246061 A JP 2004246061A JP 2004246061 A JP2004246061 A JP 2004246061A JP 2006066559 A JP2006066559 A JP 2006066559A
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semiconductor module
lead frame
manufacturing
insulating layer
molding resin
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JP4492257B2 (en
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Kenji Okamoto
健次 岡本
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Fuji Electric FA Components and Systems Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module which raises heat radiation characteristics while suppressing cost increase, and to provide a manufacturing method. <P>SOLUTION: A semiconductor module 100 is constituted such that a power semiconductor 2 or a circuit element such as a drive IC3 may be connected to the circuit pattern of a lead frame 1 by bonding wires 4 and 5 while the whole is covered with molding resin 6, and an insulating layer 7 may be welded mutually and formed by using coating material which covers the surface of core members to the opposite side of this molding resin 6. The manufacturing method of the semiconductor module 100 is carried out such that the insulating layer 7 may be formed by using the plasma spraying deposition method for spraying and accumulating thermal spray material powder covered with coating agent on the surface of core material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体モジュールおよびその製造方法に関し、より詳細には、１または複数の回路素子を搭載し、樹脂によって封止され、形成される半導体モジュールおよびその製造方法に関する。   The present invention relates to a semiconductor module and a manufacturing method thereof, and more particularly to a semiconductor module mounted with one or a plurality of circuit elements and sealed and formed with a resin, and a manufacturing method thereof.

電源装置に使用される半導体モジュールは、家庭用エアコン、冷蔵庫などの民生機器から、インバータ、サーボコントローラなどの産業機器まで、広範囲にわたって適用されている。半導体モジュールは、消費電力の点から、金属ベース基板やセラミックス基板などの配線板に搭載される。この配線板にパワー半導体などの１または複数の回路素子を搭載し、プラスチックケース枠を接着し、シリコーンゲルやエポキシ樹脂などで封止することによって半導体モジュールを製造する。   Semiconductor modules used for power supply devices are applied in a wide range from consumer equipment such as home air conditioners and refrigerators to industrial equipment such as inverters and servo controllers. The semiconductor module is mounted on a wiring board such as a metal base substrate or a ceramic substrate from the viewpoint of power consumption. A semiconductor module is manufactured by mounting one or a plurality of circuit elements such as a power semiconductor on the wiring board, bonding a plastic case frame, and sealing with a silicone gel or an epoxy resin.

このような半導体モジュールの製造では、製造コストを低減するために、トランスファー成形方式により製造されるフルモールド半導体モジュールが用いられている（例えば、特許文献１参照）。   In the manufacture of such a semiconductor module, a full mold semiconductor module manufactured by a transfer molding method is used in order to reduce the manufacturing cost (for example, see Patent Document 1).

図４に、このような従来のフルモールド半導体モジュールの第１例を示す。リードフレーム２１の上には、パワー半導体２２、駆動ＩＣ２３が実装され、ボンディングワイヤ２４，２５により相互に接続されている。これらの部品を金型にセットして、成形樹脂２６を流し込むことにより、フルモールド半導体モジュールを構成する。   FIG. 4 shows a first example of such a conventional full mold semiconductor module. A power semiconductor 22 and a driving IC 23 are mounted on the lead frame 21 and are connected to each other by bonding wires 24 and 25. These parts are set in a mold, and a molding resin 26 is poured into the full mold semiconductor module.

図５に従来のフルモールド半導体モジュールの第２例を示す。図４に示したフルモールド半導体モジュールの構成に加え、さらにその下部にヒートシンク２７を設けたものである。以下、図４，図５で示すように、リードフレームおよび回路素子が全て成型樹脂で覆われるようなフルモールド半導体モジュールを説明の便宜上のため、特に通常フルモールド半導体モジュールという。   FIG. 5 shows a second example of a conventional full mold semiconductor module. In addition to the configuration of the full mold semiconductor module shown in FIG. 4, a heat sink 27 is further provided below the full mold semiconductor module. Hereinafter, as shown in FIGS. 4 and 5, a full mold semiconductor module in which the lead frame and the circuit elements are all covered with molding resin is referred to as a normal full mold semiconductor module for convenience of explanation.

さらに、図６に従来のフルモールド半導体モジュールの第３例を示す。リードフレーム２１に接触する金属ベース基板２８が外部に露出するようなフルモールド半導体モジュールであり、導電層である銅箔２８ａ，絶縁層２８ｂおよびヒートシンク２８ｃを積層した金属ベース基板２８を設け、金属ベース基板２８に絶縁と熱放出の２つの機能を持たせるようにしたものである。このフルモールド半導体モジュールでは、リードフレーム２１、ヒートシンク２８ｃとを固定的に連結するとともに、絶縁層２８ｂにより電気的絶縁を確保している。   FIG. 6 shows a third example of a conventional full mold semiconductor module. A full mold semiconductor module in which a metal base substrate 28 that contacts the lead frame 21 is exposed to the outside, and a metal base substrate 28 in which a copper foil 28a, an insulating layer 28b, and a heat sink 28c as conductive layers are laminated is provided. The substrate 28 has two functions of insulation and heat release. In this full mold semiconductor module, the lead frame 21 and the heat sink 28c are fixedly connected, and electrical insulation is ensured by the insulating layer 28b.

また、フルモールド半導体モジュールの他の従来技術として、ヒートシンクの露出面にアルミナ等を溶射した電気絶縁層が外部に露出するように構成され、電気絶縁部材，ヒートシンクおよび電気絶縁層を介してプリント回路基板へ効率的に熱放射するような樹脂封止型半導体装置について開示されている（例えば、特許文献２参照）。以下、図６および特許文献２で示すように、リードフレームおよび回路素子が直接接触するヒートシンクを外部に露出するようなフルモールド半導体モジュールを、説明の便宜上のため、特に一部露出型フルモールド半導体モジュールという。   In addition, as another conventional technology of a full mold semiconductor module, an electrically insulating layer sprayed with alumina or the like is exposed to the outside on an exposed surface of a heat sink, and a printed circuit is formed through the electrically insulating member, the heat sink, and the electrically insulating layer. A resin-sealed semiconductor device that efficiently radiates heat to a substrate is disclosed (for example, see Patent Document 2). Hereinafter, as shown in FIG. 6 and Patent Document 2, a full mold semiconductor module in which a heat sink that directly contacts a lead frame and a circuit element is exposed to the outside is used for convenience of explanation. This is called a module.

なお、特許文献２では電機絶縁層としてアルミナ等を溶射する点が記載されているが、一般的な層形成方法として、例えば特許文献３（発明の名称：複合構造物の作成方法および作成装置），特許文献４（発明の名称：超微粒子材料吹き付け成膜方法）などに記載された先行技術が知られている。   In addition, in patent document 2, although the point which sprays an alumina etc. as an electrical-insulation layer is described, as a general layer formation method, patent document 3 (title of invention: creation method and creation apparatus of composite structure), for example The prior art described in Patent Document 4 (Title of Invention: Ultrafine particle material spraying film forming method) is known.

特開平９−１３９４６１号公報（段落番号００３８、図１）JP-A-9-139461 (paragraph number 0038, FIG. 1) 特開平１１−８７５７３号公報（段落番号００１０〜００１１、図１）Japanese Patent Laid-Open No. 11-87573 (paragraph numbers 0010 to 0011, FIG. 1) 特開２００１−１８１８５９号公報（段落番号００５３〜００７１、図１〜図１０）JP 2001-181859 A (paragraph numbers 0053 to 0071, FIGS. 1 to 10) 特開２００２−２０８７８号公報（段落番号００１３〜００３１、図１〜図１０）JP 2002-20878 (paragraph numbers 0013 to 0031, FIGS. 1 to 10)

従来技術の通常フルモールド半導体モジュール（図４，図５の半導体モジュール，特許文献１の図１の半導体パワーモジュール）では、その冷却性能が、金属ベース基板を用いた一部露出型フルモールド半導体モジュール（図６の半導体モジュール，特許文献２の図１の樹脂封止型半導体装置）の冷却性能よりも劣っていた。   The conventional full mold semiconductor module of the prior art (semiconductor module of FIGS. 4 and 5, the semiconductor power module of FIG. 1 of Patent Document 1) has a cooling performance that is a partially exposed type full mold semiconductor module using a metal base substrate. It was inferior to the cooling performance of the semiconductor module in FIG. 6 and the resin-encapsulated semiconductor device in FIG.

この原因としては、一部露出型半導体モジュールは、絶縁層（図６の絶縁層２８ａまたは特許文献２の図１の電気絶縁部材６等）の厚みを１００〜１５０μｍと薄くでき、パワー半導体の下部の熱抵抗を小さくすることができる一方で、通常フルモールド半導体モジュール（図４，図５の半導体モジュール，特許文献１の図１の半導体パワーモジュール）では、成形樹脂の充填性を確保するため成形樹脂の厚さを３００μｍ以上にする必要があり、パワー半導体の下部の熱抵抗が大きくなる、ということが理由として挙げられる。   As a cause of this, in the partially exposed semiconductor module, the thickness of the insulating layer (the insulating layer 28a in FIG. 6 or the electrical insulating member 6 in FIG. 1 of Patent Document 2) can be reduced to 100 to 150 μm, and the lower part of the power semiconductor In the normal full mold semiconductor module (the semiconductor module shown in FIGS. 4 and 5, the semiconductor power module shown in FIG. 1 of Patent Document 1), the molding resin is molded to ensure the filling property. The reason is that the thickness of the resin must be 300 μm or more, and the thermal resistance of the lower portion of the power semiconductor is increased.

例えば、図４に示したフルモールド半導体モジュールにおいて、成形樹脂２６の下側の厚さ（リードフレーム２１から下側表面までの厚さ）を２００μｍ以下とすると、金型内で成形樹脂２６の未充填部が発生し、絶縁不良が生じる。また、このような未充填部の発生を防止するため、成形時の樹脂注入圧力を高くして充填性を向上させることが可能であるが、ボンディングワイヤ２４，２５の変形、断線の原因にもなるため採用できないものであり、成型樹脂２６の下側の厚さを薄くできなかった。   For example, in the full mold semiconductor module shown in FIG. 4, if the thickness of the lower side of the molding resin 26 (thickness from the lead frame 21 to the lower surface) is 200 μm or less, the molding resin 26 is not formed in the mold. Filled parts are generated, resulting in poor insulation. Moreover, in order to prevent the occurrence of such unfilled portions, it is possible to improve the filling property by increasing the resin injection pressure at the time of molding, but this may cause deformation and disconnection of the bonding wires 24 and 25. Therefore, the thickness of the lower side of the molding resin 26 could not be reduced.

図５に示したフルモールド半導体モジュールにおいても同様であり、例えば、リードフレーム２１とヒートシンク２７との間隙の成形樹脂２６の厚さを２００μｍ以下とすると、成形樹脂２６の未充填部が残留し、絶縁不良が生じる。成形時の樹脂注入圧力を高くして充填性を向上させるとボンディングワイヤ２４，２５の変形、断線の原因にもなり、成型樹脂２６の間隙を薄くできなかった。このような問題は特許文献１に記載された従来技術でも起こりうる問題である。   The same applies to the full mold semiconductor module shown in FIG. 5. For example, when the thickness of the molding resin 26 in the gap between the lead frame 21 and the heat sink 27 is 200 μm or less, an unfilled portion of the molding resin 26 remains. Insulation failure occurs. If the resin injection pressure at the time of molding is increased to improve the filling property, the bonding wires 24 and 25 may be deformed or disconnected, and the gap between the molding resins 26 cannot be reduced. Such a problem is a problem that can occur even in the prior art described in Patent Document 1.

このように従来の通常フルモールド半導体モジュールは熱抵抗が高く冷却特性が劣るものであり、現状では実用上の冷却特性を考慮して、フルモールド半導体モジュールの消費電力の適用範囲は２００Ｖ５０Ａ程度までしか採用できなかった。電流容量が５０Ａを超えるパワー半導体を使用するとロスが大きくなって熱発生量が大きくなり、通常フルモールド半導体モジュールでは冷却性能が不十分であった。このように電流容量が５０Ａを超えるパワー半導体を搭載した通常フルモールド半導体モジュールの実用化が困難であるという問題があった。   As described above, the conventional normal full mold semiconductor module has high thermal resistance and inferior cooling characteristics. Currently, considering the practical cooling characteristics, the application range of power consumption of the full mold semiconductor module is only about 200V50A. It was not possible to adopt. When a power semiconductor having a current capacity exceeding 50 A is used, loss increases and the amount of heat generation increases, and usually a full mold semiconductor module has insufficient cooling performance. As described above, there is a problem that it is difficult to put a normal full mold semiconductor module on which a power semiconductor having a current capacity exceeding 50 A is mounted.

また、一部露出型フルモールド半導体モジュール（図６，特許文献２）において、例えば、図６で示すように、予め絶縁層２８ｂとヒートシンク２８ｃとが張り合わされた金属ベース基板２８を用いることにより下側に成形樹脂がない構成とし、成形樹脂の充填性を考慮して厚みを確保する必要をなくすとともにパワー半導体下部の熱抵抗を小さくしている。
しかしながら、金属ベース基板２８を別途製造しておく必要があるため、材料コスト・製造コストが増大するという問題点があった。このような問題は特許文献２に記載された従来技術でも起こりうる問題である。 Further, in a partially exposed type full mold semiconductor module (FIG. 6, Patent Document 2), for example, as shown in FIG. 6, a metal base substrate 28 in which an insulating layer 28b and a heat sink 28c are bonded in advance is used. The structure has no molding resin on the side, and it is not necessary to secure the thickness in consideration of the filling property of the molding resin, and the thermal resistance at the lower part of the power semiconductor is reduced.
However, since it is necessary to manufacture the metal base substrate 28 separately, there is a problem that the material cost and the manufacturing cost increase. Such a problem is a problem that may occur even in the prior art described in Patent Document 2.

また、図６で示す一部露出型フルモールド半導体モジュールの金属ベース基板２８の絶縁層２８ｂには、エポキシ樹脂に無機フィラー（酸化珪素（ＳｉＯ２）、酸化アルミニウム（Ａｌ２Ｏ３）、窒化珪素（Ｓｉ３Ｎ４）、窒化ホウ素（ＢＮ）、窒化アルミニウム（ＡｌＮ）からなるフィラー群から１種類以上を選択したもの）を充填し熱伝導率を向上させているが、現状の熱伝導率は３〜７Ｗ／ｍ・Ｋが限度であり、冷却性能に限界があった。 In addition, the insulating layer 28b of the metal base substrate 28 of the partially exposed full mold semiconductor module shown in FIG. 6 includes an epoxy resin, an inorganic filler (silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride. (Si 3 N 4 ), boron nitride (BN), and one selected from a group of fillers made of aluminum nitride (AlN) are filled to improve the thermal conductivity, but the current thermal conductivity is The limit was 3 to 7 W / m · K, and the cooling performance was limited.

なお、熱伝導率を増大させて熱抵抗を小さくするため、配線板に酸化アルミニウム、窒化珪素、窒化アルミニウムなどを焼結体であるセラミックス性の配線板を用いることもできる。この場合、冷却性能は向上するが製造コストが金属ベース基板より増大するという問題点があった。   In order to increase the thermal conductivity and reduce the thermal resistance, a ceramic wiring board that is a sintered body of aluminum oxide, silicon nitride, aluminum nitride, or the like can be used for the wiring board. In this case, although the cooling performance is improved, there is a problem that the manufacturing cost is increased as compared with the metal base substrate.

まとめると、通常フルモールド半導体モジュールでは、充填性の維持のため等の理由により熱抵抗が小さくできないという問題があり、また、一部露出型フルモールド半導体モジュールでは、熱抵抗を小さくできるが材料コスト・製造コストの増加が防げないという問題があった。   In summary, there is a problem that the normal full mold semiconductor module cannot reduce the thermal resistance for reasons such as maintaining the filling property, and the partially exposed full mold semiconductor module can reduce the thermal resistance, but the material cost is low. -There was a problem that the increase in manufacturing cost could not be prevented.

本発明は、このような問題に鑑みてなされたもので、その目的とするところは、コスト上昇を抑えつつ放熱特性を向上させた半導体モジュールおよびその製造方法を提供することにある。   The present invention has been made in view of such problems, and an object thereof is to provide a semiconductor module having improved heat dissipation characteristics while suppressing an increase in cost, and a method for manufacturing the same.

上記課題を解決するため、本発明の請求項１に係る発明の半導体モジュールは、
１または複数の回路素子を搭載し、樹脂によって封止され、形成された半導体モジュールにおいて、
回路素子を搭載するための回路パターンが形成されたリードフレームと、
回路素子およびリードフレームを覆うように一方の面に設けられる成形樹脂と、
成形樹脂およびリードフレームを覆うように他方の面に設けられる絶縁層と、
を備え、
前記絶縁層は、コア材の表面を覆う被服材が相互に溶着して形成された層であることを特徴とする。
を備えることを特徴とする。 In order to solve the above-mentioned problem, a semiconductor module according to claim 1 of the present invention provides:
In a semiconductor module in which one or more circuit elements are mounted and sealed with resin,
A lead frame on which a circuit pattern for mounting circuit elements is formed;
Molding resin provided on one surface so as to cover the circuit element and the lead frame;
An insulating layer provided on the other surface so as to cover the molding resin and the lead frame;
With
The insulating layer is a layer formed by welding clothes covering the surface of the core material to each other.
It is characterized by providing.

この構成によれば、直接絶縁層が露出しているため、回路素子下部の熱抵抗を小さくして放熱性を向上させることができる。   According to this configuration, since the insulating layer is directly exposed, the heat resistance at the lower part of the circuit element can be reduced to improve the heat dissipation.

また、本発明の請求項２に係る発明の半導体モジュールは、
請求項１に記載の半導体モジュールにおいて、
被服材が酸化珪素であり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする。 The semiconductor module of the invention according to claim 2 of the present invention is
The semiconductor module according to claim 1,
The clothing material is silicon oxide, and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride.

また、本発明の請求項３に係る発明の半導体モジュールは、
請求項１に記載の半導体モジュールにおいて、
被服材が酸化アルミニウムであり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする。 A semiconductor module of an invention according to claim 3 of the present invention is
The semiconductor module according to claim 1,
The clothing material is aluminum oxide, and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride.

また、本発明の請求項４に係る発明の半導体モジュールの製造方法は、
１または複数の回路素子を搭載し、樹脂によって封止され、形成された半導体モジュールの製造方法において、
予め成形加工されたリードフレームに回路素子を接合する第１工程と、
回路素子とリードフレームとをボンディングワイヤにより接続する第２工程と、
回路素子およびリードフレームを覆う成形樹脂を一方の面に形成する第３工程と、
コア材の表面に被服材が皮膜されてなる溶射材料粉末をプラズマ溶射法により他方の面に溶射して、成形樹脂およびリードフレームを覆う絶縁層を形成する第４工程と、
を有することを特徴とする。 Moreover, the manufacturing method of the semiconductor module of the invention which concerns on Claim 4 of this invention,
In a method for manufacturing a semiconductor module in which one or more circuit elements are mounted and sealed with a resin,
A first step of joining a circuit element to a pre-molded lead frame;
A second step of connecting the circuit element and the lead frame by a bonding wire;
A third step of forming a molding resin covering the circuit element and the lead frame on one surface;
A fourth step of forming an insulating layer covering the molding resin and the lead frame by spraying a thermal spray material powder formed by coating a coating material on the surface of the core material on the other surface by a plasma spraying method;
It is characterized by having.

また、本発明の請求項５に係る発明の半導体モジュールの製造方法は、
請求項４に記載の半導体モジュールの製造方法において、
被服材が酸化珪素であり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする。 Moreover, the manufacturing method of the semiconductor module of the invention which concerns on Claim 5 of this invention,
In the manufacturing method of the semiconductor module according to claim 4,
The clothing material is silicon oxide, and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride.

また、本発明の請求項６に係る発明の半導体モジュールの製造方法は、
請求項４に記載の半導体モジュールの製造方法において、
被服材が酸化アルミニウムであり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする。 Moreover, the manufacturing method of the semiconductor module of the invention which concerns on Claim 6 of this invention,
In the manufacturing method of the semiconductor module according to claim 4,
The clothing material is aluminum oxide, and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride.

このような本発明によれば、コスト上昇を抑えつつ放熱特性を向上させた半導体モジュールおよびその製造方法を提供することができる。   According to the present invention, it is possible to provide a semiconductor module having improved heat dissipation characteristics while suppressing an increase in cost and a method for manufacturing the same.

続いて、本発明を実施するための最良の形態に係る半導体モジュールおよびその製造方法について、図を参照しつつ以下に説明する。図１は本形態の半導体モジュールの断面構成図、図２は絶縁層の説明図である。
本形態の半導体モジュール１００は、図１で示すように、リードフレーム１、パワー半導体２、駆動ＩＣ３、ボンディングワイヤ４，５、成形樹脂６、絶縁層７を備える。
このリードフレーム１の上には、回路素子の一具体例であるパワー半導体２、回路素子の一具体例である駆動ＩＣ３が実装され、ボンディングワイヤ４，５により相互に接続されている。これらリードフレーム１、パワー半導体２、駆動ＩＣ３、ボンディングワイヤ４，５を覆うように一方の側（図１では上側）で成形樹脂６が形成され、さらに他方の側（図１では下側）に成形樹脂６およびリードフレーム１を覆うように絶縁層７が形成される。 Next, a semiconductor module and a manufacturing method thereof according to the best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional configuration diagram of a semiconductor module of this embodiment, and FIG. 2 is an explanatory diagram of an insulating layer.
As shown in FIG. 1, the semiconductor module 100 of this embodiment includes a lead frame 1, a power semiconductor 2, a driving IC 3, bonding wires 4 and 5, a molding resin 6, and an insulating layer 7.
On the lead frame 1, a power semiconductor 2, which is a specific example of a circuit element, and a drive IC 3, which is a specific example of a circuit element, are mounted and connected to each other by bonding wires 4 and 5. A molding resin 6 is formed on one side (upper side in FIG. 1) so as to cover the lead frame 1, power semiconductor 2, driving IC 3, and bonding wires 4 and 5, and further on the other side (lower side in FIG. 1). An insulating layer 7 is formed so as to cover the molding resin 6 and the lead frame 1.

この絶縁層７は、図２（ａ）で示すように、被服材１０の中に粒体状のコア材１１が多数含まれるような層である。図２（ｂ）で示すように核となるコア材１１の表面を、皮膜となる被服材１０が覆っているような粒体が、多数集まってなる溶射材料粉末を加熱し、被服材同士を溶着させて形成した層である。被服材が溶着により密接し空隙が少ない層となっている。   As shown in FIG. 2A, the insulating layer 7 is a layer in which a large number of granular core materials 11 are included in the clothing material 10. As shown in FIG. 2 (b), the surface of the core material 11 serving as the core is heated by the thermal spray material powder in which a large number of granules covering the clothing material 10 serving as a coating gather, It is a layer formed by welding. The clothing material is in close contact with the weld and is a layer with few voids.

被服材１０は酸化珪素（ＳｉＯ２）、または、酸化アルミニウム（Ａｌ２Ｏ３）であり、厚みは１０ｎｍ〜１μｍである。
コア材１１としては窒化珪素（Ｓｉ３Ｎ４）、窒化ホウ素（ＢＮ）、窒化アルミニウム（ＡｌＮ）の少なくとも一つであり、粒径は１〜５０μｍである。
従って、
（１）被服材１０を酸化珪素とし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の何れか一つを選択する組み合わせ、
（２）被服材１０を酸化珪素とし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の中から二つ選択する組み合わせ、
（３）被服材１０を酸化珪素とし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の全部を選択する組み合わせ、
を採用できる。
また、
（４）被服材１０を酸化アルミニウムとし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の何れか一つを選択する組み合わせ、
（５）被服材１０を酸化アルミニウムとし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の中から二つ選択する組み合わせ、
（６）被服材１０を酸化アルミニウムとし、また、コア材１１を窒化珪素、窒化アルミニウム、窒化ホウ素の全部を選択する組み合わせ、
を採用できる。 The clothing material 10 is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ) and has a thickness of 10 nm to 1 μm.
The core material 11 is at least one of silicon nitride (Si 3 N 4 ), boron nitride (BN), and aluminum nitride (AlN), and the particle size is 1 to 50 μm.
Therefore,
(1) The clothing material 10 is silicon oxide, and the core material 11 is a combination of selecting one of silicon nitride, aluminum nitride, and boron nitride,
(2) A combination in which the clothing material 10 is silicon oxide and the core material 11 is selected from silicon nitride, aluminum nitride, and boron nitride,
(3) A combination in which the clothing material 10 is silicon oxide, and the core material 11 is a combination of selecting all of silicon nitride, aluminum nitride, and boron nitride,
Can be adopted.
Also,
(4) A combination in which the clothing material 10 is aluminum oxide, and the core material 11 is selected from any one of silicon nitride, aluminum nitride, and boron nitride,
(5) A combination in which the clothing material 10 is aluminum oxide and the core material 11 is selected from silicon nitride, aluminum nitride, and boron nitride,
(6) A combination in which the clothing material 10 is aluminum oxide and the core material 11 is selected from silicon nitride, aluminum nitride, and boron nitride,
Can be adopted.

このような半導体モジュール１００を回路基板に実装すると、例えば図示しない回路基板にこの絶縁層７が接触して、回路基板を通じて放熱されることとなるが、従来よりも格段に熱抵抗が小さい（熱伝導率が大きい）絶縁層７を通じて効率的に放熱されることとなり、放熱特性を向上させることができる。   When such a semiconductor module 100 is mounted on a circuit board, for example, the insulating layer 7 comes into contact with a circuit board (not shown) and heat is radiated through the circuit board. However, the thermal resistance is much smaller than that in the past (heat The heat is efficiently radiated through the insulating layer 7 having a high conductivity, and the heat dissipation characteristics can be improved.

この絶縁層７の厚さａは５０〜５００μｍの範囲内に収めることが好ましい。被服材を酸化珪素（ＳｉＯ２）または酸化アルミニウム（Ａｌ２Ｏ３）とし、コア材を窒化珪素（Ｓｉ３Ｎ４）、窒化ホウ素（ＢＮ）、窒化アルミニウム（ＡｌＮ）の中の少なくとも一つとした絶縁層７を厚み５００μｍで形成した半導体モジュールは、交流破壊電圧で１０ｋＶ以上有しており、耐電圧定格が１２００Ｖのパワー半導体に使用できることが実験により確認されている。 The thickness a of the insulating layer 7 is preferably within the range of 50 to 500 μm. The clothing material is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ), and the core material is at least one of silicon nitride (Si 3 N 4 ), boron nitride (BN), and aluminum nitride (AlN). The semiconductor module in which the insulating layer 7 is formed with a thickness of 500 μm has an AC breakdown voltage of 10 kV or more, and it has been confirmed by experiments that it can be used for a power semiconductor having a withstand voltage rating of 1200 V.

なお、この厚さａが大きくなるにつれて外界からの衝撃に対する耐衝撃性を向上させることができるが熱抵抗が増大するというトレードオフの関係にあり、放熱特性を向上させたい場合には例えば１５０μｍというような値が選択される。このため、絶縁層の厚さａは５０〜５００μｍ中から使用目的に応じて設計選択される。   Note that, as the thickness a is increased, the impact resistance against an impact from the outside world can be improved, but there is a trade-off relationship that the thermal resistance is increased. A value like this is selected. For this reason, the thickness a of the insulating layer is selected from 50 to 500 μm according to the purpose of use.

続いて、半導体モジュール１００の製造方法について図を参照しつつ説明する。図３は、本実施形態の半導体モジュール１００の製造方法の説明図である。
（１）０．３〜１．０ｍｍ程度の銅板を、プレス加工により打ち抜いて、所定の回路パターンが形成されたリードフレーム１を製作する（図３（ａ））。 Next, a method for manufacturing the semiconductor module 100 will be described with reference to the drawings. FIG. 3 is an explanatory diagram of a method for manufacturing the semiconductor module 100 of the present embodiment.
(1) A copper plate having a thickness of about 0.3 to 1.0 mm is punched out by press working to produce a lead frame 1 on which a predetermined circuit pattern is formed (FIG. 3A).

（２）リードフレーム１にパワー半導体２および駆動ＩＣ３をはんだ付けにより接合する（図３（ｂ））。
はんだ付けはペレット状のはんだを利用し、水素還元が可能な炉において行う。水素還元が可能な炉を使用する理由は、リードフレーム１の表面の酸化膜を水素還元により除去して活性化させることにより、はんだとの濡れ性を向上させるためである。はんだ材料には、例えば、Ｓｎ−Ｐｂ−Ａｇからなる高温はんだ、Ｓｎ−Ａｇ−Ｃｕ系からなる鉛フリーはんだを用いる。これらはんだは高温の成形樹脂に接触しても溶けないはんだであり、はんだ付けの温度は、はんだの融点に応じて設定される。 (2) The power semiconductor 2 and the driving IC 3 are joined to the lead frame 1 by soldering (FIG. 3B).
Soldering is performed in a furnace capable of hydrogen reduction using pelletized solder. The reason for using a furnace capable of hydrogen reduction is to improve the wettability with the solder by removing and activating the oxide film on the surface of the lead frame 1 by hydrogen reduction. As the solder material, for example, high-temperature solder made of Sn—Pb—Ag or lead-free solder made of Sn—Ag—Cu is used. These solders are solders that do not melt even when they come into contact with a high-temperature molding resin, and the soldering temperature is set according to the melting point of the solder.

なお、パワー半導体２とリードフレーム１のはんだ層にボイド（空孔）が残留すると、熱抵抗が高くなり、パワー半導体２から生じる熱を効率よく放熱することができない。そこで、ボイドが発生しないように、はんだが溶融している状態で、１０Ｔｏｒｒ以下の真空引きを行う。真空環境下、泡が大きくなってはじけ、ボイドは消滅する。   If voids (holes) remain in the solder layer of the power semiconductor 2 and the lead frame 1, the thermal resistance increases, and the heat generated from the power semiconductor 2 cannot be efficiently radiated. Therefore, vacuuming of 10 Torr or less is performed in a state where the solder is melted so that no void is generated. In a vacuum environment, bubbles become larger and repel, and voids disappear.

（３）ボンディングワイヤ４，５による接続を行う（図３（ｃ））。リードフレーム１の回路とパワー半導体２とを接続するボンディングワイヤ４は、線径が１２５〜５００μｍのＡｌワイヤを使用して超音波接合する。リードフレーム１の回路と駆動ＩＣ３とを接続するボンディングワイヤ５は、線径が１０μｍ程度のＡｕワイヤを使用して超音波接合する。 (3) Connection by bonding wires 4 and 5 is performed (FIG. 3C). The bonding wire 4 connecting the circuit of the lead frame 1 and the power semiconductor 2 is ultrasonically bonded using an Al wire having a wire diameter of 125 to 500 μm. The bonding wire 5 that connects the circuit of the lead frame 1 and the drive IC 3 is ultrasonically bonded using an Au wire having a wire diameter of about 10 μm.

（４）図３（ｃ）に示した部品を、トランスファー成形機に取り付けられた金型にセットする（図示せず）。金型は１７０〜１８０℃程度に保温されており、予熱後にタブレット状のエポキシ樹脂をプランジャーにて金型内に流し込む。
このエポキシ樹脂はマトリクス（主材）であり、フィラー（添加物）として酸化珪素（ＳｉＯ２）、酸化アルミニウム（Ａｌ２Ｏ３）、窒化珪素（Ｓｉ３Ｎ４）、窒化アルミニウム（ＡｌＮ）、窒化ホウ素（ＢＮ）の中の１または２以上を選択的に組み合わせたセラミック粉末を添加したものであり、熱伝導率は２〜５Ｗ／ｍ・Ｋとなる。 (4) The components shown in FIG. 3C are set in a mold attached to a transfer molding machine (not shown). The mold is kept at a temperature of about 170 to 180 ° C. After preheating, a tablet-like epoxy resin is poured into the mold with a plunger.
This epoxy resin is a matrix (main material), and silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), nitride as fillers (additives) A ceramic powder in which one or more of boron (BN) is selectively combined is added, and the thermal conductivity is 2 to 5 W / m · K.

（５）このエポキシ樹脂の注入を行うと数十秒で硬化するので、直ぐに金型から取り出し、恒温槽で後硬化を行って封止を完了し、成形樹脂６を形成する（図３（ｄ））。
なお、このようにして形成した絶縁層形成前の半導体モジュールの底面は、リードフレーム１および成形樹脂６が下側に露出するが、同一平面となるように形成されている（理由は後述する）。従来技術ではリードフレーム１の下側にも成型樹脂を充填する必要があり、未充填部が発生するおそれがあったが、本実施形態ではリードフレーム１の下側に成形樹脂を充填させないため従来技術のような未充填部が発生する事態をなくし、また、充填性を考慮する必要もなくしている。 (5) When this epoxy resin is injected, it cures in several tens of seconds, so it is immediately removed from the mold and post-cured in a thermostatic bath to complete sealing, thereby forming a molding resin 6 (FIG. 3 (d) )).
The bottom surface of the semiconductor module formed in this way before forming the insulating layer is formed so as to be on the same plane, although the lead frame 1 and the molding resin 6 are exposed to the lower side (the reason will be described later). . In the prior art, it is necessary to fill the lower side of the lead frame 1 with the molding resin, and there is a possibility that an unfilled portion may occur. However, in the present embodiment, the molding resin is not filled in the lower side of the lead frame 1. This eliminates the occurrence of unfilled portions as in the technology, and eliminates the need to consider the filling properties.

（６）恒温槽から取り出した絶縁層形成前の半導体モジュールの底面へマスク８をあてて、コア材の表面に被服材が皮膜された溶射材料粉末をプラズマ溶射法により他方の面に溶射して絶縁層７を形成する（図３（ｅ））。 (6) The mask 8 is applied to the bottom surface of the semiconductor module before forming the insulating layer taken out from the thermostatic bath, and the sprayed material powder having the coating material coated on the surface of the core material is sprayed on the other surface by the plasma spraying method. An insulating layer 7 is formed (FIG. 3E).

ここでプラズマ溶射法とは、雰囲気を大気圧下、または、減圧下とし、加熱により溶射材料粉末を溶融もしくは軟化させて加速し、絶縁層形成前の半導体モジュールの底面に衝突させて、微粒子を凝固・堆積させて積層し、絶縁層７を形成するというものである。   Here, the plasma spraying method means that the atmosphere is under atmospheric pressure or reduced pressure, and the thermal spray material powder is accelerated by melting or softening by heating and colliding with the bottom surface of the semiconductor module before forming the insulating layer. The insulating layer 7 is formed by solidification and deposition.

この溶射材料粉末は、先に説明したが、図２（ｂ）に示すように、溶射材料粉末の一粒をみると、コア材１１による核（コアフィラー）の表面を、被服材１０による皮膜が覆っているような粒体が集まったものであり、コア材１１の粒径は１〜５０μｍの長さのものを用いる。このコア材１１の表面に、図２（ｂ）で示すように、被服材１０を１０ｎｍ〜１μｍの厚みで皮膜して皮膜状に形成する。
また、被服材１０は酸化珪素（ＳｉＯ２）、または、酸化アルミニウム（Ａｌ２Ｏ３）であり、コア材１１は窒化珪素（Ｓｉ３Ｎ４）、窒化ホウ素（ＢＮ）、窒化アルミニウム（ＡｌＮ）の少なくとも一つである。溶射材料粉末はこのような粒体の集まりである。 The thermal spray material powder has been described above. As shown in FIG. 2B, when one particle of the thermal spray material powder is seen, the surface of the core (core filler) by the core material 11 is coated with the coating material 10. The core material 11 has a particle diameter of 1 to 50 μm. As shown in FIG. 2B, the clothing material 10 is coated on the surface of the core material 11 with a thickness of 10 nm to 1 μm to form a film.
The clothing material 10 is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ), and the core material 11 is silicon nitride (Si 3 N 4 ), boron nitride (BN), or aluminum nitride (AlN). Is at least one of The thermal spray material powder is a collection of such particles.

このような溶射材料粉末のプラズマ溶射により、コア材１１の表面に皮膜された被服材１０が高温状態となって溶けるがコア材１１は溶けない状態として、リードフレーム１および成形樹脂５に溶着させるため、被服材１０がバインダーとなり、図２（ａ）に示すように、被服材１０が奥まで行き渡って絶縁層７を形成する。この場合、リードフレーム１および成形樹脂６が下側に露出する半導体モジュールの底面は、先に説明したように同一平面に形成されており、絶縁層７の積層後に凹凸等が形成されることなく、絶縁層７の下側面は平面状に形成される。   By this plasma spraying of the thermal spray material powder, the clothing material 10 coated on the surface of the core material 11 is melted at a high temperature, but the core material 11 is not melted and is welded to the lead frame 1 and the molding resin 5. For this reason, the clothing material 10 becomes a binder, and the clothing material 10 extends to the back to form the insulating layer 7 as shown in FIG. In this case, the bottom surface of the semiconductor module where the lead frame 1 and the molding resin 6 are exposed on the lower side is formed on the same plane as described above, so that no irregularities or the like are formed after the insulating layer 7 is laminated. The lower surface of the insulating layer 7 is formed in a planar shape.

この絶縁層７の厚みは溶射時間をコントロールすることにより調整できる。絶縁層７の厚みは、先に説明したが、５０〜５００μｍが好ましい。特に厚みが約５００μｍまで達すると交流破壊電圧で１０ｋＶ以上有しており、耐電圧定格が１２００Ｖのパワー素子にも用いることができる。   The thickness of the insulating layer 7 can be adjusted by controlling the spraying time. As described above, the thickness of the insulating layer 7 is preferably 50 to 500 μm. In particular, when the thickness reaches about 500 μm, it has an AC breakdown voltage of 10 kV or more, and can be used for a power element having a withstand voltage rating of 1200 V.

（７）絶縁層７が形成された後にマスク８を外して半導体モジュール１００を完成させる（図３（ｆ））
このように（１）〜（７）の工程を経て、半導体モジュール１００が製造されることとなる。 (7) After the insulating layer 7 is formed, the mask 8 is removed to complete the semiconductor module 100 (FIG. 3F).
Thus, the semiconductor module 100 is manufactured through the steps (1) to (7).

以上、本発明の半導体モジュールおよびその製造方法について説明した。本実施形態では回路素子の具体例としてパワー半導体２，駆動ＩＣ３を例に挙げて説明した。しかしながら、本発明は回路素子がパワー半導体２，駆動ＩＣ３に限定される趣旨ではなく、他の半導体・ＩＣ・抵抗・コンデンサ・コイル等各種の素子を回路素子に含めるものである。このような各種の半導体モジュールにも本発明の適用は可能である。   The semiconductor module and the manufacturing method thereof according to the present invention have been described above. In the present embodiment, the power semiconductor 2 and the driving IC 3 have been described as examples of circuit elements. However, the present invention is not intended to limit the circuit elements to the power semiconductor 2 and the driving IC 3, and includes various elements such as other semiconductors, ICs, resistors, capacitors, coils, and the like. The present invention can also be applied to such various semiconductor modules.

このように本発明によれば、リードフレーム１の下側に熱抵抗が小さい（熱伝導率が大きい）絶縁層７をプラズマ溶射法により形成することとした。これにより成形樹脂の充填性を考慮してパワー半導体の下側の成形樹脂の厚さを大きくする必要性や、ボンディングワイヤの変形、断線の原因ともなる成形時の樹脂注入圧力を高くする必要性をなくした。また、熱伝導率が高いセラミックス材料を用い、さらに絶縁層を薄く（例えば１５０μｍ）形成して、従来よりも大幅に熱抵抗を小さくした。これにより、フルモールドの半導体モジュールの冷却性能を著しく向上させることができる。   As described above, according to the present invention, the insulating layer 7 having a low thermal resistance (high thermal conductivity) is formed on the lower side of the lead frame 1 by the plasma spraying method. This makes it necessary to increase the thickness of the molding resin on the lower side of the power semiconductor in consideration of the filling property of the molding resin, and to increase the resin injection pressure at the time of molding that causes deformation of the bonding wire and disconnection. Lost. Further, a ceramic material having a high thermal conductivity was used, and an insulating layer was further thinly formed (for example, 150 μm), so that the thermal resistance was significantly reduced as compared with the prior art. Thereby, the cooling performance of a full mold semiconductor module can be remarkably improved.

また、従来技術のように熱抵抗を小さくできるが、製造コスト・材料コストが増大する金属ベース基板、または、焼結体であるセラミックス製配線板を製造する代わりに、絶縁層７を溶射形成するというものであり、製造コスト・材料コストが従来よりも増大する事態を回避することができる。また、絶縁層７の形状はマスクの孔により決定されるため、複雑な形状も可能となる。   Further, the thermal resistance can be reduced as in the prior art, but the insulating layer 7 is formed by thermal spraying instead of manufacturing a metal base substrate or a ceramic wiring board which is a sintered body, which increases manufacturing costs and material costs. Therefore, it is possible to avoid a situation in which the manufacturing cost and material cost increase compared to the conventional case. Further, since the shape of the insulating layer 7 is determined by the hole of the mask, a complicated shape is possible.

また、消費電力からみた適用範囲が２００Ｖ５０Ａを超えて熱発生量が大きいパワー半導体に対応するような冷却性能を有する半導体モジュールを実用化することができる。   In addition, a semiconductor module having a cooling performance corresponding to a power semiconductor having a heat generation amount exceeding 200V50A in terms of power consumption can be put into practical use.

本発明を実施するための最良の形態の半導体モジュールの断面構成図である。It is a cross-sectional block diagram of the semiconductor module of the best form for implementing this invention. 絶縁層の説明図である。It is explanatory drawing of an insulating layer. 本発明を実施するための最良の形態に半導体モジュールの製造方法の説明図である。It is explanatory drawing of the manufacturing method of a semiconductor module in the best form for implementing this invention. 従来のフルモールド半導体モジュールの第１例を示す断面図である。It is sectional drawing which shows the 1st example of the conventional full mold semiconductor module. 従来のフルモールド半導体モジュールの第２例を示す断面図である。It is sectional drawing which shows the 2nd example of the conventional full mold semiconductor module. 従来のフルモールド半導体モジュールの第３例を示す断面図である。It is sectional drawing which shows the 3rd example of the conventional full mold semiconductor module.

符号の説明Explanation of symbols

１００：半導体モジュール
１：リードフレーム
２：パワー半導体
３：駆動ＩＣ
４：ボンディングワイヤ
５：ボンディングワイヤ
６：成形樹脂
７：セラッミクス絶縁層
８：マスク
１０：被服材
１１：コア材 100: Semiconductor module 1: Lead frame 2: Power semiconductor 3: Drive IC
4: Bonding wire 5: Bonding wire 6: Molding resin 7: Ceramics insulating layer 8: Mask 10: Clothing material 11: Core material

Claims (6)

１または複数の回路素子を搭載し、樹脂によって封止され、形成された半導体モジュールにおいて、
回路素子を搭載するための回路パターンが形成されたリードフレームと、
回路素子およびリードフレームを覆うように一方の面に設けられる成形樹脂と、
成形樹脂およびリードフレームを覆うように他方の面に設けられる絶縁層と、
を備え、
前記絶縁層は、コア材の表面を覆う被服材が相互に溶着して形成された層であることを特徴とする半導体モジュール。 In a semiconductor module in which one or more circuit elements are mounted and sealed with resin,
A lead frame on which a circuit pattern for mounting circuit elements is formed;
Molding resin provided on one surface so as to cover the circuit element and the lead frame;
An insulating layer provided on the other surface so as to cover the molding resin and the lead frame;
With
The semiconductor module according to claim 1, wherein the insulating layer is a layer formed by welding materials covering a surface of the core material to each other. 請求項１に記載の半導体モジュールにおいて、
被服材が酸化珪素であり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする半導体モジュール。 The semiconductor module according to claim 1,
A semiconductor module, wherein the clothing material is silicon oxide and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride. 請求項１に記載の半導体モジュールにおいて、
被服材が酸化アルミニウムであり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする半導体モジュール。 The semiconductor module according to claim 1,
A semiconductor module, wherein the clothing material is aluminum oxide and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride. １または複数の回路素子を搭載し、樹脂によって封止され、形成された半導体モジュールの製造方法において、
予め成形加工されたリードフレームに回路素子を接合する第１工程と、
回路素子とリードフレームとをボンディングワイヤにより接続する第２工程と、
回路素子およびリードフレームを覆う成形樹脂を一方の面に形成する第３工程と、
コア材の表面に被服材が皮膜されてなる溶射材料粉末をプラズマ溶射法により他方の面に溶射して、成形樹脂およびリードフレームを覆う絶縁層を形成する第４工程と、
を有することを特徴とする半導体モジュールの製造方法。 In a method for manufacturing a semiconductor module in which one or more circuit elements are mounted and sealed with a resin,
A first step of joining a circuit element to a pre-molded lead frame;
A second step of connecting the circuit element and the lead frame by a bonding wire;
A third step of forming a molding resin covering the circuit element and the lead frame on one surface;
A fourth step of forming an insulating layer covering the molding resin and the lead frame by spraying a thermal spray material powder formed by coating a coating material on the surface of the core material on the other surface by a plasma spraying method;
A method for manufacturing a semiconductor module, comprising: 請求項４に記載の半導体モジュールの製造方法において、
被服材が酸化珪素であり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする半導体モジュールの製造方法。 In the manufacturing method of the semiconductor module according to claim 4,
A method for manufacturing a semiconductor module, wherein the clothing material is silicon oxide and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride. 請求項４に記載の半導体モジュールの製造方法において、
被服材が酸化アルミニウムであり、また、コア材が窒化珪素、窒化アルミニウム、窒化ホウ素の少なくとも一つであることを特徴とする半導体モジュールの製造方法。 In the manufacturing method of the semiconductor module according to claim 4,
A method for manufacturing a semiconductor module, wherein the clothing material is aluminum oxide and the core material is at least one of silicon nitride, aluminum nitride, and boron nitride.
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