CN1497688A - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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Publication number
CN1497688A
CN1497688A CNA031603378A CN03160337A CN1497688A CN 1497688 A CN1497688 A CN 1497688A CN A031603378 A CNA031603378 A CN A031603378A CN 03160337 A CN03160337 A CN 03160337A CN 1497688 A CN1497688 A CN 1497688A
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China
Prior art keywords
conducting film
wiring layer
circuit arrangement
manufacture method
conductive wiring
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Granted
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CNA031603378A
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CN1254856C (zh
Inventor
五十岚优助
坂本则明
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1497688A publication Critical patent/CN1497688A/zh
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Publication of CN1254856C publication Critical patent/CN1254856C/zh
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Abstract

一种电路装置的制造方法，目前开发了：以具有导电图案的挠性板为支承衬底、在其上安装半导体元件并进行整体模装的半导体装置。这种情况下，会产生不能形成多层配线结构的问题及制造工序中绝缘树脂板的挠曲明显的问题。本发明的电路装置的制造方法中，采用介由第三导电膜13层积薄的第一导电膜11和厚的第二导电膜12构成的层积板10。在通过蚀刻第一导电膜11形成第一导电配线层11A的工序中，通过由第三导电膜13使蚀刻停止，可控制蚀刻的深度。因此通过较薄地形成第一导电膜11，可使第一导电配线层11A形成微细图案。另外，由于介由第一绝缘层15形成第二导电配线层14A，故可实现多层配线。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法，特别是涉及使用了介由在蚀刻工序中形成阻挡层的第三导电膜层积的两张导电膜的、具有多层配线结构的、薄型电路装置的制造方法。
背景技术
近年来，IC组件在移动设备或小型高密度安装设备的采用正在发展，以往的IC组件及其安装概念正在发生很大的变化。作为有关现有半导体装置的技术，有作为绝缘树脂板的一例采用挠性板即聚酰亚胺树脂板的半导体装置(例如参照专利文献1)。
图19～图21是将挠性板50用作插入式选择(イ ンタ-ポ-ザ)衬底的图。另外，各图中上面的图为平面图，下面的图为A-A线剖面图。
首先，在图19所示的挠性板50之上面通过粘接剂粘合铜箔图案51备用。该铜箔图案51根据安装的半导体元件为晶体管、IC其图案不同，但是，通常形成有焊盘51A和岛51B。符号52是用于将电极自挠性板50的背面取出的开口部，所述铜箔图案51露出。
然后，该挠性板50被输送到装片机，如图20所示，安装半导体元件53。之后，该挠性板50被搬运到引线接合器，用金属配线54电连接焊盘51A和半导体元件53的焊盘。
最后，如图21(A)所示，在挠性板50的表面上设置密封树脂55进行密封。在此，进行传递模模装，覆盖焊盘51A、岛51B、半导体元件53和金属配线54。
之后，如图21(B)所示，设置焊锡或焊球等连接装置56，使其通过焊锡反射炉，经开口部52形成和焊盘51A熔接的球状焊锡56。而且，由于在挠性板50上半导体元件53矩阵状形成，故经如图20所示进行切割，而被一个个分离。
图21(C)所示的剖面图是在挠性板50的两面形成有作为电极的51A和51D的图。该挠性板50通常两面制图由厂家提供。
专利文献1：特开2000-133678号公报(第5页，图2)。
发明内容
由于使用上述挠性板50的半导体装置不使用公知的金属框，故具有可实现极小型且薄型的封装结构的优点，但实质上仅由设在挠性板50表面的一层铜箔图案51进行配线。这由于挠性板很柔软，故在导电膜的图案形成前后会产生变形，层积的层间位置偏移大，存在不适于多层配线结构的问题。
为了实现多层配线结构，需要抑制板的变形的支承强度，为此，需要使挠性板50足够厚，约为200μm，这有违薄型化。
另外，在制造方法中，在所述制造装置例如装片机、引线接合器、传递模装置及反射炉中，挠性板50要被搬运安装在称作工作台或桌子的部分。
但是，当减薄作为挠性板50的基座的绝缘树脂的厚度使其为50μm左右时，形成在表面上的铜箔图案51的厚度也很薄为9～35μm，此时，如图22所示，会因挠曲等而使搬运性非常不好，或向所述工作台或桌子的安装性能很差。这可以考虑因绝缘树脂自身非常薄而导致的挠曲和铜箔图案51与绝缘树脂的热膨胀系数之差引起的挠曲。
开口部52的部分在模装时要自上方加压，故会作用使焊盘51A的周边向上挠曲的力，使焊盘51A的粘接性能恶化。
若构成挠性板50的树脂材料自身无挠性或为了提高导热型而混入填充物，则变硬。在该状态下，有时在由引线接合器进行接合时会在接合部产生裂纹。在传递模模装时，有时在模型接触的部分也会产生裂纹。如图22所示在存在挠曲时，这一点会更明显。
如上说明的挠性板50都是背面未形成电极的挠性板，但是如图21(C)所示，有时在挠性板50的背面也形成电极51D。此时，电极51D会与所述制造装置接触，或与该制造装置间的搬运装置的搬运面接触，故会损伤电极51D的背面。由于在带有该损伤的状态下直接构成电极，故存在因之后的加热等而在电极51D自身产生裂纹的问题或在向母板进行焊接时使焊剂浸润性降低的问题。
当在挠性板50的背面设置电极51D时，在传递模模装时，会产生不能与工作台面接触的问题。这种情况下，若如上所述由硬的材料构成挠性板50，则电极51D形成支点，电极51D的周围被向下方加压，故存在在挠性板50产生裂纹的问题。
本发明的发明者为了解决上述问题，提出了使用层积板的提案，该层积板是介由第三导电膜使薄的第一导电膜和厚的第二导电膜层积构成的层积板。
本发明的第一方面提供一种电路装置的制造方法，其特征在于，包括下述工序：准备介由第三导电膜层积第一导电膜和第二导电膜构成的层积板；通过将所述第一导电膜蚀刻为所希望的图案，形成第一导电配线层；将所述第一导电配线层用作掩模选择性除去所述第三导电膜；将附着了第一绝缘层的绝缘板层积在第四导电膜上，使所述第一绝缘层覆盖通过除去所述第三导电膜而露出的第二导电膜表面部、所述第一导电配线层及第三导电膜端面；通过将所述第四导电膜蚀刻为所希望的图案，形成第二导电配线层；形成多层连接装置，将所述第一导电配线层和所述第二导电配线层电连接；用第二绝缘层覆盖所述第二导电配线层；通过局部除去所述第二绝缘层，使所述第二导电配线层选择性露出，形成露出部；将半导体元件固定在所述第二绝缘层上，电连接所述半导体元件和所述第二导电配线层；用密封树脂层覆盖所述半导体元件；除去所述第二绝缘层，使所述第三导电膜在背面露出；在所述第三导电膜的所希望的部位形成外部电极。
本发明第二方面的特征在于，蚀刻至所述第三导电膜微细地形成所述导电配线层。
本发明第三方面的特征在于，使用仅蚀刻所述第一导电膜的溶液。
本发明第四方面的特征在于，作为进行所述蚀刻的所述溶液，使用包含氯化铜或氯化铁的溶液。
本发明第五方面的特征在于，所述第三导电膜由电解剥离除去。。
本发明第六方面的特征在于，通过使用仅蚀刻所述第三导电膜的溶液进行的蚀刻除去所述第三导电膜。
本发明第七方面的特征在于，所述溶液为碘系溶液。
本发明第八方面的特征在于，整面蚀刻所述第二导电膜。
本发明第九方面的特征在于，所述第二导电膜形成得比所述第一导电膜厚。
本发明第十方面的特征在于，所述绝缘层是热塑性树脂、热硬性树脂或感光性树脂。
本发明第十一方面的特征在于，所述第一导电膜及所述第二导电膜是以铜为主材料的金属，所述第三导电膜是以银为主材料的金属。
本发明第十二方面的特征在于，以所述第二导电膜为底材，通过电镀层积所述第三导电膜和所述第一导电膜，制造所述层积板。
本发明第十三方面的特征在于，所述层积板由压延接合形成。
本发明第十四方面的特征在于，将所述露出并镀敷的第一导电膜部分和半导体元件以外的电子部件电连接。
本发明第十五方面的特征在于，所述绝缘板利用真空压制或真空叠片而形成。
本发明第十六方面的特征在于，利用激光加工局部除去所述绝缘层。
本发明第十七方面的特征在于，利用刻蚀工序局部除去所述绝缘层。
本发明第十八方面的特征在于，利用将所述第二导电层用作电极的电解镀敷，在局部除去所述第一绝缘层形成的通孔上，通过镀敷层积以铜为主的金属，连接所述第一导电配线层和所述第二导电配线层。
附图说明
图1是说明本发明电路装置制造方法的剖面图；
图2是说明本发明电路装置制造方法的剖面图；
图3是说明本发明电路装置制造方法的剖面图；
图4是说明本发明电路装置制造方法的剖面图；
图5是说明本发明电路装置制造方法的剖面图；
图6是说明本发明电路装置制造方法的剖面图；
图7是说明本发明电路装置制造方法的剖面图；
图8是说明本发明电路装置制造方法的剖面图；
图9是说明本发明电路装置制造方法的剖面图；
图10是说明本发明电路装置制造方法的剖面图；
图11是说明本发明电路装置制造方法的剖面图；
图12是说明本发明电路装置制造方法的剖面图；
图13是说明本发明电路装置制造方法的剖面图；
图14是说明本发明电路装置制造方法的剖面图；
图15是说明本发明电路装置制造方法的剖面图；
图16是说明本发明电路装置制造方法的剖面图；
图17是说明由本发明制造的电路装置的平面图；
图18是说明由本发明制造的电路装置的平面图；
图19是说明现有半导体装置制造方法的图；
图20是说明现有半导体装置制造方法的图；
图21是说明现有半导体装置制造方法的图；
图22是说明现有挠性板的图。
具体实施方式
下面参照图1～图18说明本发明的电路装置的制造方法。
本发明的电路装置的制造方法包括下述工序：准备介由第三导电膜层积第一导电膜和第二导电膜的层积板；通过将所述第一导电膜蚀刻为所希望的图案，形成第一导电配线层；将所述第一导电配线层用作掩模除去所述第三导电膜；将附着了第一绝缘层的绝缘板层积在第四导电膜上，使所述第一绝缘层覆盖通过除去所述第三导电膜而露出的第二导电膜表面部、所述第一导电配线层及第三导电膜端面；通过将所述第四导电膜蚀刻为所希望的图案，形成第二导电配线层；形成多层连接装置，将所述第一导电配线层和所述第二导电配线层电连接；用第二绝缘层覆盖所述第二导电配线层；通过局部除去所述第二绝缘层，使所述第二导电配线层选择性露出，形成露出部；将半导体元件固定在所述第二绝缘层上，电连接所述半导体元件和所述第二导电配线层；用密封树脂层覆盖所述半导体元件；除去所述第二绝缘层，使所述第三导电膜背面露出；在所述第三导电膜的所希望的部位形成外部电极。下面说明上述各工序。
如图1所示，本发明的第一工序是准备介由第三导电膜13层积薄的第一导电膜11和厚的第二导电膜12构成的层积板10。
层积板10的表面实质上在整个区域形成第一导电膜11，介由第三导电膜13，在背面也实质上在整个区域形成第二导电膜12。第一导电膜11及第二导电膜12理想的是由以铜为主材的材料或公知的引线架材料构成。第一导电膜11、第二导电膜12及第三导电膜13可由镀敷法、蒸镀法或溅射法形成，或粘贴由压延法或镀敷法形成的金属箔。另外，作为第一导电膜11及第二导电膜12也可以是铝、铁、铁镍合金及公知的引线架材料等。
第三导电膜13的材料采用不被除去第一导电膜11及第二导电膜12时使用的蚀刻液蚀刻的材料。另外，由于在第三导电膜13背面形成由焊锡等构成的外部电极24，故也要考虑外部电极24的粘接性能。具体地说，作为第三导电膜13的材料可采用金、银、钯构成的导电材料。
第一导电膜的厚度为了形成微细的图案而形成得很薄，其厚度为5～35μm左右。第二导电图案由于要机械支承整体，故形成得较厚，其厚度是70～200μm左右。第三导电膜13在蚀刻第一导电膜11及第二导电膜12时起阻挡层的作用，其厚度是1～10μm左右。
本发明的特征点在于，使第二导电膜12比第一导电膜11厚。第一导电膜的厚度为5～35μm左右，以可尽可能薄地形成微细图案。第二导电膜12的厚度为70～200μm左右即可，这是为了使其具有支承强度。
因此，通过较厚地形成第二导电膜12，可维持层积板10的平坦性，可提高后道工序的操作性。
另外，第二导电膜12由于要经过各个工序，故会产生损伤。但是由于厚的第二导电膜12要在后道工序除去，故可防止作为成品的电路装置产生损伤。由于可维持平坦性并硬化密封树脂，故也可使封装的背面平坦，形成于层积板10背面的外部电极也可平整地配置。因此，可使安装衬底上的电极和层积板10背面的电极接触，可防止焊剂缺陷。
下面说明上述层积板10的具体制造方法。层积板10可通过电镀进行的层积或压延接合进行制造。在由电镀制造层积板10时，首先要准备第二导电膜12。然后，在第二导电膜12的背面设置电极，利用电解电镀法层积第三导电膜。之后，同样利用电解电镀法在第三导电膜上层积第一导电膜。在利用压延制造层积板时，用压辊等施加热和压力接合准备成板状的第一导电膜11、第二导电膜12及第三导电膜13。
如图2及图3所示，本发明的第二工序在于，通过将第一导电膜11蚀刻为所希望的图案，形成第一导电配线层11A。
用所希望的图案的光致抗蚀剂PR覆盖在第一导电膜11上，利用化学蚀刻形成焊盘和形成配线的第一导电配线层11A。由于第一导电膜11是以铜为主材的，故蚀刻液使用氯化铁或氯化铜即可。由于蚀刻第一导电膜11，第三导电膜13也会和蚀刻液接触，但是由于第三导电膜13的材料是不会被氯化铁或氯化铜蚀刻的材料，故蚀刻在第三导电膜13的表面停止。这样，第一导电膜11形成5～35μm左右的厚度，因此，第一导电配线层11A可形成50μm以下的精细图案。另外，如图3所示，抗蚀剂PR在形成第一导电配线层11A后被除去。
本发明的特征在于，在蚀刻第一导电膜11的工序中，由第三导电膜13使蚀刻停止。在本工序中，被蚀刻的第一导电膜11主要由铜构成，作为局部除去铜的蚀刻液使用氯化铁或氯化铜。与此相对，第三导电膜13由不会被氯化铁及氯化铜蚀刻的导电性材料形成，故蚀刻在第三导电膜13的表面停止。第三导电膜13的材料可采用金、银及钯。
如图4所示，本发明的第三工序在于，将第一导电配线层11A作为掩模使用，除去第三导电膜13。
将在前工序中形成的第一导电膜11构成的第一导电配线层11A用作掩模，选择性除去第三导电膜13。作为选择性除去第三导电膜13的方法可采用两种方法。第一种方法是用仅除去第三导电膜13的液体进行蚀刻的方法。第二种方法是利用电解剥离仅除去第三导电膜13的方法。
下面说明利用第一种方法的蚀刻局部除去第三导电膜13的方法。该方法中使用的蚀刻液使用蚀刻第三导电膜13且不会蚀刻第一导电配线层11A及第二导电膜12的蚀刻液。例如，在第一导电配线层11A及第二导电膜12主要由铜形成且第三导电膜13为银膜的情况下，可通过使用碘系蚀刻液仅除去第三导电膜13。通过蚀刻第三导电膜13第二导电膜12虽然会与碘系蚀刻液接触，但是，例如由铜构成的第二导电膜12不会被碘系蚀刻液蚀刻。因此，这里的蚀刻在第二导电膜12的表面停止。在此，图2的抗蚀剂PR也可在该工序之后除去。
下面说明利用第二种方法即电解剥离仅除去第三导电膜13的方法。首先，使包含金属离子的溶液与第三导电膜13接触。然后，在溶液侧设置正电极，在层积板10设置负电极，接通直流电流。这样，利用和利用电解法形成镀膜相反的原理仅除去第三导电膜13。这里使用的溶液是用于镀敷处理构成第三导电膜13的材料时使用的溶液。因此，该方法仅剥离第三导电膜13。
如图5所示，本发明的第四工序在于，将附着了第一绝缘层15的绝缘板9层积在第四导电膜14上，由第一绝缘层15覆盖第一导电配线层11A及第三导电膜13。
参照图5，第三导电膜13、第一导电配线层11A及局部露出的第二导电膜12表面由第一绝缘层15覆盖。具体地说，被局部除去的第三导电膜13的侧面及第一导电配线层11A的上面及侧面(端面)被由第一绝缘层15覆盖。局部露出的第二导电膜12的表面也被由第一绝缘层15覆盖。本工序的绝缘板9进行的覆盖可利用真空压制或叠片的方法进行。真空压制是将绝缘板重叠在层积板10上以真空进行加压的方法，可将多个层积板10一起处理。叠片的方法是用压辊层积绝缘板9的方法。在叠片的方法中，虽然后固化工序要利用成批处理在另一工序进行，但是具有可高精度控制厚度的优点。也可在用上述方法仅形成第一绝缘层15之后，用无电解镀敷及电解镀敷形成第四导电膜。
如图6及图7所示，本发明的第五工序在于，通过将第四导电膜14蚀刻为所希望的图案形成第二导电配线层14A。
参照图6，通过在蚀刻工序局部除去第四导电膜14，形成第二导电配线层14A。由于第四导电膜14形成得很薄，蚀刻在第一绝缘层停止，故可微细地形成第二导电配线层14A。在此，第四导电膜14厚度形成为5～35μm，故第二导电配线层14A可形成50μm以下的微细图案。
然后，参照图7，通过形成通孔16，使第一导电配线层11A局部露出。形成该通孔16的部分在形成第二导电配线层14A时同时利用蚀刻除去第四导电膜14。第二导电配线层14A以铜为主材料，故蚀刻液使用氯化铁或氯化铜进行化学蚀刻。通孔16的开口直径因刻蚀的图象分辨率而变化，但是在此为50～100μm左右。在进行该蚀刻时，第二导电膜4由粘接性板等覆盖进行保护，以不受蚀刻液影响。但是，只要第二导电膜4自身膜厚足够厚，且蚀刻后也可维持平坦性，则即使稍微被蚀刻也没关系。另外，第二导电配线层14A可以是铝、铁、铁镍合金、公知的引线架材料等。
然后，在去除光致抗蚀剂后，以第二导电配线层14A为掩模，用激光除去通孔16正下方的第一绝缘层15，使第一导电配线层11A的表面在通孔16的底部露出。激光最好采用二氧化碳气激光。在用激光使绝缘树脂蒸发后，在开口部的底部存在残渣的情况下，用过锰酸纳或过硫酸铵等进行湿式蚀刻，除去该残渣。
本工序中，在第二导电配线层14A很薄，在10μm以下时，可在用光致抗蚀剂覆盖通孔16以外之后，用二氧化碳气激光使第二导电配线层14A及第一绝缘层15一起形成通孔16。这种情况下，需要预先使第二导电配线层14A的表面粗糙化的黑化处理工序。
如图8所示，本发明的第六工序在于，形成多层连接装置17，将第一导电配线层11A及第二导电配线层14A电连接。
在包含通孔16的第一导电配线层11A整个面上形成多层连接装置17即镀膜，以进行第二导电配线层14A和第一导电配线层11A的电连接。该镀膜可用无电解镀敷和电解镀敷两种方法形成，在此，利用将第二导电膜12用作电极的电解镀敷形成镀膜，直至第二导电配线层14A和镀膜上面连接成平坦状态。此时，由抗蚀剂进行保护，使第二导电膜12及镀敷电极取出部以外的背面不附着镀膜。该抗蚀剂在由夹具包围表面镀敷部的局部夹具镀敷中不需要。这样，通孔1 6由铜埋入，形成多层连接装置17。另外，镀膜在此采用了铜，但也可采用Au、Ag、Pd等。
如图9所示，本发明的第七工序在于，用第二绝缘层18覆盖第二导电配线层14A。
参照图9，用第二绝缘层18进行的覆盖可用树脂板利用真空压制或叠片方法进行，或用液态树脂通过印刷或用滚涂器或浸渍涂敷器进行涂敷。真空压制法是将由热硬性树脂构成的粘合材料板重叠并真空压制的方法，可将多张层积板10一起处理。叠片法是对层积板10一张张地使用辊粘接热硬性树脂板。该方法中，虽然后固化工序要利用成批处理在另一工序进行，但是具有可高精度控制厚度的优点。液态树脂在用各方法涂敷后要进行干燥处理。
参照图10，本发明的第八工序在于，通过局部除去第二绝缘层18，使第二导电配线层14A选择性露出，形成露出部。
参照图10，为了与预定载置在第二绝缘层18上的半导体元件19进行电连接，将第二绝缘层18局部除去，使第二导电配线层14A露出。露出的第二导电配线层14A为成为接合焊盘的部分。在第二绝缘层18由感光性材料构成的情况下，可由公知的刻蚀工序局部除去第二绝缘层18。也可利用激光局部除去第二绝缘层18。作为激光最好采用二氧化碳气激光。在用激光使第二绝缘层18蒸发后，在开口部的底部存在残渣的情况下，用过锰酸纳或过硫酸铵等进行湿式蚀刻，除去该残渣。
然后，在露出并形成焊盘的第二导电配线层14A的表面上形成镀层21。镀层21的形成可通过用无电解镀敷法或电解镀敷法使金或银附着来进行。在本实施例中是用无电解镀敷法形成金膜。
参照图11，本发明的第九工序在于，将半导体元件19固定在第二绝缘层18上，将半导体元件19和第二导电配线层14A电连接。
半导体元件19以裸片状态利用绝缘性粘接树脂接合在第二绝缘层18上。半导体元件19和第二导电配线层14A利用第二绝缘层18电绝缘，故第二导电配线层14A即使在半导体元件19之下也可自由配线，可实现多层配线结构。
半导体元件19的各电极焊盘用接合引线20与设于周边的第二导电配线层14A的一部分即焊盘连接。半导体元件19也可以面朝下安装。这种情况下，要在半导体元件19的各电极焊盘表面设置焊球或补片，在层积板10的表面，在与焊球位置对应的部分设置与由第二导电配线层14A构成的接合焊盘同样的电极。
下面说明进行引线接合时使用层积板10的优点。通常，在进行金线的引线接合时，要加热到120℃～300℃。此时，若第二导电膜12很薄，层积板10就会挠曲，当在该状态下，通过焊接头对层积板10加压时，就有可能使层积板10损伤。但是，通过较厚地形成第二导电膜12自身，可以解决这些问题。
如图12所示，本发明的第十工序在于，用密封树脂层22覆盖半导体元件19。
层积板10被设置在模装装置上进行树脂模装。模装方法可使用传递模模装、注射模模装、涂敷、罐封等进行。但是考虑到批量生产，则适用传递模模装、注射模模装。
在本工序中，层积板10必须平整地接触模腔的下模，厚的第二导电膜12起该作用。而且，自模腔取出后，直至密封树脂层13的收缩结束，也会由第二导电膜12维持封装的平坦性。也就是说，本工序之前层积板10的机械支承作用由第二导电膜12承担。
如图13所示，本发明的第十一工序在于，除去第二导电膜12使第三导电膜13露出背面。
通过不用掩模进行蚀刻，将第二导电膜12整面除去。该蚀刻可以是使用氯化铁或氯化铜的化学蚀刻，第二导电膜12被整面除去。这样，通过整面除去第二导电膜12，使第三导电膜13自绝缘层15露出。如上所述，第三导电膜13由在蚀刻第二导电膜12的溶液中不被蚀刻的材料形成，故在本工序中第三导电膜13不被蚀刻。
本工序的特征在于，在通过蚀刻除去第二导电膜12的工序中，由于第三导电膜13形成阻挡层，故绝缘层17及第三导电膜13构成的背面平坦地形成。第二导电膜12由于通过蚀刻被整面除去，故在蚀刻的最终阶段，第三导电膜13也会接触蚀刻液。如上所述，第三导电膜13由下述材料构成，这种材料是不会被蚀刻由铜构成的第二导电膜12的氯化铁及氯化铜蚀刻的材料。因此，在第三导电膜13的下面蚀刻停止，故第三导电膜13具有作为蚀刻的阻挡层的功能。另外，在本工序之后，整体由密封树脂层22机械支承。
如图14～图16所示，本发明的第十二工序在于，在第三导电膜13的所希望部位形成外部电极24。
此时，在银的迁移被视为问题的环境中使用的情况下，在用绝缘板9进行覆盖之前，最好选择性蚀刻并除去第三导电膜13。首先，参照图14，第三导电膜13使形成外部电极24的部分露出，网印由溶剂溶解的环氧树脂等，用外敷树脂23覆盖大部分。在所述外敷树脂23由感光性材料构成的情况下，形成外部电极24的部分可在公知的刻蚀工序局部除去所述外敷树脂23。然后，参照图15，利用焊剂的回流或乳酪焊剂的网印，在该露出部分同时形成外部电极24。
最后，参照图16，在层积板10矩阵状形成多个电路装置，切割密封树脂层22及外敷树脂23，将它们分离为一个个电路装置。
在本工序中，露出在背面的第三导电膜13构成形成外部电极24时的镀层，故在第三导电膜13仅构成外部电极24的情况下，可省略重新形成镀层的工序。可不切割铜部而仅切割密封树脂层22及外敷树脂23而分离为一个个电路装置，故可减少进行切割的切割机的磨损。
参照图17说明具化的本发明的制造方法制造的电路装置1。首先，实线所示的图案是第二导电配线层14A，虚线所示的图案是第一导电配线层11A。第二导电配线层14A围绕半导体元件19在周边设置有焊盘，局部配置为两级，与具有多个焊盘的半导体元件19对应。由第二导电配线层14A构成的接合焊盘与半导体元件19对应的电极焊盘由接合引线20连接，多个微细图案的第二导电配线层14A自接合焊盘延伸至半导体元件19之下，由实心圆所示的多层连接装置17与第一导电配线层11A连接。另外，第一导电配线层11A也可形成微细图案，可形成更多的外部电极24。
如果是这种结构，即使是具有200以上的焊盘的半导体元件，也可利用第二导电配线层14A的微细图案直至微细化的所希望的第一导电配线层11A以多层配线结构延伸，可自设于第三导电膜13的外部电极24向外部电路进行连接。
参照图18，说明具化的另一形态的电路装置1A。在此，电路装置1A形成虚线所示的第二导电配线层14A，在第二导电配线层14A上安装有半导体元件19、片状部件25及裸的晶体管26。片状部件25可全盘采用电阻、电容器、二极管、线圈等无源元件、有源元件。内装的部件相互间通过第一导电配线层11A或接合引线20电连接。并且，在与半导体元件19对应的部位形成第一导电配线层11A，可自设于第三导电膜13的外部电极24向外部电路进行连接。
根据本发明，在蚀刻形成得很薄的第一导电膜11并形成第一导电配线层11A的工序中，通过作为阻挡层设置第三导电膜13，可在规定的深度使蚀刻停止。因此，具有可通过较薄地形成第一导电膜11微细地形成第一导电配线层11A的优点。并且，介由第一绝缘层15，第二导电配线层14A也微细地形成，故可实现多层配线。
另外，在通过自背面蚀刻整面除去第二导电膜12的工序中，通过使第三导电膜13作为阻挡层起作用，具有可平坦地形成由绝缘层15及由此露出的第三导电膜构成的背面的优点。由此可提高作为成品的电路装置背面的平坦性，故可提高其品质。

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1、一种电路装置的制造方法，其特征在于，包括下述工序：准备介由第三导电膜层积第一导电膜和第二导电膜构成的层积板；通过将所述第一导电膜蚀刻为所希望的图案，形成第一导电配线层；将所述第一导电配线层用作掩模选择性除去所述第三导电膜；将附着了第一绝缘层的绝缘板层积在第四导电膜上，使所述第一绝缘层覆盖通过除去所述第三导电膜而露出的第二导电膜表面部、所述第一导电配线层及第三导电膜端面；通过将所述第四导电膜蚀刻为所希望的图案，形成第二导电配线层；形成多层连接装置，将所述第一导电配线层和所述第二导电配线层电连接；用第二绝缘层覆盖所述第二导电配线层；通过局部除去所述第二绝缘层，使所述第二导电配线层选择性露出，形成露出部；将半导体元件固定在所述第二绝缘层上，电连接所述半导体元件和所述第二导电配线层；用密封树脂层覆盖所述半导体元件；除去所述第二绝缘层，使所述第三导电膜在背面露出；在所述第三导电膜的所希望的部位形成外部电极。
2、如权利要求1所述的电路装置的制造方法，其特征在于，蚀刻至所述第三导电膜微细地形成所述导电配线层。
3、如权利要求1所述的电路装置的制造方法，其特征在于，使用仅蚀刻所述第一导电膜的溶液。
4、如权利要求3所述的电路装置的制造方法，其特征在于，作为进行所述蚀刻的所述溶液，使用包含氯化铜或氯化铁的溶液。
5、如权利要求1所述的电路装置的制造方法，其特征在于，所述第三导电膜由电解剥离除去。。
6、如权利要求1所述的电路装置的制造方法，其特征在于，通过使用仅蚀刻所述第三导电膜的溶液进行的蚀刻除去所述第三导电膜。
7、如权利要求6所述的电路装置的制造方法，其特征在于，所述溶液为碘系溶液。
8、如权利要求1所述的电路装置的制造方法，其特征在于，整面蚀刻所述第二导电膜。
9、如权利要求1所述的电路装置的制造方法，其特征在于，所述第二导电膜形成得比所述第一导电膜厚。
10、如权利要求1所述的电路装置的制造方法，其特征在于，所述绝缘层是热塑性树脂、热硬性树脂或感光性树脂。
11、如权利要求1所述的电路装置的制造方法，其特征在于，所述第一导电膜及所述第二导电膜是以铜为主材料的金属，所述第三导电膜是以银为主材料的金属。
12、如权利要求1所述的电路装置的制造方法，其特征在于，以所述第二导电膜为底材，通过电镀层积所述第三导电膜和所述第一导电膜，制造所述层积板。
13、如权利要求1所述的电路装置的制造方法，其特征在于，所述层积板由压延接合形成。
14、如权利要求1所述的电路装置的制造方法，其特征在于，将所述露出并镀敷的第一导电膜部分和半导体元件以外的电子部件电连接。
15、如权利要求1所述的电路装置的制造方法，其特征在于，所述绝缘板利用真空压制或真空叠片而形成。
16、如权利要求1所述的电路装置的制造方法，其特征在于，利用激光加工局部除去所述绝缘层。
17、如权利要求1所述的电路装置的制造方法，其特征在于，利用刻蚀工序局部除去所述绝缘层。
18、如权利要求1所述的电路装置的制造方法，其特征在于，利用将所述第二导电层用作电极的电解镀敷，在局部除去所述第一绝缘层形成的通孔上，通过镀敷层积以铜为主的金属，连接所述第一导电配线层和所述第二导电配线层。
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Families Citing this family (14)

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Publication number Priority date Publication date Assignee Title
JP4086607B2 (ja) 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4052915B2 (ja) * 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP2004119727A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4115228B2 (ja) * 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法
TWM323107U (en) * 2007-04-03 2007-12-01 Jin-Chiuan Bai Thin type semiconductor chip package substrate
US7473586B1 (en) * 2007-09-03 2009-01-06 Freescale Semiconductor, Inc. Method of forming flip-chip bump carrier type package
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
JP5629969B2 (ja) 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
US7830024B2 (en) * 2008-10-02 2010-11-09 Advanced Semiconductor Engineering, Inc. Package and fabricating method thereof
KR101030356B1 (ko) * 2008-12-08 2011-04-20 삼성전기주식회사 반도체 패키지의 제조 방법
KR101010739B1 (ko) * 2009-02-17 2011-01-25 이원배 열접촉 패드를 구비한 전기가열보온장치
KR20140108865A (ko) * 2013-03-04 2014-09-15 삼성전자주식회사 패키지 기판, 패키지 기판의 제조 방법 및 패키지 기판을 포함하는 반도체 패키지
TWI572261B (zh) * 2014-10-29 2017-02-21 健鼎科技股份有限公司 線路結構及線路結構的製作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3720209A (en) * 1968-03-11 1973-03-13 Medical Plastics Inc Plate electrode
KR100437437B1 (ko) * 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US6143116A (en) * 1996-09-26 2000-11-07 Kyocera Corporation Process for producing a multi-layer wiring board
US6120693A (en) * 1998-11-06 2000-09-19 Alliedsignal Inc. Method of manufacturing an interlayer via and a laminate precursor useful for same
JP4509437B2 (ja) * 2000-09-11 2010-07-21 Ｈｏｙａ株式会社 多層配線基板の製造方法
JP2003007918A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119727A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4086607B2 (ja) * 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP4052915B2 (ja) * 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
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