CN1254861C - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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Publication number
CN1254861C
CN1254861C CNB031603386A CN03160338A CN1254861C CN 1254861 C CN1254861 C CN 1254861C CN B031603386 A CNB031603386 A CN B031603386A CN 03160338 A CN03160338 A CN 03160338A CN 1254861 C CN1254861 C CN 1254861C
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Prior art keywords
conducting film
conductive pattern
circuit arrangement
manufacture method
anchoring section
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Expired - Fee Related
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CNB031603386A
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CN1497692A (zh
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五十岚优助
水原秀树
坂本则明
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Publication of CN1497692A publication Critical patent/CN1497692A/zh
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Abstract

一种电路装置的制造方法，目前开发了：以具有导电图案的挠性板为支承衬底、在其上安装半导体元件并进行整体模装的半导体装置。这种情况下，会产生不能形成多层配线结构的问题及制造工序中绝缘树脂板的挠曲明显的问题。本发明的电路装置的制造方法中，采用介由第三导电膜13层积薄的第一导电膜11和厚的第二导电膜12构成的层积板10。通过蚀刻薄的第一导电膜11形成微细图案的导电图案层11A，之后，以导电图案层11A为掩模超量蚀刻第三导电膜13制作锚固部15，使绝缘粘接层16及密封树脂层22咬入锚固部15，加强绝缘粘接层16及密封树脂层22和导电图案层11A的结合。

Description

电路装置的制造方法
技术领域
本发明涉及电路装置的制造方法，特别是涉及使用了介由在蚀刻工序中形成阻挡层的第三导电膜层积的两张导电膜的薄型电路装置的制造方法。
背景技术
近年来，IC组件在移动设备或小型高密度安装设备的采用正在发展，以往的IC组件及其安装概念正在发生很大的变化。例如特开2000-133678号公报所公开的。其是有关作为绝缘树脂板的一例采用挠性板即聚酰亚胺树脂板的半导体装置的技术。
图16～图18是将挠性板50用作插入式选择(インタ一ポ一ザ)衬底的图。另外，各图中上面的图为平面图，下面的图为A-A线剖面图。
首先，在图16所示的挠性板50之上面通过粘接剂粘合铜箔图案51备用。该铜箔图案51根据安装的半导体元件为晶体管、IC其图案不同，但是，通常形成有焊盘51A和岛51B。符号52是用于将电极自挠性板50的背面取出的开口部，所述铜箔图案51露出。
然后，该挠性板50被输送到装片机，如图17所示，安装半导体元件53。之后，该挠性板50被搬运到引线接合器，用金属配线54电连接焊盘51A和半导体元件53的焊盘。
最后，如图18(A)所示，在挠性板50的表面上设置密封树脂55进行密封。在此，进行传递模模装，覆盖焊盘51A、岛51B、半导体元件53和金属配线54。
之后，如图18(B)所示，设置焊锡或焊球等连接装置56，使其通过焊锡回流炉，经开口部52形成和焊盘51A熔接的球状焊锡56。而且，由于在挠性板50上半导体元件53矩阵状形成，故经如图17所示进行切割，而被一个个分离。
图18(C)所示的剖面图是在挠性板50的两面形成有作为电极的51A和51D的图。该挠性板50通常两面制图由厂家提供。
专利文献1：美国专利第5976912号说明书(第23栏第4行～第24栏第9行，图22a～图22g)。
发明内容
由于使用上述挠性板50的半导体装置不使用公知的金属框，故具有可实现极小型且薄型的封装结构的优点，但实质上仅由设在挠性板50表面的一层铜箔图案51进行配线。这由于挠性板很柔软，故在导电膜的图案形成前后会产生变形，层积的层间位置偏移大，存在不适于多层配线结构的问题。
为了抑制板的变形，要提高支承强度，为此，需要使挠性板足够厚，约为200μm，这有违薄型化。
另外，在制造方法中，在所述制造装置例如装片机、引线接合器、传递模装置及回流炉中，挠性板50要被搬运安装在称作工作台或桌子的部分。
但是，当减薄作为挠性板50的基座的绝缘树脂的厚度使其为50μm左右时，形成在表面上的铜箔图案51的厚度也很薄为9～35μm，此时，如图19所示，会因挠曲等而使搬运性非常不好，或向所述工作台或桌子的安装性能很差。这可以考虑因绝缘树脂自身非常薄而导致的挠曲和铜箔图案51与绝缘树脂的热膨胀系数之差引起的挠曲。
开口部52的部分在模装时要自上方加压，故会作用使焊盘51A的周边向上挠曲的力，使焊盘51A的粘接性能恶化。
若构成挠性板50的树脂材料自身无挠性或为了提高导热型而混入填充物，则变硬。在该状态下，有时在由引线接合器进行接合时会在接合部产生裂纹。在传递模模装时，有时在模型接触的部分也会产生裂纹。如图19所示在存在挠曲时，这一点会更明显。
如上说明的挠性板50都是背面未形成电极的挠性板，但是如图18(C)所示，有时在挠性板50的背面也形成电极51D。此时，电极51D会与所述制造装置接触，或与该制造装置间的搬运装置的搬运面接触，故会损伤电极51D的背面。由于在带有该损伤的状态下直接构成电极，故存在因之后的加热等而在电极51D自身产生裂纹的问题或在向母板进行焊接时使焊剂浸润性降低的问题。
在进行传递模模装时，也会产生挠性板50及铜箔图案51与绝缘树脂的粘接性能变弱，不能实现充分密封结构的问题。
本发明的发明者为了解决上述问题，提出了使用层积板的提案，该层积板是介由第三导电膜使薄的第一导电膜和厚的第二导电膜层积的层积板。
本发明的第一方面提供一种电路装置的制造方法，其特征在于，包括下述工序：准备在第三导电膜的两面上层积薄的第一导电膜和厚的第二导电膜而构成的层积板；通过将所述第一导电膜蚀刻为所希望的图案，形成微细的导电图案层；将所述导电图案层用作掩模除去所述第三导电膜，形成所述第三导电膜比所述导电图案层凹入内侧的锚固部；介由绝缘粘接层将半导体元件固定在所述导电图案层上，将所述绝缘粘接层填充在所述锚固部；将所述半导体元件的电极和规定的所述导电图案层电连接；用密封树脂层覆盖所述半导体元件，将所述密封树脂层填充在所述锚固部；除去所述第二导电膜，使所述密封树脂层及所述第三导电膜在背面露出。尤其是在以所示导电图案层为掩模除去第三导电膜形成锚固部并使其具有密封树脂层的锚固效果这一点上具有特征。
本发明第二方面的特征在于，蚀刻所述第一导电膜时，将所述第三导电膜用作蚀刻的阻挡层。
本发明第三方面的特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
本发明第四方面的特征在于，以形成所述导电图案时的抗蚀剂为掩模，超量蚀刻所述第三导电膜形成所述锚固部。
本发明第五方面的特征在于，进行所述蚀刻的溶液是碘系溶液。
本发明第六方面的特征在于，以形成所述导电图案时的抗蚀剂为掩模，电解剥离所述第三导电膜，并超量剥离形成所述锚固部。
本发明第七方面的特征在于，整面蚀刻所述第二导电膜，使剩余的所述第三导电膜及所述锚固部的所述密封树脂层露出。
本发明第八方面的特征在于，将焊剂附着在剩余的所述第三导电膜上，在背面形成球状的外部电极。
本发明第九方面提供一种电路装置的制造方法，其特征在于，包括下述工序：准备在第三导电膜的两面上层积薄的第一导电膜和厚的第二导电膜而构成的层积板；在所述第一导电膜上选择性形成由第四导电膜构成的焊盘；通过将所述第一导电膜蚀刻为所希望的图案，形成微细的导电图案层；将所述导电图案层用作掩模除去所述第三导电膜，形成所述第三导电膜比所述导电图案层凹入内侧的锚固部；介由绝缘粘接层将半导体元件固定在所述导电图案层上，将所述绝缘粘接层填充在所述锚固部；将所述半导体元件的电极和规定的所述导电图案层的所述焊盘电连接；用密封树脂层覆盖所述半导体元件，将所述密封树脂层填充在所述锚固部；除去所述第二导电膜，使所述密封树脂层及所述第三导电膜在背面露出。尤其是在在所述导电图案层上选择性设置焊盘和外部电极这一点上具有特征。
本发明第十方面的特征在于，蚀刻所述第一导电膜时，将所述第三导电膜用作蚀刻的阻挡层。
本发明第十一方面的特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
本发明第十二方面的特征在于，以形成所述导电图案时的抗蚀剂为掩模，超量蚀刻所述第三导电膜形成所述锚固部。
本发明第十三方面的特征在于，进行所述蚀刻的溶液是碘系溶液。
本发明第十四方面的特征在于，以形成所述导电图案时的抗蚀剂为掩模，电解剥离所述第三导电膜，并超量剥离形成所述锚固部。
本发明第十五方面的特征在于，整面蚀刻所述第二导电膜，使剩余的所述第三导电膜及所述锚固部的所述密封树脂层露出。
本发明第十六方面的特征在于，将焊剂附着在剩余的所述第三导电膜上，在背面形成球状外部电极。
附图说明
图1是说明本发明电路装置制造方法的剖面图；
图2是说明本发明电路装置制造方法的剖面图；
图3是说明本发明电路装置制造方法的剖面图；
图4是说明本发明电路装置制造方法的剖面图；
图5是说明本发明电路装置制造方法的剖面图；
图6是说明本发明电路装置制造方法的剖面图；
图7是说明本发明电路装置制造方法的剖面图；
图8是说明本发明电路装置制造方法的剖面图；
图9是说明本发明电路装置制造方法的剖面图；
图10是说明本发明电路装置制造方法的剖面图；
图11是说明本发明电路装置制造方法的剖面图；
图12是说明本发明电路装置制造方法的剖面图；
图13是说明本发明电路装置制造方法的剖面图；
图14是说明本发明电路装置制造方法的剖面图；
图15是说明由本发明制造的电路装置的平面图；
图16是说明现有半导体装置制造方法的图；
图17是说明现有半导体装置制造方法的图；
图18是说明现有半导体装置制造方法的图；
图19是说明现有挠性板的图。
具体实施方式
本发明的电路装置的制造方法包括下述工序：准备介由第三导电膜13层积薄的第一导电膜11和厚的第二导电膜12构成的层积板10；在所述第一导电膜11上选择性形成由第四导电膜14构成的焊盘14A；通过将所述第一导电膜11蚀刻为所希望的图案，形成微细的导电图案层11A；将所述导电图案层11A用作掩模除去所述第三导电膜13，形成所述第三导电膜13比所述导电图案层11A凹入内侧的锚固部15；介由绝缘粘接层将半导体元件19固定在所述导电图案层11A上，将所述绝缘粘接层填充在所述锚固部15，将所述半导体元件19的电极和规定的所述导电图案层11A的所述焊盘14A电连接；用密封树脂层22覆盖所述半导体元件19，将所述密封树脂层22填充在所述锚固部15；除去所述第二导电膜12，使所述密封树脂层22及所述第三导电膜13在背面露出。下面说明上述各工序。
如图1所示，本发明的第一工序是准备介由第三导电膜13层积薄的第一导电膜11和厚的第二导电膜12构成的层积板10。
层积板10的表面实质上在整个区域形成第一导电膜11，介由第三导电膜13，在背面实质上在整个区域形成第二导电膜12。第一导电膜11及第二导电膜12理想的是由以铜为主材的材料或公知的引线架材料构成。第一导电膜11、第二导电膜12及第三导电膜13可由镀敷法、蒸镀法或溅射法形成，或粘贴由压延法或镀敷法形成的金属箔。另外，作为第一导电膜11及第二导电膜12也可以是铝、铁、铁镍合金及公知的引线架材料等。
第三导电膜13的材料采用不被除去第一导电膜11及第二导电膜12时使用的蚀刻液蚀刻的材料。另外，由于在第三导电膜背面形成由焊锡等构成的外部电极24，故也要考虑外部电极24的粘接性能。具体地说，作为第三导电膜13的材料可采用由金、银、钯构成的导电材料。
第一导电膜的厚度为了形成微细的图案而形成得很薄，其厚度为5～35μm左右。第二导电图案由于要机械支承整体，故形成得较厚，其厚度是35～150μm左右。第三导电膜13在蚀刻第一导电膜11及第二导电膜12时起阻挡层的作用，其厚度是2～10μm左右。
因此，通过较厚地形成第二导电膜12，可维持层积板10的平坦性，可提高后道工序的操作性。
另外，第二导电膜12由于要经过各个工序，故会产生损伤。但是由于厚的第二导电膜12要在后道工序除去，故可防止作为成品的电路装置产生损伤。由于可维持平坦性并硬化密封树脂，故也可使封装的背面平坦，形成于层积板10背面的外部电极也可平整地配置。因此，可使安装衬底上的电极和层积板10背面的电极接触，可防止焊剂缺陷。
下面说明上述层积板10的具体制造方法。层积板10可通过电镀进行的层积或压延接合进行制造。在由电镀制造层积板10时，首先要准备第二导电膜12。然后，在第二导电膜12的背面设置电极，利用电镀法层积第三导电膜。之后，同样利用电镀法在第三导电膜上层积第一导电膜。在利用压延制造层积板时，用压辊等施加压力接合准备成板状的第一导电膜11、第二导电膜12及第三导电膜13。
如图2～图4所示，本发明的第二工序在于，在第一导电膜11上选择性形成由第四导电膜14构成的焊盘14A。
在本工序中，如图2所示，利用电镀在第一导电膜11上整面形成第四导电膜14。作为第四导电膜为了和第一导电膜在蚀刻上具有选择性，适用银镀敷，然后形成固定接合引线的焊盘。然后，用光致抗蚀剂PR覆盖第四导电膜14上的预定构成焊盘的区域。
接着，如图3所示，以光致抗蚀剂PR为掩模，用碘系溶液蚀刻露出的第四导电膜14，形成焊盘14A。此时，由于第一导电膜11用铜形成，故不会被碘系溶液蚀刻。
然后，如图4所示，除去光致抗蚀剂PR，露出焊盘14A。
另外，作为焊盘14A的形成方法可以是：使预定的焊盘区域露出，将剩余部分用光致抗蚀剂覆盖，对预定的焊盘区域选择性进行金镀敷或银镀敷等形成焊盘的方法。
如图5及图6所示，本发明的第三工序在于，通过将所述第一导电膜11蚀刻为所希望的图案，形成导电图案层11A。
用所希望的图案的光致抗蚀剂PR覆盖在第一导电膜11上，利用化学蚀刻形成形成配线的导电图案层11A。由于第一导电膜11是以铜为主材的，故蚀刻液使用氯化铁或氯化铜即可。由于蚀刻第一导电膜11，第三导电膜13也会和蚀刻液接触，但是由于第三导电膜13的材料是不会被氯化铁或氯化铜蚀刻的材料，故蚀刻在第三导电膜13的表面停止。这样，第一导电膜11形成5～35μm左右的厚度，因此，导电图案层11A可形成50μm以下的精细图案。另外，第二导电膜12的背面由光致抗蚀剂PR或罩膜覆盖，防止在进行导电图案层11A的化学蚀刻时受蚀刻液影响。
本工序的特征在于，蚀刻第一导电膜11时由第三导电膜13使蚀刻停止。由此，第一导电膜11的蚀刻可整片进行，故具有可实现稳定的蚀刻的优点。在本工序中，被蚀刻的第一导电膜11主要由铜构成，作为选择性除去铜的蚀刻液使用氯化铁或氯化铜。与此相对，第三导电膜13由不会被氯化铁及氯化铜蚀刻的导电性材料形成，故蚀刻在第三导电膜13的表面停止。第三导电膜13的材料可采用金、银及钯。
如图7及图8所示，本发明的第四工序在于，将导电图案层11A作为掩模使用，除去第三导电膜13，形成第三导电膜13凹入导电图案层11A内的锚固部15。
将在前工序中形成的第一导电膜11构成的导电图案层11A用作掩模，选择性除去第三导电膜13。作为选择性除去第三导电膜13的方法可采用两种方法。第一种方法是用仅除去第三导电膜13的液体进行蚀刻的方法。第二种方法是利用电解剥离仅除去第三导电膜13的方法。
下面说明利用第一种方法的蚀刻局部除去第三导电膜13的方法。该方法中使用的蚀刻液使用蚀刻第三导电膜13且不会蚀刻导电图案层11A及第二导电膜12的蚀刻液。例如，在导电图案层11A及第二导电膜12主要由铜形成且第三导电膜13由银膜形成的情况下，可通过使用碘系蚀刻液仅除去第三导电膜13。通过蚀刻第三导电膜13第二导电膜12虽然会与碘系蚀刻液接触，但是，例如由铜构成的第二导电膜12不会被碘系蚀刻液蚀刻。因此，这里的蚀刻在第二导电膜12的表面停止。在进行该蚀刻时，通过进行超量蚀刻，第三导电膜13被超量蚀刻，而自导电图案层11A的周端凹入内侧，形成凹入的锚固部15。
下面说明利用第二种方法即电解剥离仅除去第三导电膜13的方法。首先，使包含金属离子的溶液与第三导电膜13接触。然后，在溶液侧设置正电极，在层积板10设置负电极，接通直流电流。这样，利用和利用电场法形成镀膜相反的原理仅除去第三导电膜13。这里使用的溶液是用于镀敷处理构成第三导电膜13的材料时使用的溶液。因此，该方法仅剥离第三导电膜13。在进行该电解剥离时进行超量剥离使第三导电膜13超量剥离而自导电图案层11A的周端凹入内侧，形成凹的锚固部15。
本工序的特征在于，通过该超量蚀刻或超量剥离有意地形成锚固部15。由于锚固部15以导电图案层11为掩模而形成，故通过自调节效应以均匀的凹入量形成于导电图案层11A的周边。
如图9所示，本发明的第五工序在于，通过绝缘粘接层16将半导体元件19固定在导电图案层11A上，将半导体元件19的电极和规定的导电图案层11A的焊盘14A电连接。
将绝缘板粘接在预先形成半导体元件19的晶片的背面，将其粘接在晶片切割板上，将晶片和绝缘板一起切割，形成在半导体元件19表面具有绝缘粘接层16的小片。
上述绝缘板可利用真空压制或叠片方法进行。真空压制法是将由热硬性树脂构成的粘合材料板重叠并真空压制的方法。叠片法是对半导体晶片一张张地使用辊涂敷热硬性树脂或感光性树脂板。该方法中，虽然后固化工序要利用成批处理在另一工序进行，但是具有可高精度控制厚度的优点。
半导体元件19以裸片状态使绝缘粘接层16与导电图案层11A接触并接合。此时，绝缘粘接层16被加热熔融可填充在形成于导电图案层11A的锚固部15，实现牢固的粘接。
半导体元件19的各电极焊盘用接合引线20与设于周边的导电图案层11A的规定部位的焊盘14A连接。半导体元件19也可以面朝下安装。这种情况下，要在半导体元件19的各电极焊盘表面设置焊球或补片，在层积板10的表面，在与焊球位置对应的部分设置与由导电图案层11A构成的焊盘同样的电极。
下面说明进行引线接合时使用层积板10的优点。通常，在进行金线的引线接合时，要加热到200℃～300℃。此时，若第二导电膜12很薄，层积板10就会挠曲，当在该状态下，通过焊接头对层积板10加压时，就有可能使层积板10损伤。但是，通过较厚地形成第二导电膜12自身，可以解决这些问题。
如图10所示，本发明的第六工序在于，用密封树脂层22覆盖半导体元件19，并向锚固部15填充密封树脂层22。
层积板10被设置在模装装置上进行树脂模装。模装方法可使用传递模模装、注射模模装、涂敷、罐封等进行。但是考虑到批量生产，则适用传递模模装、注射模模装。
在本工序中具有下述优点，在用密封树脂层22进行模装时，要将密封树脂层22填充到形成于第二导电膜12表面的第三导电膜13的凹部形成的锚固部15，密封树脂层22和导电图案层11A的结合因锚固效应而更牢固。
在本工序中，层积板10必须平整地接触模腔的下模，厚的第二导电膜12起该作用。而且，自模腔取出后，直至密封树脂层22的收缩结束，也会由第二导电膜12维持封装的平坦性。也就是说，本工序之前层积板10的机械支承作用由第二导电膜12承担。
如图11所示，本发明的第七工序在于，除去第二导电膜12使密封树脂层22及第三导电膜13露出背面。
在本工序中，通过不用掩模进行蚀刻，将第二导电膜12整面除去。该蚀刻可以是使用氯化铁或氯化铜的化学蚀刻，第二导电膜12被整面除去。这样，通过整面除去第二导电膜12，使第三导电膜13自密封树脂层22露出。如上所述，第三导电膜13由在蚀刻第二导电膜12的溶液中不被蚀刻的材料形成，故在本工序中第三导电膜13不被蚀刻。
本工序的特征在于，在通过蚀刻除去第二导电膜12时，即使不用掩模第三导电膜13也会作为阻挡层起作用，并使密封树脂层22及第三导电膜13构成的背面平坦地形成。第二导电膜12由于通过蚀刻被整面除去，故在蚀刻的最终阶段，第三导电膜13也会接触蚀刻液。如上所述，第三导电膜13由下述材料构成，这种材料是不会被蚀刻由铜构成的第二导电膜12的氯化铁及氯化铜蚀刻的材料。因此，在第三导电膜13的下面蚀刻停止，故第三导电膜13具有作为蚀刻的阻挡层的功能。另外，在本工序之后，整体由密封树脂层22机械支承。
如图12～图14所示，本发明的最终工序在于形成焊球阵列(Ball GridArrey)结构。
在焊球阵列结构的情况下，第三导电膜13使形成外部电极24的部分露出，对由溶剂溶解的环氧树脂等进行网印，用外敷树脂23覆盖大部分。然后，如图13所示，利用乳酪焊剂的网印及焊剂的回流在该露出部分形成外部电极24。接着，如图14所示，在层积板10矩阵状形成多个电路装置，切割密封树脂层22及外敷树脂23，将它们分离为一个个电路装置。
在本工序中，由于可通过切割密封树脂层22及外敷树脂23，分离为一个个电路装置，故可减少进行切割的切割机的磨损。
参照图15说明具化的本发明的制造方法制造的电路装置。虚线所示的图案是导电配线层11A。围绕半导体元件19设置由导电配线层11A构成的接合焊盘，在半导体元件19的下方对应的区域设置由导电配线层11A构成的焊盘。由此，可知可在半导体元件19下方的区域也形成由导电配线层11A构成的图案。导电配线层11A可形成微细图案，可形成更多的外部电极24。
如果是这种结构，即使是具有200以上的焊盘的半导体元件19，也可利用导电配线层11A的微细图案形成微细化的所希望的导电图案，故可自外部电极24向外部电路进行连接。
根据本发明，通过在形成导电图案层的工序中，作为阻挡层设置第三导电膜13，可整面蚀刻第一导电膜，故具有可容易地进行导电图案层的蚀刻并且不会不必要地蚀刻其他导电膜的优点。
通过以导电图案层为掩模超量蚀刻或超量剥离第三导电膜，可由凹入导电图案层周围的第三导电膜自调节形成锚固部，并在其后由密封树脂层覆盖时，充填该锚固部，故密封树脂层及绝缘粘接层和导电图案层的咬合更加牢固，具有可实现良好的密封状态的优点。
并且，第三导电膜在整面除去第二导电膜时与密封树脂层一起作为蚀刻阻挡层起作用，故具有可无掩模地除去第二导电膜的优点。

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1、一种电路装置的制造方法，其特征在于，包括下述工序：准备在第三导电膜的两面上层积薄的第一导电膜和厚的第二导电膜而构成的层积板；通过将所述第一导电膜蚀刻为所希望的图案，形成微细的导电图案层；将所述导电图案层用作掩模除去所述第三导电膜，形成所述第三导电膜比所述导电图案层凹入内侧的锚固部；介由绝缘粘接层将半导体元件固定在所述导电图案层上，将所述绝缘粘接层填充在所述锚固部；将所述半导体元件的电极和规定的所述导电图案层电连接；用密封树脂层覆盖所述半导体元件，将所述密封树脂层填充在所述锚固部；除去所述第二导电膜，使所述密封树脂层及所述第三导电膜在背面露出。
2、如权利要求1所述的电路装置的制造方法，其特征在于，蚀刻所述第一导电膜时，将所述第三导电膜用作蚀刻的阻挡层。
3、如权利要求2所述的电路装置的制造方法，其特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
4、如权利要求1所述的电路装置的制造方法，其特征在于，以形成所述导电图案时的抗蚀剂为掩模，超量蚀刻所述第三导电膜形成所述锚固部。
5、如权利要求4所述的电路装置的制造方法，其特征在于，进行所述蚀刻的溶液是碘系溶液。
6、如权利要求1所述的电路装置的制造方法，其特征在于，以形成所述导电图案时的抗蚀剂为掩模，电解剥离所述第三导电膜，并超量剥离形成所述锚固部。
7、如权利要求1所述的电路装置的制造方法，其特征在于，整面蚀刻所述第二导电膜，使剩余的所述第三导电膜及所述锚固部的所述密封树脂层露出。
8、如权利要求7所述的电路装置的制造方法，其特征在于，将焊剂附着在剩余的所述第三导电膜上形成外部电极。
9、一种电路装置的制造方法，其特征在于，包括下述工序：准备在第三导电膜的两面上层积薄的第一导电膜和厚的第二导电膜而构成的层积板；在所述第一导电膜上选择性形成由第四导电膜构成的焊盘；通过将所述第一导电膜蚀刻为所希望的图案，形成微细的导电图案层；将所述导电图案层用作掩模除去所述第三导电膜，形成所述第三导电膜比所述导电图案层凹入内侧的锚固部；介由绝缘粘接层将半导体元件固定在所述导电图案层上，将所述绝缘粘接层填充在所述锚固部；将所述半导体元件的电极和规定的所述导电图案层的所述焊盘电连接；用密封树脂层覆盖所述半导体元件，将所述密封树脂层填充在所述锚固部；除去所述第二导电膜，使所述密封树脂层及所述第三导电膜在背面露出。
10、如权利要求9所述的电路装置的制造方法，其特征在于，蚀刻所述第一导电膜时，将所述第三导电膜用作蚀刻的阻挡层。
11、如权利要求10所述的电路装置的制造方法，其特征在于，作为进行所述蚀刻的溶液使用包含氯化铜或氯化铁的溶液。
12、如权利要求9所述的电路装置的制造方法，其特征在于，以形成所述导电图案时的抗蚀剂为掩模，超量蚀刻所述第三导电膜形成所述锚固部。
13、如权利要求12所述的电路装置的制造方法，其特征在于，进行所述蚀刻的溶液是碘系溶液。
14、如权利要求9所述的电路装置的制造方法，其特征在于，以形成所述导电图案时的抗蚀剂为掩模，电解剥离所述第三导电膜，并超量剥离形成所述锚固部。
15、如权利要求9所述的电路装置的制造方法，其特征在于，整面蚀刻所述第二导电膜，使剩余的所述第三导电膜及所述锚固部的所述密封树脂层露出。
16、如权利要求15所述的电路装置的制造方法，其特征在于，将焊剂附着在剩余的所述第三导电膜上形成外部电极。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4052915B2 (ja) * 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP2004119729A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4086607B2 (ja) 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP4115228B2 (ja) * 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法
US7119685B2 (en) * 2004-02-23 2006-10-10 Checkpoint Systems, Inc. Method for aligning capacitor plates in a security tag and a capacitor formed thereby
US7116227B2 (en) * 2004-02-23 2006-10-03 Checkpoint Systems, Inc. Tag having patterned circuit elements and a process for making same
JP2007109914A (ja) * 2005-10-14 2007-04-26 Sony Corp 半導体装置の製造方法
US7825514B2 (en) * 2007-12-11 2010-11-02 Dai Nippon Printing Co., Ltd. Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device
US20100075495A1 (en) * 2008-09-25 2010-03-25 Chien-Wei Chang Method Of Selectively Plating Without Plating Lines
US7830024B2 (en) * 2008-10-02 2010-11-09 Advanced Semiconductor Engineering, Inc. Package and fabricating method thereof
TWI421993B (zh) * 2010-04-27 2014-01-01 Aptos Technology Inc 四方扁平無導腳之半導體封裝件及其製法及用於製造該半導體封裝件之金屬板
US9177832B2 (en) * 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
CN103311216B (zh) * 2013-05-20 2016-02-24 江苏长电科技股份有限公司 高密度多层线路芯片倒装封装结构及制作方法
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
TWI647989B (zh) * 2018-01-31 2019-01-11 嘉聯益科技股份有限公司 卷對卷柔性線路板及其快速加工方法
CN111224019B (zh) * 2018-11-23 2023-05-02 Tgo科技株式会社 掩模支撑模板和其制造方法及掩模与框架连接体的制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258649A (en) * 1989-05-20 1993-11-02 Hitachi, Ltd. Semiconductor device and electronic apparatus using semiconductor device
SG52916A1 (en) * 1996-02-13 1998-09-28 Nitto Denko Corp Circuit substrate circuit-formed suspension substrate and production method thereof
EP0844663B1 (en) * 1996-05-27 2006-03-29 Dai Nippon Printing Co., Ltd. Method for manufacturing a circuit member for a semiconductor device
JP2004119726A (ja) * 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP2004119729A (ja) 2002-09-26 2004-04-15 Sanyo Electric Co Ltd 回路装置の製造方法
JP4086607B2 (ja) 2002-09-26 2008-05-14 三洋電機株式会社 回路装置の製造方法
JP4052915B2 (ja) 2002-09-26 2008-02-27 三洋電機株式会社 回路装置の製造方法
JP4115228B2 (ja) 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法

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KR100658023B1 (ko) 2006-12-15
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US7030033B2 (en) 2006-04-18

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