CN1835222A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1835222A
CN1835222A CNA2006100586776A CN200610058677A CN1835222A CN 1835222 A CN1835222 A CN 1835222A CN A2006100586776 A CNA2006100586776 A CN A2006100586776A CN 200610058677 A CN200610058677 A CN 200610058677A CN 1835222 A CN1835222 A CN 1835222A
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Prior art keywords
semiconductor chip
printed wiring
wiring board
type surface
resist film
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CNA2006100586776A
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CN100568498C (zh
Inventor
岛贯好彦
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Renesas Electronics Corp
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Renesas Technology Corp
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Abstract

本发明提高了半导体器件的可靠性。该半导体器件包括封装衬底、半导体芯片、导线、芯片键合膜、多个焊接凸点和密封体，其中封装衬底具有干型抗蚀剂膜，其覆盖了形成在主表面和背表面上的多个导体部分中的一些导体部分且由膜形成；半导体芯片安装在封装衬底上方；导线电连接半导体芯片和封装衬底；芯片键合膜布置在封装衬底的主表面和半导体芯片之间；多个焊接凸点形成在封装衬底的背表面上；以及密封体由树脂制成。通过在封装衬底的主表面和背表面上形成由膜制成的干型抗蚀剂膜，可以抑制封装衬底的翘曲，并因此可以防止在回流安装时出现封装裂缝，从而提高半导体器件的可靠性。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2005年3月18日提交的日本专利申请No.2005-078581的优先权，据此将其内容通过参考引入本申请。
技术领域
本发明涉及一种半导体制造技术，并且更特别地涉及一种可有效应用于提高半导体器件可靠性的技术。
背景技术
在通过粘合材料把半导体芯片固定在印制线路板上的半导体器件中，把从中去除绝缘膜的沟槽提供在半导体芯片和在印制线路板主表面上的电极之间，并因此，粘合材料的流出部分留在沟槽内部并且不到达印制线路板主表面上的电极。通过去除在整个深度区域上方的绝缘膜而形成沟槽(见，例如日本未审专利公开2003-92374(图1)(专利文献1))。
通常，把湿型抗蚀剂膜形成在印制线路板的前表面和背表面上。湿型抗蚀剂膜具有流动性，并通过涂覆(coat)来形成，因此，难以形成具有均匀膜厚度的膜。即，在湿型抗蚀剂膜中，膜厚度变得不均匀或不规则，并因此，印制线路板翘曲。另外，由于通过涂覆形成湿型抗蚀剂膜，所以外来物质(废弃的丝屑)等易于轻易地缠上，并且这种纠缠物会引起印制线路板的误操作。
作为对付印制线路板翘曲的一种对策，已提出这样的方法，其中使形成在印制线路板前表面和背表面上的铜布线的比例尽可能地相等，由此抑制在最初状态中的翘曲。然而，在存在有对半导体器件的小型化和厚度减小的强烈需求的同时，关于在印制线路板上的铜布线，存在有诸如铜布线布置(pull-around)的许多限制，并因此难以使形成在印制线路板前表面和背表面上的铜布线的比例相等。因此难以使用这种方法抑制翘曲。
这里，当印制线路板翘曲为U形时，出现这样的缺点，即在回流安装时，例如在装配半导体器件后安装半导体器件时，在半导体芯片的下部中生成空隙并且出现封装裂缝。
此外，当印制线路板以倒U形翘曲时，出现这样的缺点，即在芯片和在芯片外围上的衬底之间发生脱离。
此外，当印制线路板翘曲时，在执行引线键合时生成的超声波不能正常传送到印制线路板，因此发生了误键合的缺点。
此外，当印制线路板翘曲时，该翘曲也会引起传送系统上的问题。
更进一步，关于湿型抗蚀剂膜，其膜厚度变得不规则并因此形成不平坦的表面，所以难以把膜状的芯片键合材料用作芯片键合材料。即芯片键合膜无法与湿型抗蚀剂膜的不平坦表面顺形，因此在湿型抗蚀剂膜的凹入部分和芯片键合膜之间出现空隙并由此导致了封装裂缝。
因此，虽然湿型抗蚀剂膜采用糊状(paste)材料作为芯片键合材料，但在使用糊状材料中，需要防止由糊状材料从半导体芯片泄漏引起的对印制线路板键合端子的污染。因此，从半导体芯片的端部到印制线路板的端部需要确保足够的距离。结果，对于印制线路板，必须确保半导体芯片外侧区域足够的面积，这样产生了不可能实现半导体器件小型化的缺点。
发明内容
因此，本发明的一个目的是提供一种能提高半导体器件可靠性的技术。
本发明的另一个目的是提供一种能提高半导体器件质量的技术。
本发明的又一个目的是提供一种能使半导体器件小型化的技术。
从对本说明书和附图的描述，本发明的上述和其他目的及新颖特征将变得显而易见。
简要地说明在本说明书中公开的发明中的代表性发明的概述如下。
即，本发明公开了一种半导体器件，其包括：印制线路板、半导体芯片和芯片键合膜，该印制线路板具有主表面、以相对方式面向主表面的背表面、形成在主表面和背表面上的多个导体部分以及干型抗蚀剂膜，该干型抗蚀剂膜形成在主表面和背表面上，覆盖该多个导体部分中的一些导体部分并由膜形成；该半导体芯片安装在印制线路板的主表面上；以及该芯片键合膜布置在印制线路板的主表面与半导体芯片之间，其中半导体芯片通过芯片键合膜被固定到印制线路板的主表面上的干型抗蚀剂膜。
此外，本发明公开了一种半导体制造方法，该方法包括下列步骤：制备印制线路板，其具有主表面、以相对方式面向主表面的背表面、形成在主表面和背表面上的多个导体部分以及干型抗蚀剂膜，该干型抗蚀剂膜形成在主表面和背表面上，覆盖多个导体部分中的一些导体部分并由膜形成；通过芯片键合膜把半导体芯片连接到印制线路板的主表面；电连接半导体芯片和印制线路板；以及密封半导体芯片，其中通过芯片键合膜把半导体芯片固定到印制线路板主表面上的干型抗蚀剂膜。
以下是通过本说明书中公开的发明中的代表性发明所获得的有益效果的简要描述。
通过把由膜形成的干型抗蚀剂膜形成在印制线路板的主表面和背表面上，使干型抗蚀剂膜变平，并因此可以抑制印制线路板的翘曲。结果，可以防止在芯片之下形成空隙，并因此能防止在回流安装时出现封装裂缝。从而，可以提高半导体器件的可靠性和质量。此外，通过把由膜形成的干型抗蚀剂膜形成在印制线路板的主表面和背表面上，可以使主表面和背表面变平，并因此可以通过芯片键合膜把半导体芯片固定到半导体器件的印制线路板上的干型抗蚀剂膜。从而，无需考虑糊状材料从半导体芯片的流出，并因此，可以使从半导体芯片的端部到印制线路板的端部的距离尽可能地短，从而实现半导体器件的小型化。
附图说明
图1是表示以透视方式透过密封体观察到的根据本发明第一实施例的半导体器件的结构的一个例子的平面图；
图2是表示图1中所示半导体器件的结构的一个例子的截面图；
图3是表示图2中所示部分A的结构的局部放大截面图；
图4是表示装配在图1中所示半导体器件中的印制线路板的结构的一个例子的截面图；
图5是表示图4中所示部分A的结构的局部放大截面图；
图6是表示在图4中所示的印制线路板的前表面侧上的布线图形的一个例子的平面图；
图7是表示在图4中所示的印制线路板的背表面侧上的布线图形的一个例子的背表面视图；
图8是表示在图4中所示印制线路板中的干型抗蚀剂膜的形成方法的一个例子的制造工艺流程图；
图9是表示在图1中所示半导体器件的装配中树脂模制之前的装配的一个例子的制造工艺流程图；
图10是表示在图1中所示半导体器件的装配中树脂模制之后的装配的一个例子的制造工艺流程图；
图11是根据本发明第一实施例的半导体器件的变型结构的截面图；
图12是表示图11中所示部分A的结构的局部放大截面图；
图13是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的结构的一个例子的平面图；
图14是表示图13中所示半导体器件结构的一个例子的截面图；
图15是沿着图13中的A-A线获得的结构的局部放大截面图；
图16是沿着图13中的B-B线获得的结构的局部放大截面图；
图17是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的变型结构的平面图；
图18是表示图17中所示半导体器件结构的一个例子的截面图；
图19是沿着图17中的A-A线获得的结构的局部放大截面图；
图20是沿着图17中的B-B线获得的结构的局部放大截面图；
图21是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的一个变型结构的平面图；
图22是表示图21中所示半导体器件结构的一个例子的截面图；
图23是沿着图22中所示部分A获得的结构的局部放大截面图；和
图24是表示在图1中所示半导体器件的装配中树脂模制之后的装配的一种变型的制造工艺流程图。
具体实施方式
在以下将说明的实施例中，除非另外说明，否则原则上不重复对相同部分或相似部分的说明。
此外，在以下描述的实施例中，为了方便起见，将通过把本发明分成多个部分或实施例来说明本发明。但是，除非另有明确的描述，否则这些部分或实施例彼此相关，它们之间存在这样的关系，即一个部分或实施例是其他部分或实施例的一部分或全部的变型、细节和补充说明。
此外，在以下描述的实施例中，当涉及元件数目等(包括片数、数值、数量、范围等)时，除非另外特别说明或者原则上该数目明显限于指定数目，否则该数目并不限于指定数目，并且可以设定为大于或小于指定数目的值。
结合附图，详细说明本发明的实施例。这里，在所有用于说明实施例的附图中，对具有相同功能的元件给予相同的符号，并省略对元件的重复说明。
(第一实施例)
图1是表示以透视方式透过密封体观察到的根据本发明第一实施例的半导体器件的结构的一个例子的平面图，图2是表示图1中所示半导体器件的结构的一个例子的截面图，图3是表示图2中所示部分A的结构的局部放大截面图；图4是表示装配在图1中所示半导体器件中的印制线路板的结构的一个例子的截面图，图5是表示图4中所示部分A的结构的局部放大截面图，图6是表示在图4中所示的印制线路板的前表面侧上的布线图形的一个例子的平面图，图7是表示在图4中所示的印制线路板的背表面侧上的布线图形的一个例子的背表面视图，图8是表示在图4中所示的印制线路板中的干型抗蚀剂膜的形成方法的一个例子的制造工艺流程图，图9是表示在图1中所示半导体器件的装配中树脂模制之前的装配的一个例子的制造工艺流程图，图10是表示在树脂模制之后的装配的一个例子的制造工艺流程图，图11是根据本发明第一实施例的半导体器件的变型结构的截面图，以及图12是表示图11中所示部分A的结构的局部放大截面图。
根据第一实施例的半导体器件是树脂模制型小尺寸半导体封装，其中把半导体芯片1安装在印制线路板上。在第一实施例中，把在图1至图3中所示的CSP(芯片级封装)7作为一个例子来说明。
此处，在CSP 7中，把构成多个外部端子的焊接凸点8以格栅阵列形式布置在印制线路板的背表面3b上。因而，CSP 7是BGA(球栅阵列)型半导体封装。
结合图1至图3来说明CSP 7的结构，CSP 7包括封装衬底3、半导体芯片1、导线4、芯片键合膜2、焊接凸点8以及密封体6，其中封装衬底3由印制线路板构成，该印制线路板具有主表面3a、与主表面3a相对布置的背表面3b、形成在主表面3a和背表面3b上的多个导体部分、以及干型抗蚀剂膜3f，该干型抗蚀剂膜3f形成在主表面3a和背表面3b上，覆盖上述多个导体部分中的一些并且也由膜制成；半导体芯片1安装在封装衬底3的主表面3a上并且包括集成电路；导线4将构成半导体芯片1的电极的焊盘1c与封装衬底3的键合电极3h电连接；芯片键合膜2构成布置在封装衬底3的主表面3a与半导体芯片1(预先粘贴到半导体芯片1的背表面侧)之间的芯片键合材料；焊接凸点8构成多个外部端子，形成在封装衬底3的背表面3b上的多个连接盘(land)3d上；以及密封体6使用树脂密封半导体芯片1和多个导线4。通过芯片键合膜2，把半导体芯片1固定到形成在封装衬底3上的主表面3a的干型抗蚀剂膜3f。
CSP 7是小尺寸半导体封装，其中半导体芯片1的尺寸和封装衬底3的尺寸基本相等，即，封装衬底3的尺寸略大于半导体芯片1的尺寸。例如，在半导体芯片1的端部和封装衬底3的端部之间的距离大约为300μm。
因此，在CSP 7中，如图1至图3中所示，把多个键合电极3h布置在封装衬底3中芯片外侧区域中和衬底的外围部分上，其中使用导线4，把构成形成在半导体芯片1的主表面1a上的电极的焊盘1c与形成在封装衬底3上的相应的键合电极3h彼此电连接。
这里，说明装配到CSP 7中的、图4和图5中所示的封装衬底3的结构。
封装衬底3包括内层芯板(core material)3c、形成在内层芯板3c的主表面3a和背表面3b上的多个导体部分、连接主表面3a的导体部分与背表面3b的导体部分的通孔3e、以及至少覆盖上述一些导体部分的干型抗蚀剂膜3f。如图6中所示，在衬底的外围部分中，沿着构成封装衬底3的前表面的主表面3a上的相应侧，把多个键合电极3h布置成行。
此外，分别经由通孔3e和铜布线3g电连接键合电极3h。
另一方面，在封装衬底3的背表面3b上，如图7中所示，以格栅阵列布置多个连接盘3d，并把构成外部端子的焊接凸点8与连接盘3d连接。此外，多个连接盘3d分别与通孔3e连接。
以这种方式，在封装衬底3的主表面3a和背表面3b上，形成诸如键合电极3h、铜布线3g、连接盘3d和通孔3e的导体部分。例如，这些导体部分由铜合金(Cu)形成。此外，为了提高多个连接盘3d和键合电极3h与导线4的连接强度，对铜合金施加例如Ni/Au电镀或Ni/Pd/Au电镀的表面处理。使用这种表面处理形成的电镀层的总厚度大约为10μm。
这里，在封装衬底3的主表面3a和背表面3b上，如图5中所示，形成干型抗蚀剂膜3f，构成由膜制成的阻焊膜(绝缘膜)。干型抗蚀剂膜3f覆盖除键合电极3h和连接盘3d以外的导体部分。这里，干型抗蚀剂膜3f的厚度例如约为25μm。即，和湿型抗蚀剂膜(其厚度例如约为55μm)相比，干型抗蚀剂膜3f较薄。
此外，与湿型抗蚀剂膜相比，干型抗蚀剂膜3f具有更为平坦或平整的表面。
这里结合图8说明形成封装衬底3中的干型抗蚀剂膜3f的方法。
首先，制备其上形成铜布线3g的内层芯板3c，并将膜状的干型抗蚀剂膜3f布置在内层芯板3c的前表面和背表面上。此后，使用真空层压方法执行真空吸附，从而将膜状的干型抗蚀剂膜3f压缩键合到内层芯板3c的前表面和背表面。这里，由于真空吸附，可以去除包含在干型抗蚀剂膜3f内部中的气泡。
此后，使用热压方法，通过压力机(press)21把热量和负载施加到膜状的干型抗蚀剂膜3f，从而使用热压缩键合把干型抗蚀剂膜3f牢固地固定到内层芯板3c。这里，由于通过具有平加压表面的压力机21对干型抗蚀剂膜3f施压，所以能使干型抗蚀剂膜3f的表面平坦或平整。
此后，冷却衬底从而完成平整的干型抗蚀剂膜3f的制造。
由于湿型抗蚀剂膜通过固化之前的涂覆来形成，所以沿着在衬底表面上形成的不规则性，形成抗蚀剂膜。因而，难以使湿型抗蚀剂膜的表面平整或平坦。
以这种方式，由于采用了干型抗蚀剂膜3f，装配到CSP 7的封装衬底3能使其表面平整或平坦。与湿型抗蚀剂膜相比，干型抗蚀剂膜3f在厚度上呈现出较小的不规则性，因此通过使用干型抗蚀剂膜3f，可以容易地控制厚度。结果，可以降低封装衬底3的翘曲。
此外，干型抗蚀剂膜3f可以在其总厚度小于湿型抗蚀剂膜的厚度的情况下形成，因此，可以实现封装衬底3的厚度的降低。
这里说明在干型抗蚀剂膜3f的形成期间的膜厚度和衬底翘曲方向。即，装配到第一实施例的CSP 7中的封装衬底3采用由膜制成的干型抗蚀剂膜3f，并因此可以控制抗蚀剂膜3f的膜厚度。通过使干型抗蚀剂膜3f的厚度在其前表面和后表面之间不同，可以进一步降低板的翘曲。
为了更加明确，考虑分别形成在衬底的前表面和背表面上的铜布线(导体部分)3g的布线密度，例如，当从铜布线3g的面积角度考虑布线密度时，设定形成在铜布线3g面积较小的表面上的干型抗蚀剂膜3f的厚度大于形成在相对表面上的干型抗蚀剂膜3f的厚度。
可选地，当从铜布线3g的长度角度考虑布线密度时，设定形成在铜布线3g长度较小的表面上的干型抗蚀剂膜3f的厚度大于形成在相对表面上的干型抗蚀剂膜3f的厚度。
以这种方式，通过改变与铜布线(导体部分)3g的布线密度(面积或长度)对应的在其前表面和背表面之间的干型抗蚀剂膜3f的厚度，可以控制封装衬底3的翘曲方向，并且同时还可以进一步降低翘曲。
此外，在第一实施例的CSP 7中，通过在封装衬底3中采用干型抗蚀剂膜3f，如图8中所示，可以使封装衬底3的表面平整或平坦。因而，如图3中所示，即使当芯片键合膜2用作牢固固定半导体芯片1的芯片键合材料，也不可能在封装衬底3的表面和芯片键合膜2之间形成间隙，并因此可以通过芯片键合膜2固定半导体芯片1。
这里，优选使用诸如切割胶带材料作为芯片键合膜2。将详细说明切割胶带材料，切割胶带材料具有包括芯部分和形成在芯部分上的粘合层(第一粘合层，UV粘合材料层)的双层结构。在第一实施例中，芯片键合膜2不限于这种结构。例如，切割胶带材料包括芯部分、形成在芯部分上的粘合层(第一粘合层，UV粘合材料层)、以及在第一粘合层顶部上的粘合层(第二粘合层，芯片键合粘合材料层)，其形成在之前的粘合层上并构成芯片键合膜2。这里例如，将在通过切割把半导体晶片切割成片时使用的切割胶带部件的粘合层留在晶片的背表面上，并把此粘合层用作芯片键合膜2。
因而，通过芯片键合膜2能把半导体芯片1牢固地固定到封装衬底3的主表面3a。
这里，半导体芯片1由例如硅等制成，并在其主表面1a上形成集成电路。此外，如图1中所示，把构成多个电极的焊盘1c形成在半导体芯片1的主表面1a的外围部分上。此外，导线4例如由金导线等形成，导线4电连接焊盘1c和布置在封装衬底3的主表面3a的外围部分上的键合电极3h。
另外，如图2和图3中所示，把半导体芯片1以这样的状态安装在封装衬底3上，其中通过芯片键合膜2，把半导体芯片1的背表面1b牢固地固定到封装衬底3，并且使半导体芯片1的主表面1a朝上。
另外，密封体6由例如热固性环氧树脂等制成，该密封体6使用树脂来密封半导体芯片1和导线4。
接着，结合图9和图10中所示的制造工艺流程图，说明根据第一实施例的CSP 7的制造方法。
首先，执行图9中所示步骤S1中的衬底的制备。这里制备了多腔衬底9，在该多腔衬底9上定义并布置用于形成多个封装衬底3的区域。这里，在其中形成封装衬底3的区域中，把铜布线3g和至少覆盖部分铜布线3g的干型抗蚀剂膜3f形成在多腔衬底9的前表面和背表面上。
然后，执行步骤S2中所示的芯片键合，使得如图3中所示通过芯片键合膜2牢固地把半导体芯片1固定到多腔衬底9。这里，芯片键合膜2由这样的芯片键合膜构成，其通过使在通过切割把半导体芯片分割成片时使用的芯片键合胶带部件的粘合层保留在晶片的背表面上而形成。
此后，执行在步骤S3中所示的引线键合。这里，如图1和图3中所示，使用诸如金导线等的导线4，电连接半导体芯片1的主表面1a上的焊盘1c和与其对应的多腔衬底9的封装衬底3的键合电极3h。
此后，执行步骤S4中所示的树脂模制。这里，在多腔衬底9上，以这样的状态执行树脂模制，其中用树脂成形模型20的一个腔20a共同地覆盖多腔衬底9上的多个区域(器件区域)，由此形成共同密封体5。这里，形成共同密封体5的密封树脂是例如热固性环氧树脂等。
此后，执行在图10中步骤S5所示的焊球安装(ball mounting)，使得如图3中所示把焊接凸点8连接到各自的连接盘3d。
此后，执行步骤S6中所示的标记。这里，使用激光标记方法等执行标记10，由此在共同密封体5上施加了标记。这里，可以使用例如油墨标记方法等来执行标记10。
此后，执行步骤S7中所示多腔衬底9的分割。这里，切割胶带12粘贴到共同密封体5的前表面，并在用切割胶带12固定共同密封体5的状态下，使用切割刀片11切割共同密封体5，由此把多腔衬底9分割成相应CSP 7。
从而，如在步骤S8中所示，通过执行CSP 7的装配，完成产品的制造。即，完成CSP 7的装配，在该CSP 7中通过芯片键合膜2把半导体芯片1固定到封装衬底3的主表面3a的干型抗蚀剂膜3f。
根据该第一实施例的半导体器件，由于把由膜构成的干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上，所以与湿型抗蚀剂膜相比，可以减少干型抗蚀剂膜3f的厚度的不规则性，并因此可以容易地控制抗蚀剂膜的厚度，从而限制封装衬底3的翘曲。
结果，可以防止在半导体芯片之下形成空隙，并因此可以防止在执行回流安装等时出现封装裂缝。
因而，能提高CSP 7的可靠性。
另外，由于能抑制封装衬底3的翘曲，所以也可以减少半导体芯片1在衬底外围从衬底的脱离、误键合以及在装配操作中传送CSP 7时出现的问题。
因而，可以提高CSP 7的质量。
此外，由于由膜制成的干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上，所以可以使主表面3a和背表面3b平整或平坦。从而，在CSP 7中，能通过芯片键合膜2把半导体芯片1固定到封装衬底3的主表面3a上的干型抗蚀剂膜3f。
因而，由于无需使用糊状材料作为芯片键合材料，更无需考虑糊状材料的泄漏，因此，可以将半导体芯片1的端部和封装衬底3的端部之间的距离设定得尽可能地短，由此实现CSP 7的小型化。
此外，与湿型抗蚀剂膜相比，通过在封装衬底3中采用干型抗蚀剂膜3f，可以提高为使键合电极3h更精确地暴而形成的开口部分的定位精确性。此外，由于在干型抗蚀剂膜3f中形成的上述开口部分中没有形成毛刺(burr)，所以可提高衬底的质量。
此外，在采用共同密封方法的CSP 7的装配中，该共同密封方法使用树脂共同密封多个器件区域，由于把干型抗蚀剂膜3f形成在封装衬底3上，所以可减小衬底的初始翘曲，并因此可以进一步扩大用于共同密封的多腔衬底9的尺寸，从而增加了能够在多腔衬底9中制造的CSP 7的数目。
此外，把由膜形成的干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上，并因此可以通过芯片键合膜2来固定半导体芯片1，由此可进一步减小器件区域的尺寸，从而实现CSP 7的进一步小型化。特别地，采用共同模制的CSP 7的装配能实现多腔衬底9的扩大，因此封装变得越小，该第一实施例就变得越有效。
接着，说明第一实施例的一个变型。
图11和图12中所示的变型针对一种LGA(矩栅阵列)型CSP 13，其中形成在CSP 13的封装衬底3的背表面3b上的外部端子构成连接盘3d。
除外部端子以外，CSP 13的结构类似于图1至图3中所示CSP 7的结构。因此，同样在LGA型CSP 13中，也可以获得与在图1至图3所示CSP 7中获得的有益效果类似的有益效果。
(第二实施例)
图13是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的结构的一个例子的平面图，图14是表示图13中所示半导体器件的结构的一个例子的截面图，图15是沿着图13中的A-A线获得的结构的局部放大截面图，图16是沿着图13中的B-B线获得的结构的局部放大截面图，图17是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的一个变型结构的平面图，图18是表示图17中所示半导体器件的结构的一个例子的截面图，图19是沿着图17中的A-A线获得的结构的局部放大截面图，图20是沿着图17中的B-B线获得的结构的局部放大截面图，图21是表示以透视方式透过密封体观察到的根据本发明第二实施例的半导体器件的一个变型结构的平面图，图22是表示图21中所示半导体器件的结构的一个例子的截面图，以及图23是沿着图22中所示部分A获得的结构的局部放大截面图。
图13至图16中所示的该第二实施例的半导体器件，配置成通过芯片键合膜2把第二半导体芯片17固定到半导体芯片1，并将其描述为CSP 14，CSP 14是类似于CSP 7的树脂模制型CSP并具有小尺寸芯片层叠结构。
即，如图15和图16中所示，把干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上。在其中使半导体芯片1的主表面1a朝上的面向上安装中，通过芯片键合膜2，把第一级的半导体芯片1安装在封装衬底3的主表面3a上形成的干型抗蚀剂膜3f上，并在其中使第二半导体芯片17的主表面17a朝上的面向上安装中，把第二级的第二半导体芯片17安装在第一级的半导体芯片1上。这里，第二半导体芯片17也具有一个通过芯片键合膜2固定到半导体芯片1的主表面1a的背表面17b。
这里，如图15中所示，使用导线4，分别将第一级的半导体芯片1的焊盘1c和第二级的第二半导体芯片17的焊盘17c与封装衬底3的键合电极3h电连接。可选地，如图16中所示，使用导线4把第一级的半导体芯片1的焊盘1c和第二级的第二半导体芯片17的焊盘17c彼此电连接。
这里，在这种芯片和衬底的连接中，芯片侧构成第一键合侧，而衬底侧构成第二键合侧。此外，在芯片的相互连接中，如图16中所示，第二级的第二半导体芯片17侧构成第一键合侧，而第一级的半导体芯片1侧构成第二键合侧。
以这种方式，同样在具有芯片层叠结构的CSP 14中，把干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上，并因此可以通过芯片键合膜2分别把第一级的半导体芯片1和第二级的第二半导体芯片17固定到封装衬底3，由此可以在类似的环境中装配两个芯片，从而简化了制造工艺。即，与其中通过糊状材料固定第一级的半导体芯片，并进一步使用其他芯片键合器件通过芯片键合膜2固定第二级的第二半导体芯片的情况相比较，可实现半导体器件制造成本的降低。
此外，通过使用芯片键合膜2来固定第一级的半导体芯片1，可以减少第一级的半导体芯片1的安装倾斜，并因此能够实现高可靠性层叠。
此外，把根据图17至图20中所示变型的半导体器件表示为CSP15，其具有与图13至图16中所示CSP 14的结构相似的小型化芯片层叠结构。CSP 15与上述CSP 14的区别在于，当芯片和衬底彼此连接时，衬底侧构成第一键合侧，而芯片侧构成第二键合侧。另外，当芯片彼此连接时，如图20中所示，第一级的半导体芯片1侧构成第一键合侧，而第二级的第二半导体芯片17构成第二键合侧。
从而，CSP 15能制造其厚度比使用CSP 14制造的半导体芯片的厚度更小的半导体器件。
接着，把根据图21至图23中所示变型的半导体器件表示为CSP16，其具有与CSP 14和CSP 15的结构相似的小型化芯片层叠结构。然而，如图23中所示，通过倒装芯片连接，把第一级的半导体芯片1连接在封装衬底3的主表面3a上形成的干型抗蚀剂膜3f上，并把第二半导体芯片17层叠在半导体芯片1上。
即，利用倒装芯片连接，通过焊料突起电极18和金凸点19，连接半导体芯片1和在封装板3的主表面3a上的倒装电极3i。把底部填充(underfill)树脂22置入在倒装芯片连接部分中。这种底部填充树脂22可以是糊状粘合材料或膜状粘合材料。
此外，把第二半导体芯片17层叠在利用倒装芯片连接通过芯片键合膜2连接的半导体芯片1上。使用导线4，将该第二半导体芯片17与封装衬底3的键合电极3h电连接。
同样在CSP 16中，由于把干型抗蚀剂膜3f形成在封装衬底3的主表面3a和背表面3b上，所以能减少封装衬底3的翘曲，并因此可以使第一级的半导体芯片1的倒装芯片连接稳定化。与CSP 14相比，具有这种通过倒装芯片连接来连接第一级半导体芯片1的芯片层叠结构的CSP 16能实现半导体器件的更高操作速度。
(第三实施例)
图24是表示在树脂模制后装配的一个例子的制造工艺流程图。
在第三实施例中，在执行标记后执行焊球安装。
在焊球安装步骤中，在把焊料施加到封装衬底3的连接盘3d之后，通过回流处理形成焊接凸点8。因而，同样在焊球安装步骤中，出现了封装衬底3由于回流处理而进一步翘曲的缺点。在标记步骤中，使用激光标记方法等执行标记。然而，在封装衬底3翘曲的状态下，难以用激光束垂直地照射共同密封体5的表面，并因此出现了其中没有把标记施加到共同密封体5的表面的误标记。
考虑到上述缺点，在第三实施例中，在执行形成焊接凸点8的回流处理之前，把标记步骤作为回流处理之前的步骤来执行，回流处理是使封装衬底3出现翘曲的原因之一。因而，可以抑制误标记。
至此基于本发明的实施例，具体说明了由本发明人进行的本发明。然而，本发明并不限于本发明的上述实施例，不用说，在不脱离本发明的范围的情况下，可以对本发明进行各种变型。
例如，在具有在上述第二实施例中说明的芯片层叠结构的半导体器件中，第二级的第二半导体芯片17的固定并不限于使用芯片键合膜2的固定，并且第二级的第二半导体芯片17可以通过使用例如糊状粘合材料来固定。
本发明适用于包括印制线路板的电子器件及其制造技术。

Claims (12)

1.一种半导体器件，包括：
印制线路板，其具有主表面、以相对方式面向所述主表面的背表面、形成在所述主表面和所述背表面上方的多个导体部分、以及干型抗蚀剂膜，所述干型抗蚀剂膜形成在所述主表面和所述背表面上方，覆盖所述多个导体部分中的一些导体部分，并且由膜形成；
半导体芯片，其安装在所述印制线路板的所述主表面上方；和
芯片键合膜，其布置在所述印制线路板的所述主表面与所述半导体芯片之间，
其中，所述半导体芯片通过所述芯片键合膜被固定到所述印制线路板的所述主表面上的所述干型抗蚀剂膜。
2.根据权利要求1所述的半导体器件，其中，在所述印制线路板的所述主表面和所述背表面中，形成在导体部分面积较小的表面上方的所述干型抗蚀剂膜的厚度设定为大于形成在导体部分面积较大的表面上方的所述干型抗蚀剂膜的厚度。
3.根据权利要求1所述的半导体器件，其中，在所述印制线路板的所述主表面和所述背表面中，形成在导体部分长度较短的表面上方的所述干型抗蚀剂膜的厚度设定为大于形成在导体部分长度较长的表面上方的所述干型抗蚀剂膜的厚度。
4.根据权利要求1所述的半导体器件，其中，所述半导体芯片的电极和所述印制线路板的电极通过导线彼此电连接。
5.根据权利要求1所述的半导体器件，其中，所述印制线路板的所述导体部分包括铜布线。
6.根据权利要求1所述的半导体器件，其中，第二半导体芯片通过芯片键合膜被固定到所述半导体芯片。
7.根据权利要求6所述的半导体器件，其中，所述半导体芯片和所述第二半导体芯片通过所述印制线路板的电极和导线而彼此电连接。
8.根据权利要求1所述的半导体器件，其中，所述半导体芯片包括主表面、以相对方式面向所述主表面的背表面、和形成在所述主表面上方的多个电极，并且在所述半导体芯片的所述主表面以相对方式面向所述印制线路板的所述主表面的状态下，安装所述半导体芯片。
9.一种半导体器件制造方法，包括下列步骤：
(a)制备印制线路板，其具有主表面、以相对方式面向所述主表面的背表面、形成在所述主表面和所述背表面上方的多个导体部分、以及干型抗蚀剂膜，所述干型抗蚀剂膜形成在所述主表面和所述背表面上方，覆盖所述多个导体部分中的一些导体部分，并且由膜形成；
(b)通过芯片键合膜，把半导体芯片连接到所述印制线路板的所述主表面；
(c)电连接所述半导体芯片和所述印制线路板；以及
(d)密封所述半导体芯片，
其中，通过所述芯片键合膜，把所述半导体芯片固定到所述印制线路板的所述主表面上的所述干型抗蚀剂膜。
10.根据权利要求9所述的半导体器件制造方法，其中，在所述步骤(a)中，制备多腔衬底，所述多腔衬底构成所述印制线路板并被定义成能够在其上分别形成半导体器件的多个区域，在所述步骤(d)中，在用树脂模制模具的一个腔共同覆盖所述多腔衬底上的所述多个区域的状态下，形成树脂密封，并且在所述步骤(d)之后，把其上形成所述多个树脂密封区域的所述多腔衬底分割成各个半导体器件。
11.根据权利要求9所述的半导体器件制造方法，其中，在所述步骤(c)中，通过导线，把所述半导体芯片和所述印制线路板彼此电连接。
12.根据权利要求9所述的半导体器件制造方法，其中，所述半导体芯片包括主表面、以相对方式面向所述主表面的背表面、和形成在所述主表面上方的多个电极，并且在步骤(b)中，在所述半导体芯片的所述主表面以相对方式面向所述印制线路板的所述主表面的状态下，安装所述半导体芯片。
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