JP4260617B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4260617B2 JP4260617B2 JP2003426943A JP2003426943A JP4260617B2 JP 4260617 B2 JP4260617 B2 JP 4260617B2 JP 2003426943 A JP2003426943 A JP 2003426943A JP 2003426943 A JP2003426943 A JP 2003426943A JP 4260617 B2 JP4260617 B2 JP 4260617B2
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Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す断面図、図2は図1に示す半導体装置の製造方法の一例を示す組み立てフロー図、図3は図2に示す組み立てフローのステップS1〜S5に対応した組み立て状態の一例を示す断面図、図4は図2に示す組み立てフローのステップS6〜S9に対応した組み立て状態の一例を示す断面図、図5は図2に示す組み立てフローのステップS10〜S11に対応した組み立て状態の一例を示す部分断面図、図6は図2に示す組み立てフローのステップS12〜S13に対応した組み立て状態の一例を示す部分断面図、図7は図2に示す組み立てフローのステップS1〜S4に対応したウェハ状態の一例を示す斜視図、図8は図2に示す組み立てフローのNCP塗布工程におけるNCP塗布方法の一例を示す断面図、図9は図2に示す組み立てフローのFC搭載工程における仮搭載方法の一例を示す断面図、図10は図2に示す組み立てフローのFC搭載工程における本圧着方法の一例を示す断面図、図11は図10に示すA部の構造を示す拡大部分断面図、図12は本発明の実施の形態の変形例の圧着方法を示す拡大部分断面図、図13は図1に示す半導体装置の実装基板への実装構造の一例を示す部分断面図、図14は図10に示す本圧着方法に対する比較例の圧着方法を示す拡大部分断面図、図15は図14に示す比較例の圧着方法によるチップ裏面への樹脂接着剤の付着状態を示す平面図である。
1a 主面
1b 裏面
1c パッド
1d 金バンプ(突起電極)
1e 表面保護膜
2 第2の半導体チップ
2a 主面
2b 裏面
3 第3の半導体チップ
3a 主面
3b 裏面
4 第4の半導体チップ
4a 主面
4b 裏面
5 パッケージ基板(配線基板)
5a 主面
5b 裏面
5c リード(電極)
5d はんだプリコート
5e 内部配線
5f ワイヤ接続用リード
5g スルーホール配線
5h バンプランド
5i ソルダレジスト膜
6 ワイヤ
7 NCP(非導電性の樹脂接着剤)
8 ノズル
9 半導体ウェハ
9a 主面
9b 裏面
9c 凹凸
9d 研削痕
9e ダイシングライン
10 封止体
11 はんだボール(外部端子)
12 ダイボンド剤(接着剤)
13 加圧ブロック
13a 加圧面
13b 吸着ブロック
14 シート状部材
15 実装基板
15a 端子
16 SIP(半導体装置)
17 はんだ
18 チップ
18a 裏面
Claims (12)
- (a)半導体ウェハの裏面を研削して、前記半導体ウェハの厚さを薄くする工程と、
(b)前記(a)工程の後に、前記半導体ウェハの裏面を平坦化する工程と、
(c)前記(b)工程の後に、前記半導体ウェハを複数の半導体チップに分割する工程と、
(d)配線基板の主面に樹脂接着剤を配置する工程と、
(e)前記(d)工程の後に、前記(c)工程で取得した前記複数の半導体チップにおける第1半導体チップを吸着ブロックで保持し、前記第1半導体チップの主面が前記配線基板の前記主面と対向するように、前記第1半導体チップの前記主面に形成された突起電極を介して前記配線基板の前記樹脂接着剤上に配置する工程と、
(f)前記(e)工程の後、前記第1半導体チップの前記主面とは反対側の裏面側にシート状部材を介して配置された加圧ブロックにより前記第1半導体チップの裏面を押圧して、前記第1半導体チップの前記突起電極と前記配線基板の前記主面に形成された電極とを電気的に接続する工程と、
(g)前記(f)工程の後、第2半導体チップを前記第1半導体チップの前記裏面上にダイボンド剤を介して搭載する工程と、
(h)前記第2半導体チップと前記配線基板を複数のワイヤを介して電気的に接続する工程と、
(i)前記第1半導体チップ、前記第2半導体チップ、および前記複数のワイヤを樹脂で封止する工程と、
を有し、
前記第1半導体チップの前記裏面と前記第2半導体チップとの間には、前記樹脂接着剤が配置されていないことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記(b)工程では、前記半導体ウェハの裏面がポリッシングにより平坦化されることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(b)工程では、前記半導体ウェハの裏面がエッチングにより平坦化されることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(f)工程では、熱を印加した状態で行うことを特徴とする半導体装置の製造方法。
- 請求項4記載の半導体装置の製造方法において、前記シート状部材は、フッ素樹脂から成ることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記樹脂接着剤は非導電性で、かつ熱硬化性樹脂から成ることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記ダイボンド剤は熱硬化性樹脂から成ることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(i)工程における樹脂は、熱硬化性樹脂から成ることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(i)工程の後に、外部端子として複数のはんだボールを前記配線基板の裏面上に設けることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(d)工程の前に、前記配線基板の主面のフリップチップ接続が行われる複数の電極上に、はんだをプリコートすることを特徴とする半導体装置の製造方法。
- 請求項10記載の半導体装置の製造方法において、前記プリコートされたはんだを用いて、フリップチップ接続の際に、突起電極である金バンプをはんだ接続することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記(d)工程で、ペースト状の非導電性の樹脂接着剤を前記配線基板の主面上に塗布することを特徴とする半導体装置の製造方法。
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JP2003426943A JP4260617B2 (ja) | 2003-12-24 | 2003-12-24 | 半導体装置の製造方法 |
TW093135102A TWI381459B (zh) | 2003-12-24 | 2004-11-16 | Semiconductor device and manufacturing method thereof |
KR1020040106950A KR20050065318A (ko) | 2003-12-24 | 2004-12-16 | 반도체장치 및 그 제조 방법 |
US11/017,077 US20050140023A1 (en) | 2003-12-24 | 2004-12-21 | Method of manufacturing a semiconductor device |
CNB2004101048860A CN100477208C (zh) | 2003-12-24 | 2004-12-24 | 制造半导体器件的方法 |
US11/648,646 US7598121B2 (en) | 2003-12-24 | 2007-01-03 | Method of manufacturing a semiconductor device |
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TW200522293A (en) * | 2003-10-01 | 2005-07-01 | Koninkl Philips Electronics Nv | Electrical shielding in stacked dies by using conductive die attach adhesive |
JP4538830B2 (ja) * | 2004-03-30 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2006261485A (ja) * | 2005-03-18 | 2006-09-28 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR20070095504A (ko) * | 2005-10-14 | 2007-10-01 | 인티그런트 테크놀로지즈(주) | 적층형 집적회로 칩 및 패키지. |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US7993971B2 (en) * | 2007-12-28 | 2011-08-09 | Freescale Semiconductor, Inc. | Forming a 3-D semiconductor die structure with an intermetallic formation |
US20090289101A1 (en) * | 2008-05-23 | 2009-11-26 | Yong Du | Method for ball grid array (bga) solder attach for surface mount |
KR20100109243A (ko) | 2009-03-31 | 2010-10-08 | 삼성전자주식회사 | 반도체 패키지 |
US8617926B2 (en) | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
JP2012221989A (ja) | 2011-04-04 | 2012-11-12 | Elpida Memory Inc | 半導体装置製造装置、及び半導体装置の製造方法 |
JP6100489B2 (ja) | 2012-08-31 | 2017-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN104321866B (zh) | 2012-09-14 | 2018-03-02 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN103107108B (zh) * | 2012-12-12 | 2015-04-22 | 贵州振华风光半导体有限公司 | 改善厚膜混合集成电路同质键合系统质量一致性的方法 |
KR102066015B1 (ko) | 2013-08-13 | 2020-01-14 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조방법 |
JP2017059707A (ja) * | 2015-09-17 | 2017-03-23 | 富士通株式会社 | 積層チップ、積層チップを搭載する基板、及び積層チップの製造方法 |
JP6639915B2 (ja) * | 2016-01-08 | 2020-02-05 | 東レエンジニアリング株式会社 | 半導体実装装置および半導体実装方法 |
KR102592226B1 (ko) * | 2018-07-17 | 2023-10-23 | 삼성전자주식회사 | 반도체 패키지 본딩헤드 및 본딩방법 |
JP2020136642A (ja) * | 2019-02-26 | 2020-08-31 | 京セラ株式会社 | 半導体チップ、圧電デバイス及び電子機器 |
CN114496824A (zh) * | 2020-10-23 | 2022-05-13 | 长鑫存储技术有限公司 | 裸片取出方法 |
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JPH1167842A (ja) * | 1997-08-19 | 1999-03-09 | Matsushita Electric Ind Co Ltd | 電子部品の実装装置および実装方法 |
JP4343286B2 (ja) * | 1998-07-10 | 2009-10-14 | シチズンホールディングス株式会社 | 半導体装置の製造方法 |
JP3514649B2 (ja) * | 1999-01-27 | 2004-03-31 | シャープ株式会社 | フリップチップ接続構造および接続方法 |
JP3451373B2 (ja) * | 1999-11-24 | 2003-09-29 | オムロン株式会社 | 電磁波読み取り可能なデータキャリアの製造方法 |
JP2001156207A (ja) * | 1999-11-26 | 2001-06-08 | Toshiba Corp | バンプ接合体及び電子部品 |
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JP3597754B2 (ja) * | 2000-04-24 | 2004-12-08 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2001313350A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
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JP3491827B2 (ja) | 2000-07-25 | 2004-01-26 | 関西日本電気株式会社 | 半導体装置及びその製造方法 |
JP2002231879A (ja) * | 2001-01-31 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US6672947B2 (en) | 2001-03-13 | 2004-01-06 | Nptest, Llc | Method for global die thinning and polishing of flip-chip packaged integrated circuits |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
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- 2004-12-21 US US11/017,077 patent/US20050140023A1/en not_active Abandoned
- 2004-12-24 CN CNB2004101048860A patent/CN100477208C/zh not_active Expired - Fee Related
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CN100477208C (zh) | 2009-04-08 |
US20050140023A1 (en) | 2005-06-30 |
TWI381459B (zh) | 2013-01-01 |
KR20050065318A (ko) | 2005-06-29 |
US20070111384A1 (en) | 2007-05-17 |
US7598121B2 (en) | 2009-10-06 |
CN1638122A (zh) | 2005-07-13 |
JP2005191053A (ja) | 2005-07-14 |
TW200522231A (en) | 2005-07-01 |
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