JP2006261485A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006261485A JP2006261485A JP2005078581A JP2005078581A JP2006261485A JP 2006261485 A JP2006261485 A JP 2006261485A JP 2005078581 A JP2005078581 A JP 2005078581A JP 2005078581 A JP2005078581 A JP 2005078581A JP 2006261485 A JP2006261485 A JP 2006261485A
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- main surface
- semiconductor chip
- semiconductor device
- wiring board
- resist film
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Abstract
【解決手段】 主面3aおよび裏面3bに形成された複数の導体部のうちの一部を覆うとともにフィルムからなるドライレジスト膜3fを有するパッケージ基板3と、パッケージ基板3上に搭載された半導体チップ1と、半導体チップ1とパッケージ基板3とを電気的に接続する導電性ワイヤ4と、パッケージ基板3の主面3aと半導体チップ1との間に配置されたダイボンド用フィルム2と、パッケージ基板3の裏面3bに設けられた複数の半田バンプ8と、樹脂からなる封止体6とからなり、パッケージ基板3においてその主面3aと裏面3bにフィルムからなるドライレジスト膜3fが形成されていることにより、パッケージ基板3の反りを抑えることができ、リフロー実装時などのパッケージクラックの発生を防いでCSP7の信頼性の向上を図ることができる。
【選択図】 図3
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を封止体を透過して示す平面図、図2は図1に示す半導体装置の構造の一例を示す断面図、図3は図2に示すA部の構造を示す拡大部分断面図、図4は図1に示す半導体装置に組み込まれる配線基板の構造の一例を示す断面図、図5は図4に示すA部の構造を示す拡大部分断面図、図6は図4に示す配線基板の主面側の配線パターンの一例を示す平面図、図7は図4に示す配線基板の裏面側の配線パターンの一例を示す裏面図、図8は図4に示す配線基板におけるドライレジスト膜の形成方法の一例を示す製造プロセスフロー図、図9は図1に示す半導体装置の組み立てにおける樹脂モールドまでの組み立ての一例を示す製造プロセスフロー図、図10は樹脂モールド後の組み立ての一例を示す製造プロセスフロー図、図11は本発明の実施の形態1における変形例の半導体装置の構造を示す断面図、図12は図11に示すA部の構造を示す拡大部分断面図である。
図13は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図、図14は図13に示す半導体装置の構造の一例を示す断面図、図15は図13のA−A線に沿って切断した構造を示す拡大部分断面図、図16は図13のB−B線に沿って切断した構造を示す拡大部分断面図、図17は本発明の実施の形態2の変形例の半導体装置の構造を封止体を透過して示す平面図、図18は図17に示す半導体装置の構造の一例を示す断面図、図19は図17のA−A線に沿って切断した構造を示す拡大部分断面図、図20は図17のB−B線に沿って切断した構造を示す拡大部分断面図、図21は本発明の実施の形態2の変形例の半導体装置の構造を封止体を透過して示す平面図、図22は図21に示す半導体装置の構造の一例を示す断面図、図23は図22に示すA部の構造を示す拡大部分断面図である。
図24は樹脂モールド後の組み立ての一例を示す製造プロセスフロー図である。
1a 主面
1b 裏面
1c パッド(電極)
2 ダイボンド用フィルム
3 パッケージ基板(配線基板)
3a 主面
3b 裏面
3c コア材
3d ランド(導体部)
3e スルーホール
3f ドライレジスト膜
3g 銅配線(導体部)
3h ボンディング用電極(電極)
3i フリップ用電極
4 導電性ワイヤ
5 一括封止体
6 封止体
7 CSP(半導体装置)
8 半田バンプ
9 多数個取り基板
10 マーキング
11 ダイシングブレード
12 ダイシングテープ
13,14,15,16 CSP(半導体装置)
17 第2の半導体チップ
17a 主面
17b 裏面
17c パッド
18 半田突起電極
19 金バンプ
20 樹脂成形金型
20a キャビティ
21 プレス機
22 アンダーフィル樹脂
Claims (12)
- 主面と、前記主面に対向する裏面と、前記主面および裏面に形成された複数の導体部と、前記主面および裏面上に形成され、かつ前記複数の導体部のうちの一部を覆い、さらにフィルムからなるドライレジスト膜とを有する配線基板と、
前記配線基板の前記主面に搭載された半導体チップと、
前記配線基板の前記主面と前記半導体チップとの間に配置されたダイボンド用フィルムとを有し、
前記配線基板の前記主面の前記ドライレジスト膜上に、前記半導体チップが前記ダイボンド用フィルムを介して固定されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記配線基板の前記主面と前記裏面のうち、前記導体部の面積が小さい方の面に形成される前記ドライレジスト膜の厚さを、前記導体部の面積が大きい方の面に形成される前記ドライレジスト膜より厚くすることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記配線基板の前記主面と前記裏面のうち、前記導体部の長さが短い方の面に形成される前記ドライレジスト膜の厚さを、前記導体部の長さが長い方の面に形成される前記ドライレジスト膜より厚くすることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップの電極と前記配線基板の電極とが導電性ワイヤによって電気的に接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記配線基板の前記導体部は、銅配線を含むことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップの上に、第2の半導体チップがダイボンド用フィルムを介して固定されていることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記半導体チップおよび前記第2の半導体チップは、それぞれ前記配線基板の電極と導電性ワイヤによって電気的に接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップは、主面と、前記主面に対向する裏面と、前記主面に形成された複数の電極とを有し、前記半導体チップは前記半導体チップの前記主面と前記配線基板の前記主面が対向するように搭載されていることを特徴とする半導体装置。
- (a)主面と、前記主面に対向する裏面と、前記主面および裏面に形成された複数の導体部と、前記主面および裏面上に形成され、かつ前記複数の導体部のうちの一部を覆い、さらにフィルムからなるドライレジスト膜とを有する配線基板を準備する工程と、
(b)前記配線基板の前記主面上に半導体チップをダイボンド用フィルムを介して接続する工程と、
(c)前記半導体チップと前記配線基板とを電気的に接続する工程と、
(d)前記半導体チップを封止する工程とを有し、
前記配線基板の前記主面の前記ドライレジスト膜上に、前記半導体チップを前記ダイボンド用フィルムを介して固定することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、前記(a)工程で、それぞれに半導体装置を形成可能な複数の領域が区画形成された前記配線基板である多数個取り基板を準備し、さらに前記(d)工程において、樹脂成形金型の1つのキャビティで前記多数個取り基板の前記複数の領域を一括して覆った状態で樹脂封止を行い、前記(d)工程の後、個片化を行うことを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記(c)工程で、前記半導体チップと前記配線基板とを導電性ワイヤによって電気的に接続することを特徴とする半導体装置の製造方法。
- 請求項9記載の半導体装置の製造方法において、前記半導体チップは、主面と、前記主面に対向する裏面と、前記主面上に形成された複数の電極とを有し、さらに前記(b)工程では、前記半導体チップの前記主面が前記配線基板の前記主面と対向するように前記半導体チップを搭載することを特徴とする半導体装置の製造方法。
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JP2005078581A JP2006261485A (ja) | 2005-03-18 | 2005-03-18 | 半導体装置およびその製造方法 |
TW095105294A TW200636938A (en) | 2005-03-18 | 2006-02-16 | A semiconductor device and a manufacturing method of the same |
CNB2006100586776A CN100568498C (zh) | 2005-03-18 | 2006-03-08 | 半导体器件及其制造方法 |
KR1020060024883A KR20060101385A (ko) | 2005-03-18 | 2006-03-17 | 반도체 장치 및 그 제조 방법 |
US11/378,449 US7408252B2 (en) | 2005-03-18 | 2006-03-20 | Semiconductor device and a manufacturing method of the same |
US12/147,905 US7576422B2 (en) | 2005-03-18 | 2008-06-27 | Semiconductor device |
US12/497,174 US7803658B2 (en) | 2005-03-18 | 2009-07-02 | Semiconductor device |
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US8357998B2 (en) * | 2009-02-09 | 2013-01-22 | Advanced Semiconductor Engineering, Inc. | Wirebonded semiconductor package |
TWI388018B (zh) * | 2009-10-22 | 2013-03-01 | Unimicron Technology Corp | 封裝結構之製法 |
TWI416636B (zh) * | 2009-10-22 | 2013-11-21 | Unimicron Technology Corp | 封裝結構之製法 |
CN102054714B (zh) * | 2009-11-06 | 2012-10-03 | 欣兴电子股份有限公司 | 封装结构的制法 |
US8742603B2 (en) * | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
JP2012033637A (ja) | 2010-07-29 | 2012-02-16 | Nitto Denko Corp | ダイシングテープ一体型半導体裏面用フィルム及び半導体装置の製造方法 |
US9406579B2 (en) * | 2012-05-14 | 2016-08-02 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of controlling warpage in semiconductor package |
CN110429036A (zh) * | 2019-06-19 | 2019-11-08 | 惠州市志金电子科技有限公司 | 接触式身份识别卡的封装工艺及接触式身份识别卡 |
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