CN1532932A - 半导体装置及其制造方法、电子设备、电子仪器 - Google Patents

半导体装置及其制造方法、电子设备、电子仪器 Download PDF

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Publication number
CN1532932A
CN1532932A CNA2004100301842A CN200410030184A CN1532932A CN 1532932 A CN1532932 A CN 1532932A CN A2004100301842 A CNA2004100301842 A CN A2004100301842A CN 200410030184 A CN200410030184 A CN 200410030184A CN 1532932 A CN1532932 A CN 1532932A
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mentioned
semiconductor
semiconductor packages
resin
projection electrode
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CN100349292C (zh
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盐泽雅邦
理
青栁哲理
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离。半导体封装PK1，PK2经突出电极13彼此接合，在半导体封装PK1，PK2之间，不与半导体芯片3接触地在分别与突出电极13接触的状态下在突出电极13的周围设置树脂15。

Description

半导体装置及其制造方法、电子设备、电子仪器
技术领域
本发明涉及半导体装置、电子设备、电子仪器和半导体装置的制造方法，尤其适用于半导体封装的层叠结构中。
背景技术
现有的半导体封装中，例如专利文献1所公开的那样，通过经焊锡球层叠半导体封装实现空间节省。这里，二次安装层叠的半导体封装时，为防止半导体封装之间的焊锡球再熔融而产生位置偏离，在层叠的半导体封装之间填充树脂。
【专利文献1】
特开平6-13541号公报
但是，在现有半导体封装中，在经焊锡球层叠的半导体封装之间的整个间隙中填充树脂。因此，固化半导体封装之间填充的树脂之际，树脂中包含的水分不能充分去除，半导体封装之间填充的树脂中残留水分。这样，层叠的半导体封装在2次安装时的再回流时，半导体封装之间填充的树脂中包含的水分气化而膨胀，出现半导体封装之间产生剥离的问题。
发明内容
因此本发明的目的是提供一种能够防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离的半导体装置、电子设备、电子仪器和半导体装置的制造方法。
为解决上述问题，根据本发明之一形式的半导体装置，其特征在于，包括：搭载第一半导体芯片的第一半导体封装；搭载第二半导体芯片的第二半导体封装；突出电极，其连接上述第一半导体封装和上述第二半导体封装，以便使上述第二半导体封装保持在上述第一半导体芯片上；树脂，其设置在上述第一半导体封装和上述第二半导体封装之间，以配置成避开上述第一半导体芯片的表面的至少一部。
由此，在经突出电极连接的第一半导体封装和第二半导体封装之间仍残留间隙的状态下，能够在第一半导体封装和第二半导体封装之间填充树脂。因此，容易去除第一半导体封装和第二半导体封装之间的树脂中包含的水分，在2次安装时的回流时，能够抑制第一半导体封装和第二半导体封装之间的树脂膨胀。其结果，能够抑制第一半导体封装和第二半导体封装之间的剥离，并且能够由树脂固定第一半导体封装和上述第二半导体封装，2次安装时进行突出电极的再回流时也能够防止第一半导体封装和第二半导体封装之间的位置偏离。
根据本发明之一形式的半导体装置，其特征在于上述突出电极是焊锡球。
由此，通过进行回流处理能够电连接第一半导体封装和第二半导体封装，能够将第二半导体封装有效安装在第一半导体封装上。
根据本发明之一形式的半导体装置，其特征在于，上述树脂不接触上述突出电极，配置在上述第一半导体封装和上述第二半导体封装之间。
由此，在经突出电极连接的第一半导体封装和第二半导体封装之间仍残留间隙的状态下，能够在第一半导体封装和第二半导体封装之间填充树脂，同时在进行突出电极的回流处理的情况下，也能够抑制对树脂的热损坏。因此，能够降低树脂的耐热性，能够选择吸湿性低的树脂，能够防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离。
根据本发明之一形式的半导体装置，其特征在于，上述树脂仅配置在上述第二半导体封装的角上。
由此，在第一半导体封装和第二半导体封装之间的间隙狭窄的情况下也能够在第一半导体封装和第二半导体封装之间填充树脂。因此，能够抑制制造工序变复杂，并且能够防止层叠的半导体封装二次安装时位置偏离，同时抑制半导体封装之间的剥离。
另外，根据本发明之一形式的半导体装置，其特征在于，上述第一半导体封装和上述第二半导体封装上对应上述树脂的配置位置设置突出电极的未配置区域。
由此，在突出电极密集配置的情况下，也能够不与突出电极接触地在第一半导体封装和第二半导体封装之间填充树脂。因此，能够对应多端子化，并且能够抑制制造工序变复杂，并且能够防止层叠的半导体封装二次安装时位置偏离，同时抑制半导体封装之间的剥离。
另外，根据本发明之一形式的半导体装置，其特征在于，上述树脂在与上述突出电极的周围接触的状态下配置着。
由此，以第一半导体封装和第二半导体封装之间残留间隙的形态、在第一半导体封装和第二半导体封装之间设置树脂的情况下，也不需要在树脂与突出电极之间设置间隔。因此，第一半导体封装和第二半导体封装之间不需要与突出电极另外设置确保用于配置树脂的区域，能够对突出电极的配置不会产生影响地在第一半导体封装和第二半导体封装之间填充树脂。其结果，能够抑制突出电极的配置数的减少，并且防止层叠的半导体封装二次安装时位置偏离，同时抑制半导体封装之间的剥离。
根据本发明之一形式的半导体装置，其特征在于，上述树脂包含焊剂。
由此，在焊接回流时，能够在焊接周围上缘(布置)树脂，并且通过焊接稳定进行接合。因此通过进行回流处理，能够在与突出电极的周围接触的状态下配置树脂，不会使制造工序变复杂，能够防止层叠的半导体封装二次安装时位置偏离，同时抑制半导体封装之间的剥离。
另外，根据本发明之一形式的半导体装置，其特征在于，上述第一半导体封装包括：第一载体基板和在上述第一载体基板上倒装片安装的第一半导体芯片；上述第二半导体封装包括经上述突出电极安装在上述第一载体基板上，以使之保持在上述第一半导体芯片上的第二载体基板；搭载在上述第二载体基板上的第二半导体芯片和密封上述第二半导体芯片的密封件。
由此，即使第一半导体封装和第二半导体封装的种类不同的情况下，也能够防止层叠的半导体封装二次安装时位置偏离，同时抑制半导体封装之间的剥离，能够节省空间，并且可以提高第一半导体封装和第二半导体封装之间的连接可靠性。
根据本发明之一形式的半导体装置，其特征在于，上述第一半导体封装是在上述第一载体基板上倒装片安装上述第一半导体芯片的球栅阵列，上述第二半导体封装是模压密封上述第二载体基板上搭载的第二半导体芯片的球栅阵列或芯片尺寸封装。
由此，使用通用封装的情况下也能够防止层叠的半导体封装二次安装时位置偏离，并且抑制半导体封装之间的剥离，不会破坏生产效率，提高不同种类封装之间的连接可靠性。
根据本发明之一形式的电子设备，其特征在于，包括：搭载第一电子部件的第一封装；搭载第二电子部件的第二封装；突出电极，其连接上述第一封装和上述第二封装，以使上述第二封装保持在上述第一电子部件上；树脂，其设置在上述第一封装和上述第二封装之间，以配置成避开上述第一电子部件的表面的至少一部分。
由此，在经突出电极连接的第一封装和第二封装之间仍残留间隙的状态下，能够在第一封装和第二封装之间填充树脂。因此，能够抑制半导体封装之间的剥离，并且能够用树脂固定第一封装和第二封装，在2次安装时进行突出电极的再次回流的情况下，也能够防止第一封装和第二封装之间的位置偏离。
根据本发明之一形式的电子仪器，其特征在于，包括：搭载第一半导体芯片的第一半导体封装；搭载第二半导体芯片的第二半导体封装；突出电极，其连接上述第一封装和上述第二封装，以使上述第二封装保持在上述第一电子部件上；树脂，其设置在上述第一封装和上述第二封装之间，以配置成避开上述第一电子部件的表面的至少一部分；搭载连接上述第二半导体封装的上述第一半导体封装的母基板；经上述母基板连接上述第一半导体芯片和上述第二半导体芯片的电子部件。
由此，能够抑制层叠的半导体封装的可靠性恶化，并且能够防止二次安装时的半导体封装位置偏离，能够将电子仪器小型化、轻量化，并且提高电子仪器的可靠性。
另外，根据本发明之一形式的制造方法，其特征在于，包括：经突出电极连接搭载第一半导体芯片的第一半导体封装和搭载第二半导体芯片的第二半导体封装的工序；以避开上述第一半导体芯片的表面的至少一部分的形态，在上述第一半导体封装和上述第二半导体封装之间设置树脂的工序。
由此，在第一半导体封装和第二半导体封装之间填充树脂的情况下，也能够在经突出电极连接的第一半导体封装和第二半导体封装之间残余间隙，能够防止层叠的半导体封装二次安装时位置偏离，并且抑制第一半导体封装和第二半导体封装之间的剥离。
根据本发明之一形式的半导体装置的制造方法，其特征在于上述树脂不与上述突出电极接触地配置在上述第一半导体封装和上述第二半导体封装之间。
由此，进行突出电极的回流处理的情况下，也能够抑制对树脂的热破坏，降低树脂的耐热性，能够选择吸湿性低的树脂。
根据本发明之一形式的半导体装置的制造方法，其特征在于，上述树脂仅配置在上述第二半导体封装的角上。
由此，在第一半导体封装和第二半导体封装之间的间隙狭窄的情况下，也能够抑制制造工序变复杂，并且在第一半导体封装和第二半导体封装之间有效填充树脂。
根据本发明之一形式的半导体装置的制造方法，其特征在于，包括：向第一半导体封装上设置的岸面供给加入树脂的焊剂的工序；在供给上述加入树脂的焊剂的岸面上配置第二半导体封装上设置的焊锡球的工序；通过进行回流处理使上述焊锡球熔融、将上述焊锡球接合于上述岸面上的同时，使加入到上述加入树脂的焊剂的树脂沿着上述焊锡球的表面上缘上去的工序。
由此，通过进行焊锡球的回流处理能够在与突出电极的周围接触的状态下配置树脂，不会使制造工序变复杂，能够防止层叠的半导体封装二次安装时位置偏离，同时抑制第一半导体封装和第二半导体封装之间的剥离。
附图说明
图1是表示第一实施方式的半导体装置的简要结构的截面图；
图2是表示图1的半导体装置的制造方法的一个例子的截面图；
图3是表示第二实施方式的半导体装置的简要结构的截面图；
图4是表示第三实施方式的半导体装置的简要结构的截面图；
图5是表示第四实施方式的半导体装置的简要结构的截面图；
图6是表示第五实施方式的半导体装置的简要结构的截面图；
图7是表示图6的半导体装置的制造方法的一个例子的截面图；
图8是表示第六、第七实施方式的半导体装置的简要结构的截面图；
图9是表示第八实施方式的半导体装置的制造方法的一个例子的截面图。
具体实施方式
下面参照附图说明本发明的实施方式的半导体装置及其制造方法。
图1是表示本发明的第一实施方式的半导体装置的简要结构的截面图。
图1中，半导体封装PK1上设置载体基板1，载体基板1的两面上分别形成岸面2a、2b。并且，载体基板1上倒装片安装半导体芯片3，半导体芯片3上设置有用于倒装片安装的突出电极4。并且，半导体芯片3上设置的突出电极4，经各向异性导电片5ACF(各向异性导电膜)接合于岸面2b上。
另一方面，半导体封装PK2上设置载体基板11，载体基板11的里面上形成岸面12，岸面12上设置有突出电极13。载体基板11上安装半导体芯片，安装半导体芯片的载体基板11用密封树脂14密封。载体基板11上也可以安装引线接合连接的半导体芯片，也可以安装半导体芯片的层叠结构。
并且，通过载体基板1上设置的岸面2b上接合突出电极13，将载体基板11配置在半导体芯片3上，在半导体封装PK1上安装半导体封装PK2。
另外，半导体封装PK1，PK2之间不与半导体芯片3接触地设置有树脂15。这里树脂15分别接触突出电极13，可以设置在突出电极13的周围。
由此，在经突出电极13连接的半导体封装PK1，PK2之间仍残留间隙的状态下，能够在半导体封装PK1，PK2之间设置树脂15。因此，容易去除半导体封装PK1，PK2之间的树脂15中包含的水分，在2次安装时的回流时，能够抑制半导体封装PK1，PK2之间的树脂15膨胀。其结果，能够抑制半导体封装PK1，PK2之间的剥离，并且能够由树脂15彼此固定半导体封装PK1，PK2，2次安装时进行突出电极13的再回流时也能够防止半导体封装PK1，PK2之间的位置偏离。
通过分别与突出电极13接触地在突出电极13的周围设置树脂15，在半导体封装PK1，PK2之间残留间隙，在半导体封装PK1，PK2之间设置树脂15的情况下，也不需要在树脂15和突出电极13之间空出间隔。因此，半导体封装PK1，PK2之间不需要与突出电极13另外地设置用于配置树脂15的区域，能够抑制突出电极13的配置数减少，并且能够在半导体封装PK1，PK2之间设置树脂15。
作为载体基板1，11，例如能够使用两面基板、多层配线基板、叠放基板、带基板或膜基板等，作为载体基板1，11的材质，能够使用例如聚酰胺树脂、玻璃环氧树脂、BT树脂、芳族聚酰胺和环氧树脂的复合物物或陶瓷等。作为突出电极4，6，13，能够使用例如Au块、由焊锡材料等覆盖的Cu块，Ni块或焊锡球等。
另外，在经突出电极13彼此连接半导体封装PK1，PK2的情况下，可以使用焊接接合、合金接合等的金属接合，或也可以使用ACF接合、NCF(非导电膜)接合、ACP(各向异性导电膏)接合、NCP(非导电膏)接合等的压接接合。
图2是表示图1的半导体装置的制造方法的一个例子的截面图。
在图2(a)中，半导体封装PK1上层叠半导体封装PK2的情况下，在半导体封装PK2的岸面12上作为突出电极13形成焊锡球，同时向载体基板1的岸面2b上供给未填充焊剂7。另外，未填充焊剂7可以通过混入树脂的焊剂同时进行热固化树脂向基层的焊接和粘接。
接着如图2(b)所示，在半导体封装PK1上安装半导体封装PK2。并且，通过进行突出电极13的回流处理使突出电极13熔融，将突出电极13接合在岸面2b上，同时未加入未填充焊剂7中的树脂沿着突出电极13布置，使之与突出电极13周围接触，在半导体封装PK1，PK2之间形成树脂15。
这里，通过使用未填充焊剂7进行突出电极13的回流处理，能够在与突出电极13的周围接触的状态下配置树脂15，不会使制造工序变复杂，可以在半导体封装PK1，PK2之间形成树脂15。
另外，除未填充焊剂7之外，也可以使用未填充膏(包含热固化性树脂的焊接膏)。
另外，通过在突出电极13的周围设置树脂15，确保树脂15中包含的水分逃离的空间，并且能够在半导体封装PK1，PK2之间设置树脂15，减少树脂15中包含的水分的残余量。
接着如图2(c)所示，在载体基板1的里面上设置的岸面2a上形成用于将载体基板1安装在母基板8上的突出电极6。
接着如图2(d)所示，将形成突出电极6的载体基板1安装在母基板8上。并且，通过进行突出电极6的回流处理将突出电极6接合在母基板8的岸面9上。
这里，在基本去除半导体封装PK1，PK2之间的树脂15中包含的水分的状态下，可以进行突出电极6的回流处理。因此，突出电极6回流时能够抑制树脂15的膨胀，能够防止半导体封装PK1，PK2彼此剥离。突出电极6回流时进行突出电极13的再回流时也维持半导体封装PK1，PK2用树脂15彼此固定的原样状态，能够防止半导体封装PK1，PK2之间的位置偏离。
另外，在上述实施方式中，说明了为了将半导体封装PK2安装在半导体封装PK1上，在载体基板1的岸面2b上设置突出电极13的同时，在载体基板11的岸面12上供给未填充焊剂7的方法，但也可以在载体基板1的岸面2b上供给未填充焊剂7的同时，在载体基板11的岸面12上设置突出电极13。此外，在上述实施方式中，说明了通过使用未填充焊剂7，分别与突出电极13接触地在突出电极13周围设置树脂15的方法，但不需要一定使用未填充焊剂7，例如也可以在经突出电极13接合半导体封装PK1，PK2后在突出电极13周围填充树脂。另外，上述实施方式中说明了用突出电极13分割树脂15、将树脂15设置在突出电极13的周围的方法，但也可以在多个突出电极13之间填上树脂。而且，在上述实施方式中，说明了在半导体封装PK1，PK2之间设置的全部突出电极13的周围设置树脂15的方法，但也可以仅在半导体封装PK1，PK2之间设置的部分突出电极13的周围设置树脂。另外，在突出电极13周围设置树脂时，也可以对应突出电极13的配置位置经成型的树脂片接合突出电极13。
图3是表示本发明的第二实施方式的半导体装置的简要结构的截面图。
图3中，半导体封装PK11上设置载体基板21，载体基板21的两面上分别形成岸面22a，22c，同时载体基板21内形成内部配线22b。并且，载体基板21上倒装片安装半导体芯片23，半导体芯片23上设置用于倒装片安装的突出电极24。并且，半导体芯片23上设置的突出电极24经各向异性导电片25ACF接合在岸面22c上。载体基板21的里面设置的岸面22a上设置有用于将载体基板21安装在母基板上的突出电极26。
另一方面，半导体封装PK12上设置载体基板31，载体基板31的两面上分别形成岸面32a，32c，同时，载体基板31内形成有内部配线32b。并且，载体基板31上经粘接层34倒装片安装半导体芯片33a，半导体芯片33a经导电性线35a引线接合在连接于岸面32c。另外，半导体芯片33a上避开导电性线35a倒装片安装半导体芯片33b，安装半导体芯片33b经粘接层34b固定在安装半导体芯片33a上，同时经导电性线35b引线接合连接于岸面32c。
另外，载体基板31的里面上设置的岸面32a上，以使载体基板31保持在半导体芯片23上的形态、设置有用于将载体基板31安装在载体基板21上的突出电极36。这里，突出电极36避开半导体芯片23的搭载区域而配置，例如可以在载体基板31的里面周围配置突出电极36。并且载体基板21上设置的岸面22c上接合突出电极36使得载体基板31安装在载体基板21上。
在半导体芯片33a，33b的安装面侧的载体基板31上设置密封树脂37，通过该密封树脂37密封半导体芯片33a，33b。密封树脂37密封半导体芯片33a，33b的情况下，可以通过使用环氧树脂等的热固化树脂的模压成型等进行。
另外，经突出电极36接合的载体基板21，31之间，在载体基板21，31之间残留间隙来设置树脂38。这里树脂38分别与突出电极36接触，设置在突出电极36周围。
由此，层叠不同种类封装的情况下，在经突出电极36连接的载体基板21，31之间仍残留间隙的状态下，能够在载体基板21，31之间设置树脂38。因此，安装大小或种类不同的半导体芯片23，33a，33b时能够节省空间，同时能够防止层叠的半导体封装PK11，PK12在2次安装时位置偏离，并且能够抑制半导体封装PK11，PK12之间的剥离。
图4是表示本发明的第三实施方式的半导体装置的简要结构的截面图。
图4中，半导体封装PK31上设置载体基板41，载体基板41的两面上分别形成岸面42a，42c，同时载体基板41内形成内部配线42b。并且，载体基板21上倒装片安装半导体芯片43，半导体芯片43上设置用于倒装片安装的突出电极44。并且，半导体芯片43上设置的突出电极44经各向异性导电片45ACF接合在岸面42c上。另外，载体基板21的里面设置的岸面42a上设置有用于将载体基板41安装在母基板上的突出电极46。
另一方面，半导体封装PK32上设置半导体芯片51，半导体芯片51上设置电极垫52的同时，使电极垫52露出，设置有绝缘膜53。并且半导体芯片51上露出电极垫52、形成应力缓和层54，电极垫52上形成有在应力缓和层54上延伸的再配置配线55。
并且，再配置配线55上形成焊接抗蚀剂膜56，焊接抗蚀剂膜56上形成有在应力缓和层54中露出再配置配线55的开口部57。并且经开口部57露出的再配置配线55上设置有用于将半导体芯片51倒装片安装在载体基板41上的突出电极58，以将半导体封装PK32保持在半导体芯片53上。
这里，突出电极58避开半导体芯片43的搭载区域配置，例如可以在半导体芯片51的周围配置突出电极58。并且，在载体基板41上设置的岸面42c上接合突出电极58，将半导体芯片PK32安装在载体基板41上。
另外，经突出电极58接合的载体基板41和半导体芯片51之间，在载体基板41与半导体芯片51之间残留间隙地设置树脂59。这里，树脂59分别与突出电极58接触，设置在突出电极58周围。
由此，在半导体封装PK31上层叠W-CSP(晶片级—芯片尺寸封装)时，在经突出电极58接合的载体基板41和半导体芯片51之间仍残留间隙的状态下，能够在载体基板41和半导体芯片51之间设置树脂59。因此，半导体芯片43，51的种类或大小不同的情况下，也不用在半导体芯片43，51之间插入载体基板，在半导体芯片43上能够3维安装半导体芯片51，同时防止层叠的半导体封装PK31，PK32在2次安装时位置偏离，并且能够抑制半导体封装PK31，PK32之间的剥离。其结果，能够抑制3维安装的半导体芯片43，51的可靠性恶化，实现半导体芯片43，51安装时节省空间。
图5是表示本发明的第四实施方式的半导体装置的简要结构的截面图。
在图5中，半导体封装PK41上设置载体基板61，载体基板61的两面上分别形成有岸面62a，62b。
并且，载体基板61上倒装片安装半导体芯片63，半导体芯片63上设置有用于倒装片安装的突出电极64。并且，半导体芯片63上设置的突出电极64经各向异性导电片65ACF接合在岸面62b上。
另一方面，半导体封装PK42上设置载体基板71，在载体基板71的里面上形成岸面72，岸面72上设置有突出电极73。另外，载体基板71上安装半导体芯片，安装半导体芯片的载体基板71用密封树脂74被密封。载体基板71上可以安装引线接合连接的半导体芯片，也可以倒装片安装半导体芯片，也可以安装半导体芯片的层叠结构。
并且，通过载体基板61上设置的岸面62b上接合突出电极73，将使载体基板71配置在半导体芯片63上，将半导体封装PK42安装在半导体封装PK41上。这里，半导体封装PK42和半导体芯片63之间设置树脂76，半导体封装PK42和半导体芯片63经树脂76固定。
半导体封装PK41，PK42之间设置树脂75，使树脂75分别与突出电极73接触，而可以设置在突出电极73的周围。
由此在经突出电极73连接的半导体封装PK41，PK42之间仍残留间隙的状态下，能够在半导体封装PK41，PK42之间设置树脂75，同时用树脂76加固半导体封装PK41，PK42之间的粘接强度。因此，半导体封装PK41，PK42之间设置的树脂75量少时，在2次安装时的突出电极73再回流时，能够防止半导体封装PK41，PK42之间的位置偏离。在2次安装时的突出电极66回流时，能够抑制半导体封装PK41，PK42之间的树脂75膨胀，抑制半导体封装PK41，PK42之间的剥离。
图6是表示本发明的第五实施方式的半导体装置的简要结构的截面图。
在图6中，半导体封装PK51上设置载体基板81，载体基板81的两面上分别形成有岸面82a，82b。
并且，在载体基板81上倒装片安装半导体芯片83，半导体芯片83上设置有用于倒装片安装的突出电极84。并且，半导体芯片83上设置的突出电极84经各向异性导电片85ACF接合在岸面862b上。
另一方面，半导体封装PK52上设置载体基板91，载体基板91的里面上形成岸面92，岸面92上设置有突出电极93。载体基板91上安装半导体芯片，安装半导体芯片的载体基板91用密封树脂94被密封。载体基板91上可以安装引线接合连接的半导体芯片，也可以倒装片安装半导体芯片，也可以安装半导体芯片的层叠结构。
并且，通过载体基板81上设置的岸面82b上接合突出电极93，以使载体基板91配置在半导体芯片83上，将半导体封装PK52安装在半导体封装PK51上。
另外，半导体封装PK51，PK52之间，以接触突出电极93而设置树脂95，树脂95例如可以配置在半导体封装PK52的4个角上。也可以沿着半导体封装PK52的边配置树脂95。
由此在经突出电极93连接的半导体封装PK51，PK52之间仍残留间隙的状态下，能够在半导体封装PK51，PK52之间设置树脂95，同时进行突出电极93的回流时也能够抑制对树脂95的热破坏。
因此，能够降低树脂95的耐热性，能够选择吸湿性低的树脂95，并能够提高层叠的半导体封装PK51，PK52的可靠性。
另外，由于不与突出电极93接触地在半导体封装PK51，PK52之间设置树脂95，也可以对应树脂95的配置位置而设置突出电极93的未配置区域。
由此，在突出电极93密集配置的情况下，也能够不与突出电极93接触地在半导体封装PK51，PK52之间填充树脂95。因此，能够对应半导体封装PK51，PK52的多端子化，并且能够防止层叠的半导体封装PK51，PK52的二次安装时位置偏离，同时抑制半导体封装PK51，PK52之间的剥离。
图7是表示图6的半导体装置的制造方法的一个例子的截面图。
在图7(a)中，半导体封装PK51上层叠半导体封装PK52的情况下，在半导体封装PK52的岸面92上作为突出电极93形成焊锡球，同时向载体基板81的岸面82b上供给焊剂87。另外，也可以向载体基板81的岸面82b上供给焊接膏，以替代供给焊剂87。
接着如图7(b)所示，在半导体封装PK51上安装半导体封装PK52。并且，通过进行突出电极93的回流处理使突出电极93熔融，将突出电极93接合在岸面82b上。
接着如图7(c)所示，通过使用焊接膏等不与突出电极93接触地在半导体封装PK51，PK52之间注入树脂95，以固化树脂95。
这里，不与突出电极93接触地在半导体封装PK51，PK52之间设置树脂95，使得能够确保树脂95中包含的水分逃离的间隙，能够用树脂95固定半导体封装PK51，PK52，减少树脂95中包含的水分的残留量。
接着如图(7d)所示，在载体基板81的里面上设置的岸面82a上形成用于将载体基板81安装在母基板上的突出电极86。并且，将形成突出电极86的载体基板81安装在母基板上。并且，通过进行突出电极86的回流处理，将半导体封装PK51，PK52的层叠结构安装在母基板上。
这里，能够在基本去除半导体封装PK51，PK52之间的树脂15中包含的水分的状态下，进行突出电极86的回流处理。
因此，突出电极86回流时能够抑制树脂95的膨胀，能够防止半导体封装PK51，PK52彼此剥离。另外，突出电极86回流时进行突出电极93的再回流时，也能够维持半导体封装PK51，PK52用树脂95彼此固定的原样状态，能够防止半导体封装PK51，PK52之间的位置偏离。
图8(a)是表示本发明的第六实施方式的半导体装置的简要结构的平面图，图8(b)是表示本发明的第七实施方式的半导体装置的简要结构的平面图。
图8(a)中，在半导体封装101上设置有半导体芯片102。并且，经突出电极104保持在半导体芯片102上的形态，使半导体封装103安装在半导体封装101上。
并且半导体封装101，103之间设置树脂105，树脂105不与突出电极104接触地配置在半导体封装103的4个角上。突出电极104避开树脂105的配置区域配置在半导体封装103上。
由此，在半导体封装101，103之间的间隙狭窄的情况下，也能够在半导体封装101，103之间容易地填充树脂105。因此，能够抑制制造工序变复杂，并且能够防止层叠的半导体封装101，103的二次安装时位置偏离，同时抑制半导体封装101，103之间的剥离。另外，通过在半导体封装103的4个角上配置树脂105，能够由树脂105有效吸收施加在半导体封装103上的应力，能够提高半导体封装103的耐冲击性。
另外，在图8(b)中，在半导体封装201上搭在着半导体芯片202。并且，经突出电极204保持在半导体芯片202上的形态，使半导体封装203安装在半导体封装201上。
并且半导体封装201，203之间设置树脂205，树脂205不与突出电极204接触地配置在半导体封装203的边的中央。另外，突出电极204避开树脂205的配置区域配置在半导体封装203上。
由此，在半导体封装201，203之间的间隙狭窄的情况下，也能够在半导体封装201，203之间容易地填充树脂205。因此，能够抑制制造工序变复杂，并且能够防止层叠的半导体封装201，203的二次安装时位置偏离，同时能够抑制半导体封装201，203之间的剥离。
图9是表示本发明的第八实施方式的半导体装置的制造方法的一个例子的截面图。
在图9(a)中，半导体封装PK61上设置载体基板301，在载体基板301的两面上分别形成有岸面302a，302b。并且，载体基板301上倒装片安装半导体芯片303，在半导体芯片303上设置有用于倒装片安装的突出电极304。并且，在半导体芯片303上设置的突出电极304经各向异性导电片305ACF接合于岸面302b上。
另一方面，半导体封装PK62上设置载体基板311，在载体基板311的里面上形成岸面312，岸面312上设置有突出电极313。另外，载体基板311上安装半导体芯片，安装了半导体芯片的载体基板311用密封树脂314被密封。
并且，在半导体封装PK61上层叠半导体封装PK62的情况下，半导体封装PK62的岸面312上，作为突出电极313形成焊锡球的同时，向载体基板301的岸面302b上供给焊剂307。而且也可以向载体基板301的岸面302b上供给焊接膏，以替代供给焊剂307。也可以通过使用分散器等将树脂315供给载体基板301上的未配置岸面302b的区域。
接着如图9(b)所示，在半导体封装PK61上安装半导体封装PK62。并且通过进行突出电极313的回流处理使突出电极313熔融，将突出电极313接合在岸面302b上。这里将突出电极313接合在岸面302b的情况下，在A阶段状态(由于升温使树脂软化的状态)或B阶段状态(通过升温树脂粘度提高的状态)下维持树脂315为好。因此，通过突出电极313熔融时的表面张力能够将突出电极313自匹配地配置在岸面302b上，能够将半导体封装PK62高精度配置在半导体封装PK61上。并且，突出电极313与岸面302b接合时，在比突出电极313的回流时的温度低的温度下固化树脂315，将树脂315移动到C阶段状态(固化状态)。
这里，通过将树脂315设置在半导体封装PK61，PK62之间的间隙的一部分上能够确保树脂315中包含的水分逃离的间隙，能够用树脂315固定半导体封装PK61，PK62，并且能够减少树脂315中包含的水分的残留量。
在向半导体封装PK61上层叠半导体封装PK62之前，通过向半导体封装PK61上供给树脂315，即使在层叠后的半导体封装PK61，PK62之间的间隙狭窄的情况下，也能够在半导体封装PK61，PK62之间的任意位置上容易地配置树脂315。因此，考虑半导体芯片303和突出电极313的配置位置、向半导体封装PK61，PK62施加的应力等种种因素，能够容易地将树脂315设置在半导体封装PK61，PK62之间的一部分上，并且能够抑制制造工序变复杂，提高半导体封装PK61，PK62的层叠结构的可靠性。
接着如图9(c)所示，在载体基板301的里面上设置的岸面302a上形成用于将载体基板301安装在母基板上的突出电极306。将形成突出电极306的载体基板301安装在母基板上，通过进行突出电极306的回流处理将半导体封装PK61，PK62的层叠结构安装在母基板上。
这里，在基本去除半导体封装PK61，PK62之间的树脂315中包含的水分的状态下，进行突出电极306的回流处理。因此，突出电极306回流时能够抑制树脂315的膨胀，能够防止半导体封装PK61，PK62彼此剥离。突出电极306回流时进行突出电极313的再回流时也维持半导体封装PK61，PK62用树脂315彼此固定的原样状态，能够防止半导体封装PK61，PK62之间的位置偏离。
上述的半导体装置可以适用于例如液晶显示装置、便携电话、便携信息终端、摄像机、数码相机、MD(Mini Disc)播放器等的电子仪器，可以实现电子仪器的小型化、轻量化，并且提高电子仪器的可靠性。
另外，在上述实施方式中，举例说明了层叠半导体封装的方法，但本发明不限定于层叠半导体封装的方法，例如也可以层叠弹性表面波(SAW)元件等的陶瓷元件、光调制器和光开关等的光学元件、磁传感器或生物传感器等的各种传感器类等。

Claims (15)

1、一种半导体装置，其特征在于，包括：
搭载第一半导体芯片的第一半导体封装；
搭载第二半导体芯片的第二半导体封装；
突出电极，其连接上述第一半导体封装和上述第二半导体封装，以便使上述第二半导体封装保持在上述第一半导体芯片上；
树脂，其设置在上述第一半导体封装和上述第二半导体封装之间，以配置成避开上述第一半导体芯片的表面的至少一部分。
2、根据权利要求1所述的半导体装置，其特征在于，上述突出电极是焊锡球。
3、根据权利要求1或2所述的半导体装置，其特征在于，使上述树脂不接触上述突出电极，以配置在上述第一半导体封装和上述第二半导体封装之间。
4、根据权利要求3所述的半导体装置，其特征在于，上述树脂仅配置在上述第二半导体封装的角上。
5、根据权利要求3或4所述的半导体装置，其特征在于，上述第一半导体封装和上述第二半导体封装上对应上述树脂的配置位置设有突出电极的未配置区域。
6、根据权利要求1或2所述的半导体装置，其特征在于，上述树脂是在与上述突出电极的周围接触的状态下配置的。
7、根据权利要求6所述的半导体装置，其特征在于，上述树脂包含焊剂。
8、根据权利要求1～7中的任意1项所述的半导体装置，其特征在于，上述第一半导体封装包括第一载体基板和在上述第一载体基板上倒装片安装的第一半导体芯片；
上述第二半导体封装包括经上述突出电极安装在上述第一载体基板上以使之保持在上述第一半导体芯片上的第二载体基板、搭载在上述第二载体基板上的第二半导体芯片和密封上述第二半导体芯片的密封件。
9、根据权利要求8所述的半导体装置，其特征在于，上述第一半导体封装是在上述第一载体基板上倒装片安装上述第一半导体芯片的球栅阵列，上述第二半导体封装是模压密封上述第二载体基板上搭载的第二半导体芯片的球栅阵列或芯片尺寸封装。
10、一种电子设备，其特征在于，包括：
搭载第一电子部件的第一封装；
搭载第二电子部件的第二封装；
突出电极，其连接上述第一封装和上述第二封装，以便使上述第二封装保持在上述第一电子部件上；
树脂，其设置在上述第一封装和上述第二封装之间，以配置成避开上述第一电子部件的表面的至少一部分。
11、一种电子仪器，其特征在于，包括：
搭载第一半导体芯片的第一半导体封装；
搭载第二半导体芯片的第二半导体封装；
突出电极，其连接上述第一半导体封装和上述第二半导体封装，以便使上述第二半导体封装保持在上述第一半导体芯片上；
树脂，其设置在上述第一半导体封装和上述第二半导体封装之间，以配置成避开上述第一半导体芯片的表面的至少一部分；
母基板，其搭载连接上述第二半导体封装的上述第一半导体封装；
电子部件，经上述母基板连接上述第一半导体芯片和上述第二半导体芯片。
12、一种半导体装置的制造方法，其特征在于，包括：
经突出电极连接搭载第一半导体芯片的第一半导体封装和搭载第二半导体芯片的第二半导体封装的工序；
以避开上述第一半导体芯片的表面的至少一部分的形态，在上述第一半导体封装和上述第二半导体封装之间设置树脂的工序。
13、根据权利要求12所述的半导体装置的制造方法，其特征在于，上述树脂不与上述突出电极接触地配置在上述第一半导体封装和上述第二半导体封装之间。
14、根据权利要求13所述的半导体装置的制造方法，其特征在于，上述树脂仅配置在上述第二半导体封装的角上。
15、一种半导体装置的制造方法，其特征在于，包括：
向第一半导体封装上设置的岸面供给加入树脂的焊剂的工序；
在供给上述加入树脂的焊剂的岸面上配置第二半导体封装上设置的焊锡球的工序；
通过进行回流处理使上述焊锡球熔融，将上述焊锡球接合于上述岸面上的同时，使加入到上述加入树脂的焊剂的树脂，沿着上述焊锡球的表面攀缘上去的工序。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN105489592A (zh) * 2014-10-06 2016-04-13 三星电子株式会社 半导体器件封装件、层叠封装件和计算装置
CN105936183A (zh) * 2015-03-05 2016-09-14 精工爱普生株式会社 电子装置以及电子装置的制造方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3786103B2 (ja) * 2003-05-02 2006-06-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP4040644B2 (ja) * 2005-07-28 2008-01-30 シャープ株式会社 半田付け実装構造の製造方法および半田付け実装方法
US20070063344A1 (en) * 2005-09-22 2007-03-22 Chun-Hung Lin Chip package structure and bumping process
JP4528715B2 (ja) * 2005-11-25 2010-08-18 株式会社東芝 半導体装置及びその製造方法
JP4751714B2 (ja) * 2005-12-22 2011-08-17 オリンパス株式会社 積層実装構造体
US20100155964A1 (en) * 2006-04-27 2010-06-24 Sumitomo Bakelite Co., Ltd. Adhesive Tape, Semiconductor Package and Electronics
WO2008023452A1 (fr) * 2006-08-25 2008-02-28 Sumitomo Bakelite Co., Ltd. Bande adhésive, structure de jonction, et ensemble semi-conducteur
JP5085081B2 (ja) * 2006-09-22 2012-11-28 パナソニック株式会社 電子部品実装構造体
JP5044189B2 (ja) * 2006-10-24 2012-10-10 リンテック株式会社 複合型半導体装置の製造方法、及び複合型半導体装置
KR101329355B1 (ko) 2007-08-31 2013-11-20 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
KR100881400B1 (ko) * 2007-09-10 2009-02-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
US7842552B2 (en) * 2007-10-12 2010-11-30 International Business Machines Corporation Semiconductor chip packages having reduced stress
US8193624B1 (en) * 2008-02-25 2012-06-05 Amkor Technology, Inc. Semiconductor device having improved contact interface reliability and method therefor
US8779570B2 (en) * 2008-03-19 2014-07-15 Stats Chippac Ltd. Stackable integrated circuit package system
JP2009278064A (ja) * 2008-04-17 2009-11-26 Panasonic Corp 半導体装置とその製造方法
CN102027584B (zh) * 2008-05-16 2013-03-27 住友电木株式会社 半导体组件的制造方法和半导体组件
KR101481577B1 (ko) * 2008-09-29 2015-01-13 삼성전자주식회사 잉크 젯 방식의 댐을 구비하는 반도체 패키지 및 그 제조방법
JP2010212421A (ja) * 2009-03-10 2010-09-24 Panasonic Corp 半導体装置
JP5214554B2 (ja) * 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
FR2974234A1 (fr) * 2011-04-14 2012-10-19 St Microelectronics Grenoble 2 Assemblage de dispositifs a composants semiconducteurs empiles
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
KR20120131530A (ko) 2011-05-25 2012-12-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
DE102013103301B4 (de) 2012-04-13 2023-01-26 Samsung Electronics Co., Ltd. Elektronische Gehäuse-auf-Gehäuse-Vorrichtungen mit Abdichtungsschichten und Verfahren zum Herstellen derselben
KR102000678B1 (ko) 2012-10-26 2019-07-16 삼성전자주식회사 반도체 장치 및 이를 제조하는 방법
US9287204B2 (en) 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
US20140367854A1 (en) * 2013-06-17 2014-12-18 Broadcom Corporation Interconnect structure for molded ic packages
US9368458B2 (en) * 2013-07-10 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Die-on-interposer assembly with dam structure and method of manufacturing the same
US20150221570A1 (en) * 2014-02-04 2015-08-06 Amkor Technology, Inc. Thin sandwich embedded package
US9613933B2 (en) * 2014-03-05 2017-04-04 Intel Corporation Package structure to enhance yield of TMI interconnections
US10879211B2 (en) 2016-06-30 2020-12-29 R.S.M. Electron Power, Inc. Method of joining a surface-mount component to a substrate with solder that has been temporarily secured
DE102017212796A1 (de) * 2017-07-26 2019-01-31 Robert Bosch Gmbh Elektrische Baugruppe
US11121089B2 (en) * 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US135243A (en) * 1873-01-28 Improvement in machines for pressing and shaping cigar-fillers
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5340771A (en) * 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
GB9312328D0 (en) * 1993-06-15 1993-07-28 Lexor Technology Limited A method of brazing
KR970000214B1 (ko) 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
JPH0817860A (ja) * 1994-06-30 1996-01-19 Oki Electric Ind Co Ltd 電子部品の製造方法
JPH08115989A (ja) * 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
JP3311215B2 (ja) 1995-09-28 2002-08-05 株式会社東芝 半導体装置
AU7096696A (en) * 1995-11-28 1997-06-19 Hitachi Limited Semiconductor device, process for producing the same, and packaged substrate
JP2806357B2 (ja) 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
JPH1084076A (ja) 1996-09-05 1998-03-31 Hitachi Ltd 半導体装置およびその製造方法
JPH10163386A (ja) * 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US6492719B2 (en) * 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP2964983B2 (ja) * 1997-04-02 1999-10-18 日本電気株式会社 三次元メモリモジュール及びそれを用いた半導体装置
JPH10294423A (ja) * 1997-04-17 1998-11-04 Nec Corp 半導体装置
JP3564946B2 (ja) 1997-06-09 2004-09-15 株式会社デンソー フリップチップの実装構造
US6120885A (en) * 1997-07-10 2000-09-19 International Business Machines Corporation Structure, materials, and methods for socketable ball grid
US6274929B1 (en) * 1998-09-01 2001-08-14 Texas Instruments Incorporated Stacked double sided integrated circuit package
JP3230487B2 (ja) 1998-04-20 2001-11-19 住友金属工業株式会社 三次元パッケージおよびその製造方法
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
JP2000040713A (ja) 1998-07-23 2000-02-08 Citizen Watch Co Ltd 半導体パッケージの製造方法
JP3201353B2 (ja) * 1998-08-04 2001-08-20 日本電気株式会社 半導体装置とその製造方法
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
TW434767B (en) * 1998-09-05 2001-05-16 Via Tech Inc Package architecture of ball grid array integrated circuit device
US6274937B1 (en) * 1999-02-01 2001-08-14 Micron Technology, Inc. Silicon multi-chip module packaging with integrated passive components and method of making
US6573119B1 (en) * 1999-02-17 2003-06-03 Hitachi, Ltd. Semiconductor device and method of manufacture thereof
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
US6023097A (en) * 1999-03-17 2000-02-08 Chipmos Technologies, Inc. Stacked multiple-chip module micro ball grid array packaging
JP2000286380A (ja) 1999-03-30 2000-10-13 Nec Corp 半導体の実装構造および製造方法
JP2001015633A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体装置
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
TW415056B (en) * 1999-08-05 2000-12-11 Siliconware Precision Industries Co Ltd Multi-chip packaging structure
JP2001156212A (ja) * 1999-09-16 2001-06-08 Nec Corp 樹脂封止型半導体装置及びその製造方法
JP3668074B2 (ja) 1999-10-07 2005-07-06 松下電器産業株式会社 半導体装置およびその製造方法
US6373142B1 (en) * 1999-11-15 2002-04-16 Lsi Logic Corporation Method of adding filler into a non-filled underfill system by using a highly filled fillet
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3881488B2 (ja) * 1999-12-13 2007-02-14 株式会社東芝 回路モジュールの冷却装置およびこの冷却装置を有する電子機器
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6731009B1 (en) * 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
JP2001339011A (ja) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001284382A (ja) 2000-03-28 2001-10-12 Nec Corp はんだバンプ形成方法、フリップチップ実装方法及び実装構造体
US6531341B1 (en) * 2000-05-16 2003-03-11 Sandia Corporation Method of fabricating a microelectronic device package with an integral window
JP2001352035A (ja) * 2000-06-07 2001-12-21 Sony Corp 多層半導体装置の組立治具及び多層半導体装置の製造方法
US6461881B1 (en) * 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
JP2002057273A (ja) 2000-08-07 2002-02-22 Orient Semiconductor Electronics Ltd 集積回路パッケージ用積み重ねダイセット
JP4570809B2 (ja) * 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
JP2002134650A (ja) * 2000-10-23 2002-05-10 Rohm Co Ltd 半導体装置およびその製造方法
JP4451559B2 (ja) 2000-10-26 2010-04-14 パナソニック株式会社 半導体装置およびその製造方法
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
JP3854819B2 (ja) 2001-04-27 2006-12-06 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4629912B2 (ja) 2001-05-25 2011-02-09 富士通セミコンダクター株式会社 はんだバンプの形成方法
JP2003007972A (ja) 2001-06-27 2003-01-10 Toshiba Corp 積層型半導体装置及びその製造方法
US6686225B2 (en) * 2001-07-27 2004-02-03 Texas Instruments Incorporated Method of separating semiconductor dies from a wafer
US6881609B2 (en) * 2001-09-07 2005-04-19 Peter C. Salmon Component connections using bumps and wells
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP3866591B2 (ja) * 2001-10-29 2007-01-10 富士通株式会社 電極間接続構造体の形成方法および電極間接続構造体
JP2003218150A (ja) * 2002-01-23 2003-07-31 Fujitsu Media Device Kk モジュール部品
CN1251318C (zh) * 2002-02-25 2006-04-12 精工爱普生株式会社 半导体芯片、半导体装置和它们的制造方法以及使用它们的电路板和仪器
JP2003318361A (ja) 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
US6903458B1 (en) * 2002-06-20 2005-06-07 Richard J. Nathan Embedded carrier for an integrated circuit chip
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
JP4072020B2 (ja) * 2002-08-09 2008-04-02 日本電波工業株式会社 表面実装水晶発振器
JP2004079923A (ja) 2002-08-22 2004-03-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2004179232A (ja) * 2002-11-25 2004-06-24 Seiko Epson Corp 半導体装置及びその製造方法並びに電子機器
JP4086657B2 (ja) 2002-12-27 2008-05-14 富士通株式会社 積層型半導体装置
JP4475875B2 (ja) 2003-02-26 2010-06-09 イビデン株式会社 プリント配線板
JP3917946B2 (ja) 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
JP4096774B2 (ja) * 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487059A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 堆叠式封装结构
CN105489592A (zh) * 2014-10-06 2016-04-13 三星电子株式会社 半导体器件封装件、层叠封装件和计算装置
CN105489592B (zh) * 2014-10-06 2019-05-03 三星电子株式会社 半导体器件封装件、层叠封装件和计算装置
CN105936183A (zh) * 2015-03-05 2016-09-14 精工爱普生株式会社 电子装置以及电子装置的制造方法

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