CN1542963A - 半导体装置及其制造方法、电子设备、电子仪器 - Google Patents
半导体装置及其制造方法、电子设备、电子仪器 Download PDFInfo
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- CN1542963A CN1542963A CNA2004100386412A CN200410038641A CN1542963A CN 1542963 A CN1542963 A CN 1542963A CN A2004100386412 A CNA2004100386412 A CN A2004100386412A CN 200410038641 A CN200410038641 A CN 200410038641A CN 1542963 A CN1542963 A CN 1542963A
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Abstract
防止层叠的半导体封装的二次安装时的位置偏离并且抑制半导体封装之间的剥离。在隔着突出电极(13)彼此接合的半导体封装PK1,PK2中,在半导体芯片(3)上层叠树脂以露出半导体芯片(3)的至少一部分,隔着树脂(15)将半导体封装PK2固定在半导体芯片(3)上。
Description
技术领域
本发明涉及半导体装置、电子设备、电子仪器和半导体装置的制造方法,尤其适用于半导体封装的层叠结构。
背景技术
以往的半导体封装中,例如像专利文献1所公开的那样,通过隔着焊锡球层叠半导体封装,实现空间节省。这里,在层叠的半导体封装之间填充树脂。
【专利文献1】
特开2002-170906号公报
但是以往的半导体封装中,隔着焊锡球层叠的半导体封装之间的整个空隙中填充树脂。因此,固化半导体封装之间填充的树脂时,树脂中包含的水分不能充分去除,半导体封装之间填充的树脂中仍残留水分。这样,层叠的半导体封装二次安装的回流时,半导体封装之间填充的树脂中包含的水分气化而膨胀,存在半导体封装之间产生剥离的问题。
因此,本发明的目的是提供一种可防止层叠的半导体封装二次安装时的位置偏离,并且抑制半导体封装之间的剥离的半导体装置、电子设备、电子仪器和半导体装置的制造方法。
发明内容
为解决上述问题,根据本发明的一个形式的半导体装置,其特征在于包括:装载第一半导体芯片的第一半导体封装;以配置在上述第一半导体芯片上的形态、被支持在上述第一半导体封装上的第二半导体封装;配置成上述第一半导体芯片的至少一部分露出、并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂。
由此,隔着第一半导体芯片上配置的树脂而固定第一半导体封装和第二半导体封装成为可能,第一半导体封装和第二半导体封装之间设置了树脂的情况下,也能够在第一半导体封装和第二半导体封装之间残留间隙。因此,能够容易去除第一半导体封装和第二半导体封装之间的树脂中包含的水分,二次安装时进行回流处理的情况下,能够抑制第一半导体封装和第二半导体封装之间的树脂膨胀。其结果是能够抑制第一半导体封装和第二半导体封装之间的剥离,并且用树脂固定第一半导体封装和第二半导体封装,能够防止第一半导体封装和第二半导体封装之间的位置偏离。
根据本发明的一个形式的半导体装置,其特征在于包括:装载第一半导体芯片的第一半导体封装;以端部配置在上述第一半导体芯片上的形态、被支持在上述第一半导体封装上的第二半导体封装;配置成上述第一半导体芯片的至少一部分露出、并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂。
由此,隔着第一半导体芯片上配置的树脂,固定第一半导体封装和第二半导体封装成为可能,第一半导体封装和第二半导体封装之间设置树脂的情况下,也能够在第一半导体封装和第二半导体封装之间残留间隙,同时在同一第一半导体芯片上能够配置多个半导体封装。因此,能够进一步缩小安装面积,并且能够抑制第一半导体封装和第二半导体封装之间的剥离,同时,能够防止层叠的第一半导体封装和第二半导体封装的二次安装时的位置偏离。
根据本发明的一个形式的半导体装置,其特征在于上述树脂仅设置在上述第二半导体封装和上述第一半导体芯片的相对向面上。
由此,能够不使树脂与第一半导体封装接触、隔着配置在第一半导体芯片上的树脂有效地固定第一半导体封装和第二半导体封装。从而,能够抑制第一半导体封装和第二半导体封装之间的剥离,能够防止层叠的第一半导体封装和第二半导体封装的二次安装时的位置偏离。
另外,根据本发明的一个形式的半导体装置,其特征在于上述树脂设置在上述第一半导体芯片的中央部。
由此,隔着突出电极电连接第一半导体封装和第二半导体封装的情况下,也能够在从突出电极离开的位置上配置树脂。因此,能够抑制树脂的伸缩影响波及突出电极,并能够提高温度循环等的耐久性。
根据本发明的一个形式的半导体装置,其特征在于上述树脂中混入有填充物。
由此,能够容易控制树脂的粘度,防止树脂的液态下垂,容易控制树脂的存在范围。
根据本发明的一个形式的半导体装置,其特征在于:上述第一半导体封装具有:倒装片安装上述第一半导体芯片的第一载体基板,和在上述第一半导体芯片和上述第一载体基板之间设置的树脂层,上述第二半导体封装具有:第二半导体芯片;安装上述第二半导体芯片的第二载体基板;接合上述第一载体基板、在上述第一半导体芯片上保持上述第二载体基板的突出电极;和密封上述第二半导体芯片的密封件。
由此,第一半导体封装和第二半导体封装种类不同的情况下,也防止层叠的第一半导体封装和第二半导体封装的二次安装时的位置偏离,并且,能够抑制第一半导体封装和第二半导体封装之间的剥离,能节省空间,并且可以提高第一半导体封装和第二半导体封装之间的连接可靠性。
根据本发明的一个形式的半导体装置,其特征在于上述突出电极是焊锡球。
由此,通过进行回流处理,能够电连接第一半导体封装和第二半导体封装,能够在第一半导体封装上高效安装第二半导体封装。
根据本发明的一个形式的半导体装置,其特征在于上述第一半导体芯片和上述第二半导体封装之间设置的树脂,与上述第一半导体芯片和上述第一载体基板之间设置的树脂层相比,弹性系数低。
由此,施加在第一半导体芯片上的冲击能够被第一半导体封装和第二半导体封装之间设置的树脂有效吸收。这样,能够提高半导体芯片的耐冲击性,确保半导体芯片的可靠性,并且层叠多个半导体芯片。
根据本发明的一个形式的半导体装置,其特征在于上述第一半导体封装是在上述第一载体基板上倒装片安装上述第一半导体芯片的球栅阵列,上述第二半导体封装是模压密封上述第二载体基板上装载的第二半导体芯片的球栅阵列或芯片大小封装。
由此,使用通用封装的情况下,也能够防止层叠的半导体封装二次安装时的位置偏离,并且抑制第一半导体封装和第二半导体封装之间的剥离,不恶化生产效率,提高不同种类封装之间的连接可靠性。
根据本发明的一个形式的电子设备,其特征在于包括:装载电子零件的第一封装;以在上述电子零件上配置的形态、在上述第一封装上被支持的第二封装;配置成上述电子零件的至少一部分露出、并被设置在上述电子零件和上述第二封装之间的树脂。
由此,能够隔着电子零件上配置的树脂固定第一封装和第二封装,在第一封装和第二封装之间设置了树脂的情况下,也能够在第一封装和第二封装之间残留间隙。这样,能够抑制第一封装和第二封装之间的剥离,并且用树脂固定第一封装和第二封装,防止第一封装和第二封装之间的位置偏离。
根据本发明的一个形式的电子仪器,其特征在于包括:装载第一半导体芯片的第一半导体封装;以在上述第一半导体芯片上配置的形态、在上述第一半导体封装上被支持的第二半导体封装;配置成上述第一半导体芯片的至少一部分露出、并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂;装载支持上述第二半导体封装的上述第一半导体封装的母基板;隔着上述母基板被连接在上述第一半导体芯片的电子零件。
由此,能够抑制层叠的半导体封装的可靠性恶化,并且防止二次安装时的半导体封装的位置偏离,可以实现电子仪器的小型化、轻量化,并且提高电子设备的可靠性。
根据本发明的一个形式的半导体装置的制造方法,其特征在于包括:向装载在第一半导体封装上的第一半导体芯片供给树脂的工序;以上述第一半导体芯片的至少一部分从上述树脂露出的形态、将装载了第二半导体芯片的第二半导体封装安装在上述第一半导体封装上的工序。
由此,第一半导体封装和第二半导体封装之间填充树脂的情况下,也能够在第一半导体封装和第二半导体封装之间残留间隙,能够防止层叠的半导体封装二次安装时的位置偏离,并且抑制第一半导体封装和第二半导体封装之间的剥离。
附图说明
图1是表示第一实施方式的半导体装置的示意结构的截面图;
图2是表示图1的半导体装置的制造方法的一例的截面图;
图3是表示第二实施方式的半导体装置的示意结构的截面图;
图4是表示第三实施方式的半导体装置的示意结构的截面图;
图5是表示第四实施方式的半导体装置的示意结构的截面图;
图6是表示第五实施方式的半导体装置的示意结构的截面图。
图中,
PK1、PK2、PK11、PK12、PK21、PK22、PK31、PK32、PK41、PK42—半导体封装,1、11、21、31、41、61、71、81、91、101、201—载体基板,2a、2b、9、12、22a、22c、32a、32c、42a、42c、62a、62b、72、82、92a、92c、102a、102c、202a、202c—岸面,3、23、33a、33b、43、51、63、93、103a、103b、103c、203a、203b、203c—半导体芯片,4、13、24、26、36、44、46、58、64、66、73、83、94、96、106、206—突出电极,5、25、45、65、95—各向异性导电片,7—焊剂,14、37、74、84、107、207—密封树脂,15、38、59、67、97—树脂,22b、32b、42b、92b、102b、202b—内部配线,34a、34b、104a、104b、104c、204a、204b、204c—粘接层,35a、35b、105a、105b、105c、205a、205b、205c—导电性线,52—电极片垫片,53—绝缘膜,54—应力缓和层,55—再配置配线,56—焊料抗蚀剂层,57—开口部。
具体实施方式
下面参考附图说明本发明的实施方式的半导体装置及其制造方法。
图1是表示本发明的第一实施方式的半导体装置的示意结构的截面图。
图1中,半导体封装PK1上设置载体基板1,载体基板1的两面上分别形成有岸面2a,2b。并且,载体基板1上倒装片安装半导体芯片3,在半导体芯片3上设有用于倒装片安装的突出电极4。并且,半导体芯片3上设置的突出电极4隔着各向异性导电片5,ACF(各向异性导电膜)接合于岸面2b上。
另一方面,半导体封装PK2上设置载体基板11,载体基板11的背面上形成岸面12,岸面12上设有突出电极13。另外,载体基板11上安装半导体芯片,已安装半导体芯片的载体基板11用密封树脂14被密封。另外,载体基板11上可以安装成线焊接连接的半导体芯片,也可以为倒装片安装半导体芯片,也可以安装成半导体芯片的层叠结构。
并且,通过载体基板1上设置的岸面2b上接合突出电极13,以使载体基板11配置在半导体芯片3上的形态,在半导体封装PK1上安装了半导体封装PK2。
另外,半导体芯片3上配置树脂15,以露出半导体芯片3的至少一部分,而半导体封装PK2隔着树脂15固定在半导体芯片3上。这里,作为树脂15,可以使用树脂膏或树脂片之一。
由此隔着半导体芯片3上设置的树脂15能够固定半导体封装PK1和半导体封装PK2,在半导体封装PK1,PK2之间设置树脂15的情况下,也能够在半导体封装PK1,PK2之间残留间隙。因此,能够容易去除半导体封装PK1,PK2之间的树脂15中包含的水分,二次安装时进行突出电极6的回流处理时,也能够抑制半导体封装PK1,PK2之间的树脂15膨胀。其结果,能够抑制半导体封装PK1,PK2之间的剥离,并且能够用树脂15固定半导体封装PK1和半导体封装PK2,防止半导体封装PK1,PK2之间的位置偏离。
树脂15也可以仅设置在半导体封装PK2和半导体芯片3的相对向面上。由此,能够不使树脂15与半导体封装PK1接触、隔着配置在半导体芯片3上的树脂15有效固定半导体封装PK1和半导体封装PK2,能够抑制半导体封装PK1和半导体封装PK2之间的剥离,并且能够防止层叠的半导体封装PK1和半导体封装PK2的二次安装时的位置偏离。
树脂15可以设置在半导体芯片15的中央部。由此,隔着突出电极13电连接半导体封装PK1和半导体封装PK2的情况下,也能够在从突出电极13离开的位置上配置树脂15。这样,能够抑制树脂15的伸缩影响波及突出电极13,能够提高温度循环等的耐久性。
半导体芯片3和半导体封装PK2之间设置的树脂15,与半导体芯片3和载体基板1之间设置的各向异性导电片5相比,弹性系数低为好。由此,施加在半导体芯片3上的冲击能够被树脂15有效吸收。这样,能够提高半导体芯片3的耐冲击性,确保半导体芯片3的可靠性,并且层叠半导体封装PK1,PK2。
树脂15中也可以混入氧化硅、氧化铝等的填充物。由此,能够容易控制树脂15的粘度,防止树脂15的液态下垂,容易控制树脂15的存在范围。
半导体芯片3上的树脂15也可以仅配置在1个位置上,但也可以分散配置在半导体芯片3上。这里,通过将树脂15分散配置到半导体芯片3上,能够在半导体芯片3上确保用于树脂15中包含的水分逃离的路径,在半导体芯片3和半导体封装PK2之间的间隙狭窄的情况下也能够减少树脂15中包含的水分。
作为载体基板1,11,例如可以使用两面基板、多层配线基板、叠放基板、带基板或膜基板等,作为载体基板1,11的材质,可以使用例如聚酰胺树脂、玻璃环氧树脂、BT树脂、芳基聚酰胺和环氧树脂的复合物或陶瓷等。作为突出电极4,6,13,可以使用例如由Au块、焊锡材料等覆盖的Cu块,Ni块或焊锡球等。
另外,在隔着突出电极13彼此接合半导体封装PK1,PK2的情况下,可以使用焊接接合、合金接合等的金属接合,或使用ACF接合、NCF(非导电膜)接合、ACP(各向异性导电膏)接合、NCP(非导电膏)接合等的压接接合。在上述实施方式中,说明了在隔着突出电极4在载体基板1上倒装片安装半导体芯片3的情况下使用ACF接合的方法,但也可以使用NCF接合、ACP接合、NCP接合等的压接接合,也可以使用焊锡接合、合金接合等的金属接合。
图2是表示图1的半导体装置的制造方法的一个例子的截面图。
在图2(a)中,半导体封装PK1上层叠半导体封装PK2的情况下,在半导体封装PK2的岸面12上作为突出电极13形成焊接球,同时向载体基板1的岸面2b上供给焊剂7。通过使用分散器等将树脂15供给半导体芯片3上。
接着如图2(b)所示,在半导体封装PK1上安装半导体封装PK2。并且,通过进行突出电极13的回流处理使突出电极13熔融,将突出电极13接合在岸面2b上。
这里,将突出电极13接合在岸面2b上时,最好将树脂15维持在A阶段状态(通过升温软化树脂的状态)或B阶段状态(通过升温提高树脂粘度的状态)。由此,通过突出电极13熔融时的表面张力,能够将突出电极13自我匹配地配置在岸面2b上,能够在半导体封装PK1上精确配置半导体封装PK2。并且,将突出电极13接合在岸面2b上时,在比突出电极13的回流时的温度低的温度下固化树脂15,将树脂15移动到C阶段状态(固化状态)。
这里,通过在半导体芯片3上设置树脂15,以使半导体芯片3的至少一部分露出,能够确保树脂15中包含的水分逃离用的间隙,并且隔着半导体芯片3彼此固定半导体封装PK1,PK2,同时减少树脂15中包含的水分的残留量。
接着如图2(c)所示,在载体基板1的背面上设置的岸面2a上形成用于将载体基板1安装在母基板8上的突出电极6。
接着如图2(d)所示,将形成突出电极6的载体基板1安装在母基板8上。并且,通过进行突出电极6的回流处理将突出电极6接合在母基板8的岸面9上。
这里,通过在半导体芯片3上设置树脂15,以使半导体芯片3的至少一部分露出,可以在基本去除半导体封装PK1,PK2之间的树脂15中包含的水分的状态下,进行突出电极6的回流处理。这样突出电极6回流时能够抑制树脂15膨胀,能够防止半导体封装PK1,PK2彼此剥离。而且,在突出电极6回流时进行突出电极13的再回流的情况下,也能够维持用树脂15彼此固定半导体封装PK1,PK2的原样状态,能够防止半导体封装PK1,PK2之间的位置偏离。
在上述实施方式中,说明了为了半导体封装PK2安装在半导体封装PK1上,在载体基板1的岸面2b上设置突出电极13的同时,在载体基板11的岸面12上供给焊剂7的方法,但载体基板1的岸面2b上供给焊剂7的同时,也可以在载体基板11的岸面12上设置突出电极13。也可以使用焊锡膏替代焊剂7。另外,说明了通过使用分散器等向半导体芯片3上供给膏状的树脂15的方法,但也可以向半导体芯片3上供给片状的树脂15。
图3是表示本发明的第二实施方式的半导体装置的简要结构的截面图。
图3中,半导体封装PK11上设置载体基板21,载体基板21的两面上分别形成岸面22a,22c,同时载体基板21内形成内部配线22b。并且,载体基板21上倒装片安装半导体芯片23,在半导体芯片23上设有用于倒装片安装的突出电极24。并且,半导体芯片23上设置的突出电极24隔着各向异性导电片25ACF接合在岸面22c上。而且载体基板21的背面设置的岸面22a上设有用于将载体基板21安装在母基板上的突出电极26。
另一方面,半导体封装PK12上设置载体基板31,载体基板31的两面上分别形成岸面32a,32c,同时,载体基板31内形成有内部配线32b。并且,载体基板31上隔着粘接层34a正片安装半导体芯片33a,半导体芯片33a隔着导电性线35a,线焊接连接在岸面32c。另外,半导体芯片33a上,以避开导电性线35a的形态正片安装半导体芯片33b,半导体芯片33b隔着粘接层34b固定在安装半导体芯片33a上,同时隔着导电性线35b线焊接连接于岸面32c。
载体基板31的背面上设置的岸面32a上,以使载体基板31保持在半导体芯片23上的形态设有为了将载体基板31安装在载体基板21上的突出电极36。这里,突出电极36避开半导体芯片23的装载区域的形态而配置,例如可以在载体基板31的背面周围配置突出电极36。并且在载体基板21上设置的岸面22c上接合突出电极36使之载体基板31安装在载体基板21上。
在半导体芯片33a,33b的安装面侧的载体基板31上设置密封树脂37,通过该密封树脂37密封了半导体芯片33a,33b。用密封树脂37密封半导体芯片33a,33b的情况下,可以通过使用例如环氧树脂等的热固化树脂的模压成型等进行。
在半导体芯片23上配置树脂38以使露出半导体芯片23的至少一部分,而半导体封装PK12隔着树脂38固定在半导体芯片23上。
由此,即使层叠不同种类封装的情况下,在隔着突出电极36连接的载体基板21,31之间仍残留间隙的状态下,能够在载体基板21,31之间设置树脂38。因此,安装大小或种类不同的半导体芯片23,33a,33b时可节省空间,同时可防止层叠的半导体封装PK11,PK12在2次安装时位置偏离,并且能够抑制半导体封装PK11,PK12之间的剥离。
图4是表示本发明的第三实施方式的半导体装置的简要结构的截面图。
图4中,半导体封装PK21上设置载体基板41,载体基板41的两面上分别形成岸面42a,42c,同时载体基板41内形成内部配线42b。并且,载体基板41上倒装片安装半导体芯片43,半导体芯片43上设有用于倒装片安装的突出电极44。并且,半导体芯片43上设置的突出电极44隔着各向异性导电片45ACF接合在岸面42c上。另外,载体基板41的背面设置的岸面42a上设有用于将载体基板41安装在母基板上的突出电极46。
另一方面,半导体封装PK22上设置半导体芯片51,半导体芯片51上设置电极垫片52的同时,使电极垫片52露出的形态,设置绝缘膜53。并且半导体芯片51上露出电极垫片52、形成应力缓和层54,电极垫片52上形成有在应力缓和层54上延伸的再配置配线55。并且,再配置配线55上形成焊接抗蚀剂膜56,焊接抗蚀剂膜56上形成在应力缓和层54中露出再配置配线55的开口部57。并且隔着开口部57露出的再配置配线55上设有用于将半导体芯片51面朝下安装在载体基板41上的突出电极58以使半导体封装PK32保持在半导体芯片53上。
这里,突出电极58避开半导体芯片43的装载区域的形态配置,例如可以在半导体芯片51的周围配置突出电极58。并且,在载体基板41上设置的岸面42c上接合突出电极58,将半导体芯片PK22安装在载体基板41上。
另外,半导体芯片43上配置树脂59以露出半导体芯片43的至少一部分,而半导体芯片PK22隔着树脂59固定在半导体芯片43上。
由此,在半导体封装PK21上层叠W-CSP(晶片级一芯片大小封装)时,在隔着突出电极58接合的载体基板41和半导体芯片51之间仍残留间隙的状态下,能够在载体基板41和半导体芯片51之间设置树脂59。因此,半导体芯片43,51的种类或大小不同的情况下也不用在半导体芯片43,51之间插入载体基板,在半导体芯片43上3维安装半导体芯片51,同时防止层叠的半导体封装PK21,PK22在2次安装时位置偏离,并且抑制半导体封装PK21,PK22之间的剥离。其结果是抑制3维安装的半导体芯片43,51的可靠性恶化,并且抑制半导体芯片43,51层叠时的高度增大,实现半导体芯片43,51安装时节省空间。
图5是表示本发明的第四实施方式的半导体装置的简要结构的截面图。
图5中,半导体封装PK31上设置载体基板61,载体基板61的两面上分别形成有岸面62a,62b。并且,载体基板61上倒装片安装半导体芯片63,半导体芯片63上设有用于倒装片安装的突出电极64。并且,半导体芯片63上设置的突出电极64隔着各向异性导电片65ACF接合在岸面62b上。
另一方面,半导体封装PK32,PK33上分别设置载体基板71,81,载体基板71,81的背面上分别形成岸面72,82,岸面72,82上分别设有焊锡球等的突出电极73,83。载体基板71,81上分别安装半导体芯片,安装半导体芯片的载体基板71,81分别用密封树脂74,84密封。
并且,通过载体基板61上设置的岸面62b上分别接合突出电极73,83将载体基板71,81的端部分别配置在半导体芯片63上,将多个半导体封装PK32,PK33安装在半导体封装PK31上。
另外,半导体芯片63上配置树脂67以露出半导体芯片63的至少一部分,半导体封装PK32,PK33的端部隔着树脂67固定在半导体芯片63上。
由此,隔着半导体芯片63上配置的树脂67能够在半导体封装PK31上统一固定多个半导体封装PK32,PK33,即使在半导体封装PK32,PK33和半导体封装PK31之间设置了树脂67的情况下,也能够抑制制造工序复杂化,并且能够在半导体封装PK32,PK33和半导体封装PK31之间残留间隙。因此,可进一步缩小安装面积,并且抑制半导体封装PK32,PK33和半导体封装PK31之间的剥离,同时防止半导体封装PK31,PK32,PK33在二次安装时位置偏离。
半导体芯片63和半导体封装PK32,PK33之间分别设置树脂67的情况下,也可以在向半导体芯片63供给树脂67后,向半导体芯片63上分别配置半导体封装PK32,PK33。也可以在向半导体芯片63上分别配置半导体封装PK32,PK33后隔着半导体封装PK32,PK33之间的间隙向半导体芯片63上供给树脂67。
图6是表示本发明的第五实施方式的半导体装置的简要结构的截面图。
图6中,半导体封装PK41上设置载体基板91,载体基板91的两面上分别形成岸面92a,92b,同时载体基板91内形成有内部配线92b。并且,载体基板91上倒装片安装半导体芯片93,半导体芯片93上设有用于倒装片安装的突出电极94。并且,半导体芯片93上设置的突出电极94隔着各向异性导电片95ACF接合在岸面92c上。载体基板91的背面上设置的岸面92a上设有用于将载体基板91安装到母基板的突出电极96。
另一方面,半导体封装PK42,PK43上分别设置载体基板101,201,载体基板101,201的背面上分别形成岸面102a,202a,同时,载体基板101,201的表面分别形成岸面102c,202c,载体基板101,201内分别形成内部配线102b,202b。
并且,载体基板101,201上分别隔着粘接层104a,204a各自正片安装半导体芯片103a,203a,半导体芯片103a,203a分别隔着导电线105a,205a各自线焊接连接岸面102c,202c。
另外,半导体芯片103a,203a上,避开导电线105a,205a分别正片安装半导体芯片103b,203b,半导体芯片103b,203b分别隔着粘接层104b,204b各自固定于半导体芯片103a,203a上,同时分别隔着导电线105b,205b各自线焊接连接在岸面102c,202c。另外,半导体芯片103b,203b上避开导电线105b,205b分别正片安装半导体芯片103c,203c,半导体芯片103c,203c分别隔着粘接层104c,204c各自固定于半导体芯片103b,203b,同时分别隔着导电线105c,205c各自线焊接连接在岸面102c,202c。
另外,载体基板101,201的背面上分别设置的岸面102a,202a上,以将载体基板101,201分别支持在半导体芯片93上的形态、分别设置用于将载体基板101,201安装在载体基板91上的突出电极106,206。这里突出电极106,206最好至少存在于载体基板101,201的4角上,例如可以按コ字状排列突出电极106,206。
并且通过在载体基板91上设置的岸面92c上分别接合突出电极106,206,使载体基板101,201的端部分别配置在半导体芯片93上的形态、将载体基板101,201分别安装在载体基板91上。
另外,在半导体芯片103a~103c、203a~203c的安装面侧的载体基板101,201上分别设置密封树脂107,207,通过该密封树脂107,207分别密封着半导体芯片103a~103c、203a~203c。
半导体芯片93上配置树脂97以露出半导体芯片93的至少一部分,半导体封装PK42,PK43的端部隔着树脂97固定在半导体芯片93上。
由此,在同一半导体芯片93上可配置多个半导体封装PK42,PK43,可缩小安装面积,并且实现不同种类的半导体芯片93,103a~103c、203a~203c的三维安装,同时抑制半导体封装PK42,PK43和半导体封装PK41之间的剥离,并且防止半导体封装PK41,PK42,PK43在二维安装时的位置偏离。
另外,上述的半导体装置可以适用于例如液晶显示装置、便携电话、便携信息终端、摄像机、数字相机、MD(Mini Disc)播放器等的电子仪器,可以实现电子仪器的小型化、轻量化,并且提高电子仪器的可靠性。
另外,在上述实施方式中,举例说明了层叠半导体封装的方法,但本发明不限定于层叠半导体封装的方法,例如可层叠弹性表面波(SAW)元件等的陶瓷元件、光调制器和光开关等的光学元件、磁传感器和生物传器等的各种传感器类等。
Claims (12)
1.一种半导体装置,其特征在于包括:
装载第一半导体芯片的第一半导体封装;
以配置在上述第一半导体芯片上的形态,支持在上述第一半导体封装上的第二半导体封装;
配置成上述第一半导体芯片的至少一部分露出,并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂。
2.一种半导体装置,其特征在于包括:
装载第一半导体芯片的第一半导体封装;
以端部配置在上述第一半导体芯片上的形态、支持在上述第一半导体封装上的第二半导体封装;
配置成上述第一半导体芯片的至少一部分露出,并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂。
3.根据权利要求1或2所述的半导体装置,其特征在于,上述树脂仅设置在上述第二半导体封装和上述第一半导体芯片的相对向面上。
4.根据权利要求1~3中的任一项所述的半导体装置,其特征在于,上述树脂设置在上述第一半导体芯片的中央部。
5.根据权利要求1~4中的任一项所述的半导体装置,其特征在于上述树脂中混入了填充物。
6.根据权利要求1~5中的任一项所述的半导体装置,其特征在于:
上述第一半导体封装具有:
倒装片安装上述第一半导体芯片的第一载体基板,和
在上述第一半导体芯片和上述第一载体基板之间设置的树脂层,
上述第二半导体封装具有:
第二半导体芯片;
安装上述第二半导体芯片的第二载体基板;
接合上述第一载体基板、在上述第一半导体芯片上保持上述第二载体基板的突出电极;和
密封上述第二半导体芯片的密封件。
7.根据权利要求6所述的半导体装置,其特征在于,上述突出电极是焊锡球。
8.根据权利要求6或7所述的半导体装置,其特征在于,上述第一半导体芯片和上述第二半导体封装之间设置的树脂,与上述第一半导体芯片和上述第一载体基板之间设置的树脂层相比,弹性系数低。
9.根据权利要求6~8中的任一项所述的半导体装置,其特征在于,上述第一半导体封装是在上述第一载体基板上倒装片安装上述第一半导体芯片的球栅阵列,上述第二半导体封装是模压密封上述第二载体基板上装载的第二半导体芯片的球栅阵列或芯片大小封装。
10.一种电子设备,其特征在于包括:
装载电子零件的第一封装;
以在上述电子零件上配置的形态、在上述第一封装上被支持的第二封装;
配置成上述电子零件的至少一部分露出、并设置在上述电子零件和上述第二封装之间的树脂。
11.一种电子仪器,其特征在于包括:
装载了第一半导体芯片的第一半导体封装;
以在上述第一半导体芯片上配置的形态、在上述第一半导体封装上被支持的第二半导体封装;
配置成上述第一半导体芯片的至少一部分露出、并被设置在上述第一半导体芯片和上述第二半导体封装之间的树脂;
装载支持上述第二半导体封装的上述第一半导体封装的母基板;
隔着上述母基板连接上述第一半导体芯片的电子零件。
12.一种半导体装置的制造方法,其特征在于包括:
向装载在第一半导体封装上的第一半导体芯片供给树脂的工序;
使上述第一半导体芯片的至少一部分从上述树脂露出的形态、将装载了第二半导体芯片的第二半导体封装安装在上述第一半导体封装上的工序。
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JP2003127057A JP3786103B2 (ja) | 2003-05-02 | 2003-05-02 | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
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Cited By (3)
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CN103187405A (zh) * | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | 用于层叠封装器件减少应变的方法和装置 |
CN104880265A (zh) * | 2014-02-27 | 2015-09-02 | 精工爱普生株式会社 | 力检测装置、以及机械臂 |
CN110947434A (zh) * | 2018-09-26 | 2020-04-03 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
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JP5116268B2 (ja) * | 2005-08-31 | 2013-01-09 | キヤノン株式会社 | 積層型半導体装置およびその製造方法 |
US7829989B2 (en) * | 2005-09-07 | 2010-11-09 | Alpha & Omega Semiconductor, Ltd. | Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside |
CN102608736A (zh) * | 2006-07-21 | 2012-07-25 | 株式会社尼康 | 变焦透镜系统、成像设备和变焦透镜系统的变焦方法 |
JP2010212595A (ja) | 2009-03-12 | 2010-09-24 | Murata Mfg Co Ltd | パッケージ基板 |
KR101686199B1 (ko) | 2010-03-26 | 2016-12-14 | 삼성전자주식회사 | 반도체 패키지 구조물 |
US8963312B2 (en) * | 2010-05-11 | 2015-02-24 | Xintec, Inc. | Stacked chip package and method for forming the same |
JP6010880B2 (ja) * | 2011-04-15 | 2016-10-19 | 株式会社ニコン | 位置情報検出センサ、位置情報検出センサの製造方法、エンコーダ、モータ装置及びロボット装置 |
CN104637998B (zh) * | 2015-02-06 | 2017-06-30 | 清华大学 | 一种提高晶闸管抗干扰能力的方法 |
WO2019181589A1 (ja) * | 2018-03-23 | 2019-09-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
CN215300624U (zh) * | 2018-03-23 | 2021-12-24 | 株式会社村田制作所 | 高频模块和通信装置 |
JP2021106341A (ja) * | 2019-12-26 | 2021-07-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
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JPH09260436A (ja) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置 |
JP3798597B2 (ja) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
JP2001210761A (ja) * | 2000-01-24 | 2001-08-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3798620B2 (ja) * | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
DE10110203B4 (de) * | 2001-03-02 | 2006-12-14 | Infineon Technologies Ag | Elektronisches Bauteil mit gestapelten Halbleiterchips und Verfahren zu seiner Herstellung |
JP2003007962A (ja) * | 2001-06-19 | 2003-01-10 | Toshiba Corp | 半導体積層モジュール |
JP2003318361A (ja) * | 2002-04-19 | 2003-11-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004349495A (ja) * | 2003-03-25 | 2004-12-09 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
-
2003
- 2003-05-02 JP JP2003127057A patent/JP3786103B2/ja not_active Expired - Lifetime
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- 2004-04-27 CN CNB2004100386412A patent/CN100369249C/zh not_active Expired - Fee Related
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Cited By (5)
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CN103187405A (zh) * | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | 用于层叠封装器件减少应变的方法和装置 |
CN103187405B (zh) * | 2012-01-03 | 2018-09-14 | 台湾积体电路制造股份有限公司 | 用于层叠封装器件减少应变的方法和装置 |
CN104880265A (zh) * | 2014-02-27 | 2015-09-02 | 精工爱普生株式会社 | 力检测装置、以及机械臂 |
CN104880265B (zh) * | 2014-02-27 | 2020-01-07 | 精工爱普生株式会社 | 力检测装置、以及机械臂 |
CN110947434A (zh) * | 2018-09-26 | 2020-04-03 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
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JP3786103B2 (ja) | 2006-06-14 |
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JP2004335603A (ja) | 2004-11-25 |
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