JP2010212595A - パッケージ基板 - Google Patents
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/026—Multiple connections subassemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
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- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Abstract
【解決手段】ICなどが搭載される第1の主面4aを有するメインパッケージ本体4の第1の主面4aと反対側の第2の主面4b上に、実装用の複数の第1の接合材5が設けられており、メインパッケージ4内には、第1の接合材5に電気的に接続されている内部回路6が形成されており、第2の主面4b上に、複数の電子部品13を内蔵しているサブパッケージ3が配置されており、第2の主面4bからサブパッケージ3の第2の主面4bから最も遠い部分までの距離である厚み方向寸法Tが、第2の主面4bから第1の接合材5の第2の主面4bの端部までの距離である厚み方向寸法B以下とされている、パッケージ基板1。
【選択図】図1
Description
2…メインパッケージ
3…サブパッケージ
4…メインパッケージ本体
4a…第1の主面
4b…第2の主面
4c…凹部
5…第1の接合材
6…内部回路
7…第1の表面導体
8…第2の表面導体
8a…延長部
9…接続導電路
10…バンプ
11…IC
12…サブパッケージ本体
12a…第1の主面
12b…第2の主面
13…電子部品
14…セラミック焼結体
14a…第1の端面
14b…第2の端面
15…第1の外部電極
16…第2の外部電極
17…第1の内部電極
17a…開口部
18…第2の内部電極
18a…開口部
21…第1のパッド導体
22…第2のパッド導体
23…ビアホール導体
24…ビアホール導体
25…支持体
26…金属箔
26a…導体
27…接着剤
28…プリプレグシート
29…金属箔
29a…導体
30…導電性接着剤
31…サブパッケージ
32…電子部品
33…第1のビアホール導体
34…第2のビアホール導体
35…導電性接着剤
36…第1の外部電極
37…第2の外部電極
41…電子部品
42…セラミック焼結体
42a…上面
42b…下面
43…第1の内部電極
43a…第1の内部電極
43b…第1の内部電極
44…第2の内部電極
44a…第2の内部電極
44b…第2の内部電極
45a…第1の外部電極
45b…第2の外部電極
45c…第3の外部電極
45d…第4の外部電極
45e…第5の外部電極
45f…第6の外部電極
45g…第7の外部電極
45h…第8の外部電極
51…パッケージ基板
101…コンデンサ
102…パッケージ基板
102a…空間
103…ダイ
104…バンプ
Claims (8)
- 対向し合っている第1,第2の主面を有するメインパッケージ本体と、
前記メインパッケージ本体の前記第2の主面に設けられた第1の接合材と、
前記メインパッケージ本体内に設けられており、前記第1の接合材に電気的に接続されている内部回路とを有するメインパッケージと、
前記メインパッケージの前記第2の主面上に配置されており、複数の電子部品を内蔵しているサブパッケージとを備え、
前記メインパッケージの第2の主面からサブパッケージの最も離れた部分までの寸法である厚み方向寸法が、前記第1の接合材の厚み方向寸法以下とされている、パッケージ基板。 - 前記メインパッケージ本体には、独立した電子部品が内蔵されていない、請求項1に記載のパッケージ基板。
- 前記サブパッケージが、対向し合う第1,第2の主面を有するサブパッケージ本体と、
前記サブパッケージ本体の前記第1の主面上に形成されており、前記メインパッケージの前記内部回路と、前記サブパッケージ本体内の前記電子部品とに電気的に接続されている第1のパッド導体と、
前記サブパッケージ本体の前記第2の主面上に形成されており、前記サブパッケージ内の前記電子部品に電気的に接続されている第2のパッド導体とを有し、
前記第2のパッド導体が、前記第1の接合材と共に、前記内部回路への入力経路部分または前記内部回路からの出力経路部分として機能する、請求項1または2に記載のパッケージ基板。 - 対向し合っている第1,第2の主面を有するメインパッケージ本体と、
前記メインパッケージ本体の前記第2の主面に設けられた第1の接合材と、
前記メインパッケージ本体内に設けられており、前記第1の接合材に電気的に接続されている内部回路とを有し、前記第2の主面において、下方に開いた凹部が形成されており、前記第1の接合剤が、該凹部の周囲の領域において第2の主面上に設けられているメインパッケージと、
前記メインパッケージの前記凹部内に配置されており、複数の電子部品を内蔵しているサブパッケージとを備え、
前記サブパッケージが、対向し合う第1,第2の主面を有するサブパッケージ本体と、前記サブパッケージ本体の前記第1の主面に形成されており、前記メインパッケージの前記内部回路と、前記サブパッケージ本体内の前記電子部品とに電気的に接続されている第1のパッド導体と、
前記サブパッケージ本体の前記第2の主面上に形成されており、前記サブパッケージ内の前記電子部品に電気的に接続されている第2のパッド導体とを有し、
前記メインパッケージの凹部の底面から前記サブパッケージの前記凹部から最も離れた部分までの寸法である厚み方向寸法が、前記凹部の底面から前記第1の接合材の前記メインパッケージの底面から最も離れた部分までの寸法以下とされている、パッケージ基板。 - 前記メインパッケージ本体の前記第2の主面上に複数の前記第1の接合材が配置されており、前記サブパッケージが、複数の前記第1の接合材に囲まれるように配置されている、請求項1〜4のいずれか1項に記載のパッケージ基板。
- 前記複数の前記第1の接合材が、前記メインパッケージ本体の前記第2の主面上においての外周に沿う位置に配置されている、請求項5に記載のパッケージ基板。
- 前記サブパッケージ本体が合成樹脂からなる、請求項3に記載のパッケージ基板。
- 前記第1の接合材がバンプからなる、請求項1〜7のいずれか1項に記載のパッケージ基板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009059522A JP2010212595A (ja) | 2009-03-12 | 2009-03-12 | パッケージ基板 |
US12/722,607 US8339797B2 (en) | 2009-03-12 | 2010-03-12 | Package substrate |
US13/689,794 US9313911B2 (en) | 2009-03-12 | 2012-11-30 | Package substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009059522A JP2010212595A (ja) | 2009-03-12 | 2009-03-12 | パッケージ基板 |
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JP2010212595A true JP2010212595A (ja) | 2010-09-24 |
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JP2009059522A Pending JP2010212595A (ja) | 2009-03-12 | 2009-03-12 | パッケージ基板 |
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US (2) | US8339797B2 (ja) |
JP (1) | JP2010212595A (ja) |
Cited By (3)
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JP2012109387A (ja) * | 2010-11-17 | 2012-06-07 | Ngk Spark Plug Co Ltd | 配線基板 |
US8964403B2 (en) | 2010-11-17 | 2015-02-24 | Ngk Spark Plug Co., Ltd. | Wiring board having a reinforcing member with capacitors incorporated therein |
CN105244348A (zh) * | 2015-09-30 | 2016-01-13 | 日月光半导体(上海)有限公司 | 封装基板及其制造方法 |
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US9035194B2 (en) * | 2012-10-30 | 2015-05-19 | Intel Corporation | Circuit board with integrated passive devices |
US20140167900A1 (en) | 2012-12-14 | 2014-06-19 | Gregorio R. Murtagian | Surface-mount inductor structures for forming one or more inductors with substrate traces |
US20160055976A1 (en) * | 2014-08-25 | 2016-02-25 | Qualcomm Incorporated | Package substrates including embedded capacitors |
KR102287396B1 (ko) * | 2014-10-21 | 2021-08-06 | 삼성전자주식회사 | 시스템 온 패키지 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
US20190198460A1 (en) * | 2017-12-21 | 2019-06-27 | AP Memory Technology Corp. | Circuit system having compact decoupling structure |
US11744018B2 (en) * | 2020-01-17 | 2023-08-29 | Kemet Electronics Corporation | Component assemblies and embedding for high density electronics |
JP2022142214A (ja) * | 2021-03-16 | 2022-09-30 | 太陽誘電株式会社 | セラミック電子部品、実装基板およびセラミック電子部品の製造方法 |
JP2022142213A (ja) | 2021-03-16 | 2022-09-30 | 太陽誘電株式会社 | セラミック電子部品、実装基板およびセラミック電子部品の製造方法 |
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Also Published As
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US8339797B2 (en) | 2012-12-25 |
US20130083502A1 (en) | 2013-04-04 |
US20100232126A1 (en) | 2010-09-16 |
US9313911B2 (en) | 2016-04-12 |
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