CN1812082A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN1812082A
CN1812082A CNA2005100228837A CN200510022883A CN1812082A CN 1812082 A CN1812082 A CN 1812082A CN A2005100228837 A CNA2005100228837 A CN A2005100228837A CN 200510022883 A CN200510022883 A CN 200510022883A CN 1812082 A CN1812082 A CN 1812082A
Authority
CN
China
Prior art keywords
semiconductor device
substrate
terminal
mounting terminal
resin bed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2005100228837A
Other languages
English (en)
Inventor
赤池贞和
井上明宣
加治木笃典
高津浩幸
坪田崇
山西学雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN1812082A publication Critical patent/CN1812082A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01067Holmium [Ho]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

提供一种半导体器件,包含半导体芯片、安装半导体芯片的基板、配置在基板的第一侧面上的安装端子和配置在基板的第二侧面上的测试端子,第二侧面是在基板的第一侧面反对面。

Description

半导体器件
技术领域
本发明涉及包含有配置在安装半导体芯片的基板上的测试端子的半导体器件。
背景技术
称之为单片组件的半导体器件除用于半导体器件与另一像母板之类基板连接的一些安装端子以外可以包含一些用于测试半导体器件电信号的测试端子。图1是包含象这样一些测试端子的半导体器件的剖面图。
图1所示的半导体器件10包含基板11、半导体芯片25,安装端子41和测试端子42。半导体芯片25和导线28是用模制树脂29密封的。
基板11包含基底衬板12、穿过基底衬板12的通路12,上层布线14、上树脂层15、通路16和33、布线17、阻焊层12和38,下层布线31、下树脂层32以及连接焊接区35和37。在图1中注意到,在上树脂层15上面装配半导体芯片的区域称之为芯片安装区域A。
在基底衬板12的上表面12A上配置上层布线14并且与通路14电连接。使上树脂层15配置成覆盖上层布线14和基底衬板12的上表面12A。使通路16配置成穿过上树脂层15、通路16在一侧面上的末端部分与上层布线14连接和通路16在另一侧面上的末端部分与布线17连接。布线17配置在上树脂层15上面并且包含连接导线28的连接部分19。阻焊层21配置在上树脂层15上面,并且在覆盖除了连接部分19外的布线部分17时露出芯片安装区域A和连接部分19。
在基底衬板12的下表面12B上配置下层布线31并且与通路13电连接。使下树脂层32配置成覆盖下层布线31和基底衬板12的下表面12B。使通路33装配成穿过下树脂层32、通路33在一侧面上的末端部分与连接焊接区35或者连接焊接区37连接和通路33在另一侧面上的末端部分与下层布线31连接。连接焊接区35和37安装在下树脂层32的表面32A上并且与通路33连接。连接焊接区37用于固定安装端子41,而连接焊接区35用于安装测试端子42。
半导体芯片25包含经由导线28与连接部分19连接的电极焊接区26。把半导体芯片25安装在上树脂层15上面的芯片安装区域A上。
测试端子42与用于测试半导体器件10电信号的外部端子相对应。把测试端子42安装在基底衬板12的下表面12B侧(即下树脂层32的下表面32A)配置的连接焊接区35上。
近几年来连续不断地有例如提高半导体器件小型化和致密化的需求,而随后为重叠一个以上半导体器件并且把所重叠的半导体器件安装在另一像母板之类的基板上而研制了一种技术方法。注意到在Japanese Laid-open Patent No.2001-339011中公开了像这样的技术方法。图2是两个半导体器件的剖面图,两个半导体器件是一个半导体器件重叠在另一个半导体器件的顶部。应该指出,规定与图1所示的半导体器件10中部分相同的图2所示的重叠半导体器件50和70中部分具有同样的数字标记。
在图2中,半导体器件50装有重叠在其上的半导体器件70并且配置成与另一像母板之类的基板(未表示出)连接。半导体器件50包含基板51、半导体芯片55和安装端子62。
基板51包含基底衬板12、通路13、上层布线14、上树脂层15、通路16和33、阻焊层21和38、下层布线31、下树脂层32、连接部分53以及连接焊接区54和61。把连接部分53和连接焊接区54配置在上树脂层15上面并且与通路16电连接。使连接部分53与半导体芯片55中的电极焊接区56电连接。使连接焊接区54与配置在半导体器件70上的安装端子72连接。把连接焊接区61配置在下树脂层32的下表面32A上,并且与通路33电连接。
半导体芯片55包含与螺栓凸缘57电连接的电极焊接区56。螺栓凸缘57通过低温焊料58与连接部分53电连接。并且在半导体芯片55和基板51之间配置未填满树脂59。把安装端子62装配在连接焊接区61上并且配置成与另一像母板之类的基板(未表示出)连接。
半导体器件70安装在半导体器件50中的连接焊接区54上面,并且包含基板71、半导体芯片25和安装端子72。用模制树脂29密封半导体芯片25和导线28。
基板71包含基底衬板12、通路13、上层布线14、上树脂层15、通路16和33、布线17、阻焊层21和38、下层布线31、下树脂层32以及连接焊接区37。安装端子72与半导体器件50中的连接焊接区54电连接。通过使安装端子72与连接焊接区54连接,可以获得半导体器件50和半导体器件70之间的电连接。
通过如上所述的重叠两个半导体器件50和70并且把所重叠的半导体器件结构安装在另一像母板之类的基板上面,可以减小为安装半导体50和70而要求的在另一基板上区域的外部尺寸,并且可以以更高密度安装半导体50和70。
在图1所举例说明的实施例中,由于半导体器件10装有配置在基板11的一侧(即下树脂层32的下表面32A侧)上的两种类型端子(即安装端子41和测试端子42),因此基板11的外部尺寸可能是比较大的,这时不会使半导体器件10充分满足小型化。
在图2所举例说明两个半导体50和70实现重叠半导体器件结构的实施例中,可以实现半导体器件50和70的致密化。然而,在这样的实施例中,即使设置与半导体器件10中的测试端子类似的测试端子,那末测试端子竖着朝向半导体器件50以致不可能进行半导体器件50和半导体器件70之间电信号的测试。
发明内容
本发明应以上所述的一个或更多个问题而生,而且本发明提供可以小型化的半导体器件并且适用于能够测试配置成重叠半导体器结构的该半导体器件和另一半导体器件的电信号。
根据本发明的一种实施方式,提供一种半导体器件,包含:
半导体芯片;
安装半导体芯片的基板;
在该基板的第一侧面上配置的安装端子;和
在基板的第二侧面上配置的测试端子,第二侧面是在第一侧面对面。
在本实施方式的一个方面中,通过在对着配置安装端子的基板第一侧面的基板第二侧面上配置测试端子,例如可以减小基板的外部尺寸而且可以实现半导体器件的小型化。在本实施方式的另一种状况中,甚至例如在本实施方式的半导体器件上面安装另一半导体器件时,也可以进行半导体器件中的电信号的测试。
根据本发明具体实施方式,在基板第二侧面上安装半导体芯片,并且使测试端子从基板第二侧面比半导体芯片更进一步凸出。
在本实施方式的一个方面中,通过把测试端子配置成比半导体芯片更进一步凸出,例如可以防止半导体芯片妨碍测试装置中的探针与测试端子的连接过程因此可以容易地使探针和测试端子连接。
根据本发明另一种具体实施方式,半导体芯片通过导线与基板连接,并且测试端子从基板第二侧面比导线更进一步凸出。
在本实施方式的一个方面中,通过把测试端子装配成比导线更进一步凸出,例如可以防止导线妨碍测试装置中的探针与测试端子的连接过程因此可以容易地使探针和测试端子连接。
根据本发明另一种具体实施方式,用树脂覆盖半导体芯片,并且穿通树脂露出测试端子中的一部分。
在本实施方式的一个方面中,例如树脂可以控制测试端子相对于基板的定位。
附图说明
图1是包含测试端子的半导体器件的剖面图;
图2是一个重叠在另一个顶部上的两个半导体器件的剖面图;
图3是根据本发明实施方式的半导体器件的平面图;
图4是横切图3所示线B-B的半导体器件的剖面图;
图5是通过把根据本实施方式的半导体器件安装在另一半导体器件上所获得的一种结构的剖面图;
图6是举例说明用于制造根据本实施方式的半导体器件的第一工艺步骤的例图;
图7是举例说明用于制造根据本实施方式的半导体器件的第二工艺步骤的例图;
图8是举例说明用于制造根据本实施方式的半导体器件的第三工艺步骤的例图;
图9是举例说明用于制造根据本实施方式的半导体器件的第四工艺步骤的例图;
图10是举例说明用于制造根据本实施方式的半导体器件的第五工艺步骤的例图;
图11是根据本发明另一种实施方式,包含有在基板两侧上的测试端子的半导体器件的剖面图;
图12是通过把另一半导体器件安装在图11所示的半导体器件上面所获得的一种结构的剖面图;
图13是通过把图4所示的半导体器件安装在图11所示的半导体器件上面所获得的一种结构的剖面图;
图14是根据本发明另一种实施方式包含电子元件和测试端子的半导体器件的剖面图;和
图15是通过使图14所示的半导体器件与母板连接所获得的一种结构的剖面图。
具体实施方式
在下文中,参阅附图描述本发明具体实施例。
首先,参阅图3和4描述根据本发明一种实施方式的半导体器件80。图3是根据本实施方式的半导体器件80的平面图,而图4是横切图3所示B-B线的半导体器件80的剖面图。注意在图3中,R1表示穿通模制树脂109露出的测试端子103平坦表面103A的直径(在下文中称之为‘直径R1’)。在图4中也注意到,C表示在上树脂层96上面安装半导体芯片105的区域(在下文中称之为‘芯片安装区域C’),H1表示导线107相对于电极焊接区106的高度(在下文中称之为‘高度H1’),T1表示包含电极焊接区106的半导体芯片105的厚度(在下文中称之为‘厚度T1’),T2表示模制树脂109相对于上树脂层109上表面的厚度(在下文中称之为‘厚度T2’),R2表示基本上成球面构形的测试端子103的直径(称之为‘直径R2’)以及R3表示基本上成球面构形的安装端子92的直径(在下文中称之为‘直径R3’)。
根据本实施方式,半导体器件80包含基板81、半导体芯片105、安装端子92和测试端子103。基板81包含基底衬板82、通路83、下层布线85、下树脂层87、通路88和97、连接焊接区89和101、阻焊层91和102、上层布线95、上树脂层96以及导线连接部分99。
基底衬板82例如可以是用树脂原材料或陶瓷原材料制成的一种平板构件。把通路83配置成穿通基底衬板82。为实现上层布线95和下层布线85之间的电连接而设置通路83。下层布线85配置在基底衬板82的下表面82B上并且与通路83电连接。把下树脂层87配置成覆盖下层布线85和基底衬板82的下表面82B。把通路88配置成穿通下树脂层87、在一侧面上的通路88末端部分与下层布线85连接,和在另一侧面上的通路88末端部分与连接焊接区89连接。
连接焊接区89配置在下树脂层87的表面87A上,并且与通路88电连接。连接焊接区89用于装配安装端子92。把阻焊层91配置成覆盖下树脂层87的表面87A而露出连接焊接区89。
上层布线95配置在基底衬板82的上表面82A上,并且与通路83电连接。把上树脂层96配置成覆盖上层布线95和基底衬板82的上表面82A。注意,安装半导体芯片105的芯片安装区域C是在上树脂层96上面形成的。把通路97配置成穿通上树脂层96、在一侧面上的通路97末端部分与上层布线95连接,和在另一侧面上的通路97末端部分与导线连接部分99或者连接焊接区101连接。
导线连接部分99配置在上树脂层96上,并且与通路97电连接。导线连接部分99用于安装与半导体芯片105连接的导线107。连接焊接区101配置在上树脂层96上,并且与通路97电连接。测试端子103配置在连接焊接区101上。把阻焊层102配置成覆盖上树脂层96的上表面而露出连接焊接区101和芯片安装区域C。
用粘合剂把半导体芯片105安装在上树脂层96上面的芯片安装区域C上。半导体芯片105包含经由导线107与导线连接部分99电连接的电极焊接区106。半导体芯片105的厚度T1例如可以为0.15mm。而且,导线107的高度H1例如可以为0.1mm。
根据一种实施方式,一些安装端子92可以与像半导体器件50(见图5)之类的另一半导体器件电连接的一些外部端子相对应。安装端子92配置在下树脂层87的下表面87A上,并且与连接焊接区89电连接。注意到,例如焊料珠或者金属柱可以用作安装端子92。在焊料珠用作安装端子92的情况中,安装端子92的直径R3例如可以为0.4mm。
测试端子103可以用于测试电信号。在一种实施方式中,通过使测试装置中的一些探针(未表示出)连接到测试端子103可以实施电信号测试。测试端子103配置在上树脂层96的上表面上,也就是在相对于配置安装端子92的侧面(即下树脂层87的表面87A)对置的基板81侧面上,并且测试端子103与连接焊接区101电连接。
通过把测试端子103装配在相对于配置安装端子92的基板81侧面(例如下树脂层87的下表面87A)对置的基板81侧面(例如上树脂层96的上表面)上,用于安装测试端子103的连接焊接区不一定要装配在配置安装端子92的同一个基板81侧面上,因此可以减小基板81的外部尺寸同时可以使半导体器件80小型化。
图5是通过把本实施方式的半导体器件80安装在图2所示的半导体器件50上面所获得的结构的剖面图。当例如把本实施方式的半导体器件80安装在如图5所示的半导体器件50上时,可以使测试装置中的一些探针(未表示出)连接到配置在上树脂层96的上表面侧,也就是不是面向半导体器件50侧的一些测试端子103,因此可以实施半导体器件50和半导体器件80中的电信号测试。
在所举例说明的实施方式中,测试端子103含有基本上是球面的构形而在球面构形的上面部分上配置成平坦表面103A。应当指出,测试端子103优选配置成比导线107更进一步凸出。
通过把测试端子103配置成比导线更进一步凸出,可以防止导线107妨碍测试装置的一些探针与测试端子103的平坦表面103A连接的过程。本身也可以便于测试装置一些探针与一些测试端子103连接。此外,在半导体芯片105倒装式地与基板81连接的情况中,使测试端子103优选配置成比半导体芯片105更进一步凸出。
在所举例说明的实施方式中,把用于保护导线107的模制树脂109配置成露出测试端子103的平坦表面103A而覆盖测试端子103的其他部分。使测试端子103的平坦表面103A和模制树脂109的表面109A配置成基本上是同一平面的。通过把模制树脂109配置成露出测试端子的平坦表面103A而覆盖测试端子103的其他部分,模制村脂109可以支承测试端子130的周边,并且可以控制测试端子103相对于基板81的定位。
注意到例如焊料珠或者圆柱形/棱柱形金属柱可以用作测试端子103。在金属柱用作测试端子103的情况中,例如可以用低温焊料把用铜制造的金属柱和连接焊接区101连接在一起,或者通过在连接焊接区101上诱发镀层沉积生长可以形成金属柱。在焊料珠用作测试端子103的情况中,例如测试端子103的直径R2可以为0.4mm,并且在象这样的情况中,通过模制树脂109露出的平坦表面103A的直径R1例如可以为0.25mm。此外,模制树脂109的厚度T2例如可以为0.3mm。
在下文中,参阅图6一直到10,描述制造本实施方式的半导体器件80的方法。图6一直到10是举例说明用于制造半导体器件80的工艺步骤的例图。注意到在图6一直到10中,与图4所示部分相同的部分具有相同的数字标记。此外,注意到在图8中,T3表示在抛光模制树脂109以前模制树脂109相对于上树脂层96上表面的厚度(在下文中称之为‘厚度T3’)。
根据所举例说明的实施方式,如图6所示,首先例如通过制造基板的常规方法制造如参照图4所描述那样的基板81。在这样的情况中,在上树脂层96的上表面(即相对于形成用于装配安装端子的连接焊接区的侧面的对置侧面)上形成连接焊接区101。
然后,如图7所示,借助于粘合剂把半导体芯片105安装在上树脂层96上面的芯片安装区域C上,而且借助于导线107使电极106和导线连接部分99连接。然后,使测试端子103与连接焊接区101连接。在一个实施例中,半导体芯片105的厚度T1可以为0.15mm,而导线107的高度H1可以为0.1mm。此外,在焊料珠用作测试端子103的情况中,测试端子103的直径R2例如可以为0.4mm。
然后,如图8所示,把模制树脂109配置成覆盖导线107、半导体芯片105和测试端子103。注意使模制树脂109的厚度T3优选配置成足以覆盖导线107的厚度。
然后,如图9所示,磨平模制树脂109的抛光表面因此可以使抛光表面配置成与基底衬板82的平面方向平行,结果使测试端子103穿通模制树脂109露出上面部分。在这样的情况中,测试端子103与模制树脂109一起磨光以使测试端子103的上面部分配置成穿通模制树脂109露出平坦表面103A。注意,磨光以后模制树脂109的厚度T2例如可以为0.3mm。测试端子103平坦表面103A的直径R1例如可以为0.25mm。
然后,如图10所示,使安装端子92与连接焊接区89连接,因而制成半导体器件80。注意在焊料珠用作安装端子92的情况中,安装端子92的直径R3例如可以为0.4mm。
在下文中,参阅图11和12描述半导体器件80的变换实施例。在根据这个变换实施例的半导体器件110中,在上树脂层96的上表面配置用于实现与另一半导体器件连接的安装端子而不是测试端子103。也就是说,半导体器件110具有配置在其基板两侧上的安装端子。
图11是半导体器件110的剖面图,而图12是通过把图2所示的半导体器件70安装在半导体器件110上面所获得的一种结构的剖面图。注意在图11中,T4表示包含电极焊接区106的半导体芯片123的厚度(在下文中称之为‘厚度T4’)。此外,注意在图11和12中,与图4所示的半导体器件80中的部分相同的部分具有相同的数字标记。
根据所举例说明的实施方式,半导体器件110包含基板115、半导体芯片123以及安装端子118和125。用粘合剂把半导体芯片123粘合到上树脂层96上面的芯片安装区域C上。
基板包含基底衬板82、通路83、下层布线85、下树脂层87、通路88和97、阻焊层91和102上层布线95、上树脂层96、导线连接部分99以及连接焊接区117和121。连接焊接区117是用于装配安装端子118,并且配置在下树脂层87的表面87A上。连接焊接区121是用于装配安装端子125,并且配置在上树脂层96的上表面上。
半导体芯片123包含经由导线107与导线连接部分99电连接的电极焊接区106。在一个实施例中,半导体器件123的厚度T4可以为0.15mm。此外,导线107的高度H1例如可以为0.1mm。
一些安装端子118与用于实现与另一例如母板之类的基板连接的一些外部连接端子相对应。安装端子118含基本上是球面的构形并且配置在连接焊接区117上面。注意到焊料珠或金属柱例如可以用作安装端子118。在焊料珠用作安装端子118的情况中,安装端子118的直径R4例如可以为0.4mm。
安装端子125含基本上是球面的构形而平坦表面125A配置在球面构形的上面部分上。注意使安装端子125优选配置成比导线107更进一步凸出。
如图12所示,通过使安装端子125在连接焊区121上配置成121比导线107更进一步凸出,在半导体器件110上面安装半导体器件70时可以在远离导线107位置的位置上连接安装端子125和安装端子41。在这样的方法中,不必考虑半导体芯片123和导线107之间的定位关系,因此能够便于把半导体器件70装配到半导体器件110上。注意到在半导体器件123倒装式地与基板115连接的情况中,使安装端子125优选配置成比半导体芯片123更进一步凸出。
在所举例说明的实施方式中,安装端子125配置在连接焊接区121上面,并且把模制树脂109配置成露出安装端子125的表面125A而覆盖安装端子125的其他部分。此外,使安装端子125的表面125A配置成基本上与模制树脂109的表面109A共面。
通过使模制树脂109配置成露出表面125A而覆盖安装端子125的其他部分,可以控制安装端子125相对于基板115的定位。注意到例如焊料珠或者圆柱形/棱柱形金属柱可以用作安装端子125。在金属柱用作安装端子125的情况中,例如可以用低温焊料把用铜制造的金属柱和连接焊接区121连接在一起,或者通过在连接焊接区121上诱发镀层沉积生长可以形成金属柱。在一个实施例中,安装端子125的直径R5例如可以为0.4mm,并且在这样的情况中,由模制树脂109露出的安装端子125表面125A的直径R6例如可以为0.25mm。
图13是通过在半导体器件110上装配如图4所示的半导体器件80所获得的结构的剖面图。如图13所示,可以在半导体器件110上安装含配置在基底衬板82的上表面82A侧上的测试端子103的半导体器件80,因此可以实施半导体器件80和半导体器件110之间电信号的测试。
在下文中,参阅图14和15描述半导体器件80的另一变换实施例。根据本变换实施例的半导体器件130包含用于实现与配置在基底基板82上表面82A侧上的像母板之类另一基板连接的安装端子134和配置在基底衬板82下表面侧上的电子元件。图14是半导体器件130的剖面图,而图15是通过半导体器件130与母板150连接所实现的结构的剖面图。注意在图14和15中,与图4所示的半导体器件80的部分相同的部具有相同的数字标号。
在所举例说明的实施方式中,半导体器件130包含基板131、半导体芯片105、安装端子134、独立元件141和容纳半导体芯片(未表示出)在其内的封装件145。
基板131包含基底衬板82、通路83、下层布线85、下树脂层87、通路88和97、上层布线95、上树脂层96、导线连接部分99、阻焊层102和138、连接焊接区132、第一连接部分136和第二连接部分137。连接焊接区132配置在上树脂层96上面并且与通路97电连接。连接焊接区用于装配安装端子134。
第一连接部分136配置在下树脂层87的表面87A上并且与通路88电连接。使第一连接部分136构形成实现与独立元件141电连接。第二连接部分137配置在下树脂层87的表面87A上,并且与通路88电连接。使第二连接部分137构形成实现与封装件145电连接。阻焊层138配置在下树脂层87表面87A上面第一连接部分136和第二连接部分137之间的区域上。
安装端子134含基本上是球面的构形而平坦表面134A配置在球面构形的上面部分上。安装端子134装配在连接焊接区132上面,并且配置成比导线107更进一步凸出。注意到,例如焊料珠或者金属柱可以用作安装端子134。
如图15所示,通过使安装端子134在连接焊接区132上配置成比导线107更进一步凸出,在母板150上面安装半导体器件130时可以在远离导线107的位置上电连接母板150的连接焊接区151和安装端子134。在这样的方法中,半导体器件130可以很容易安装在母板150上而不必考虑半导体芯片105和导线107的位置。在半导体芯片105倒装式地与基板131连接的情况中,使安装端子优选配置成比半导体芯片105更进一步凸出。
在所举例说明的实施方式中,把模制树脂109配置成露出安装端子134的表面134A而覆盖安装端子134的其他部分。使安装端子134的表面134A配置成基本上与模制树脂109的表面109A共面。
通过使模制树脂109配置成露出表面134A而覆盖安装端子134的其他部分,模制树脂109可以支承安装端子134的周边因此可以控制安装端子134相对于基板131的定位。注意到焊料珠或者圆柱形/棱柱形金属柱可以用作安装端子134。在金属柱用作安装端子134的情况中,例如可以用低温焊料把用铜制造的金属柱和连接焊接区132连接在一起,或者例如通过在连接焊接区132上诱发镀层沉积生长可以形成金属柱。在焊料珠用作测试端子134的情况中,测试端子134的直径R7例如可以为0.4mm,而在像这样的情况中,安装端子134中的平坦表面134A的直径R8例如可以为0.25mm。
独立元件141是包含电极142的电子元件。用低温焊料柱143使电极142与第一连接部分136电连接。在一种实施方式中,例如一些独立元件141中的每个独立元件141可以相当于像晶体管、二极管、电阻器或电容器之类基本的电器件;也就是说,一些元件141中的每个元件141可以实现像这些功能中的一个功能(元件141也称之为‘分立元件’)。
相当于另一种电子元件的封装件145包含组件本体146、引线架147和容纳在组件本体146内的半导体芯片(未表示出)。引线架147与容纳在组件本体146内的半导体芯电连接。用低温焊料使引线架147与第二连接部分137电连接。
通过把安装端子134配置在安装半导体芯片105的基板131侧面上,可以在基板131另一侧面上,也就是相对于安装半导体芯片105侧面对置的侧面上配置一个以上的电子元件(例如独立元件141和封装件145)。在这样的方法中,可以高密度地安装半导体器件130。应该指出配置在基板131上的电子元件类型不局限于所举例说明的实施例中的电子元件类型。
虽然根据一些具体实施方式说明和描述本发明,但是对熟练的技术人员来说在阅读和理解本说明书时会想到一些同等物和变换物是显而易见的。本发明包含所有像这样的同等物和变换物,而只受权利要求书中的范围限制。
本申请书是基于并主张日本专利申请No.2004-358543(2004年12月10日已申请)的利益,在此引入完整内容作参考。

Claims (4)

1.一种半导体器件,包括:
半导体芯片;
安装半导体芯片的基板;
在基板的第一侧面上配置的安装端子;和
配置在基板的第二侧面上的测试端子,第二侧面是在基板的第一侧面对面。
2.如权利要求1所述的半导体器件,其中:
在基板的第二侧面上安装半导体芯片;和
测试端子从基板的第二侧面比半导体芯片更进一步凸出。
3.如权利要求2所述的半导体器件,其中:
半导体芯片通过导线与基板连接;和
测试端子从基板的第二侧面比导线更进一步凸出。
4.如权利要求1所述的半导体器件,其中,
半导体芯片由树脂覆盖,并且测试端子的一部分穿过树脂露出。
CNA2005100228837A 2004-12-10 2005-12-09 半导体器件 Pending CN1812082A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004358543 2004-12-10
JP2004358543A JP4444088B2 (ja) 2004-12-10 2004-12-10 半導体装置

Publications (1)

Publication Number Publication Date
CN1812082A true CN1812082A (zh) 2006-08-02

Family

ID=36582851

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2005100228837A Pending CN1812082A (zh) 2004-12-10 2005-12-09 半导体器件

Country Status (5)

Country Link
US (1) US20060125077A1 (zh)
JP (1) JP4444088B2 (zh)
KR (1) KR20060065561A (zh)
CN (1) CN1812082A (zh)
TW (1) TWI395302B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892935B1 (ko) 2005-12-14 2009-04-09 신꼬오덴기 고교 가부시키가이샤 칩 내장 기판 및 칩 내장 기판의 제조방법
JP2008016630A (ja) * 2006-07-06 2008-01-24 Matsushita Electric Ind Co Ltd プリント配線板およびその製造方法
JP5135828B2 (ja) * 2007-02-28 2013-02-06 ソニー株式会社 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法
JP4802155B2 (ja) * 2007-08-07 2011-10-26 京セラSlcテクノロジー株式会社 配線基板
JP5557439B2 (ja) 2008-10-24 2014-07-23 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
CN103681359A (zh) * 2012-09-19 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
JP6320681B2 (ja) * 2013-03-29 2018-05-09 ローム株式会社 半導体装置
CN103346137A (zh) * 2013-06-24 2013-10-09 曙光信息产业(北京)有限公司 集成电路封装件及其工艺方法
KR102237870B1 (ko) * 2013-10-25 2021-04-09 엘지이노텍 주식회사 인쇄회로기판 및 그 제조방법과 이를 이용하는 반도체 패키지
KR102192569B1 (ko) * 2015-11-06 2020-12-17 삼성전자주식회사 전자 부품 패키지 및 그 제조방법
US10204889B2 (en) * 2016-11-28 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100266693B1 (ko) * 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
JP2001339011A (ja) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US6326700B1 (en) * 2000-08-15 2001-12-04 United Test Center, Inc. Low profile semiconductor package and process for making the same
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package

Also Published As

Publication number Publication date
JP4444088B2 (ja) 2010-03-31
US20060125077A1 (en) 2006-06-15
TW200625561A (en) 2006-07-16
JP2006165466A (ja) 2006-06-22
KR20060065561A (ko) 2006-06-14
TWI395302B (zh) 2013-05-01

Similar Documents

Publication Publication Date Title
CN1812082A (zh) 半导体器件
CN1183593C (zh) 半导体装置
CN101080958A (zh) 部件内置模块及其制造方法
CN1208820C (zh) 半导体晶片、半导体装置及其制造方法
CN1107349C (zh) 一种半导体器件引线框架及引线接合法
CN1848427A (zh) 电子装置及其制造方法
CN1292475C (zh) 半导体封装及其制造方法
CN1945817A (zh) 半导体器件及其制造方法
CN1512445A (zh) Ic卡及其制造方法
CN1319885A (zh) 固定夹具、配线基板和电子零部件组装体及其制造方法
CN1516898A (zh) 半导体装置及其制造方法
CN1277737A (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1459855A (zh) 半导体器件及其制造方法
CN1641873A (zh) 多芯片封装、其中使用的半导体器件及其制造方法
CN1591861A (zh) 电路元件内置模块及其制造方法
CN1441489A (zh) 半导体装置及其制造方法、电路板和电子仪器
CN1815733A (zh) 半导体装置及其制造方法
CN1835229A (zh) 半导体器件和制造半导体器件的方法
CN1779951A (zh) 半导体器件及其制造方法
CN1293375A (zh) 光学模块及其制造方法、半导体装置以及光传递装置
CN1551343A (zh) 电子元件封装结构及其制造方法
CN1622328A (zh) 半导体器件及其制造方法
CN1532932A (zh) 半导体装置及其制造方法、电子设备、电子仪器
CN1901178A (zh) 继电板及具有继电板的半导体器件
CN1476100A (zh) 摄像机模块及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Open date: 20060802