CN1901178A - 继电板及具有继电板的半导体器件 - Google Patents

继电板及具有继电板的半导体器件 Download PDF

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CN1901178A
CN1901178A CNA2005101136368A CN200510113636A CN1901178A CN 1901178 A CN1901178 A CN 1901178A CN A2005101136368 A CNA2005101136368 A CN A2005101136368A CN 200510113636 A CN200510113636 A CN 200510113636A CN 1901178 A CN1901178 A CN 1901178A
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chip
relay plate
semiconductor
semiconductor chip
wiring
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CN1901178B (zh
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泷吞丰
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Socionext Inc
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Fujitsu Ltd
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Abstract

本发明涉及一种继电板，其设置于设有多个半导体芯片的半导体封装中，该继电板转接用于对多个半导体芯片进行布线的线或用于对该半导体封装的引线框架和该半导体芯片进行布线的线，该继电板包括多条布线，每条布线连接至少三个焊盘。

Description

继电板及具有继电板的半导体器件
技术领域
本发明通常涉及继电板(relay board)以及具有继电板的半导体器件，更具体地涉及一种设置于半导体器件中的继电板，例如用于对多个半导体芯片进行布线或对半导体芯片和半导体封装的引线框架进行布线的继电板，并涉及具有该继电板的半导体器件，其中该半导体器件具有多个半导体芯片容置在单个半导体封装中的结构。
背景技术
已知可通过使用SiP(系统级封装)技术可以制作在一个半导体封装中设置有多个具有不同功能的芯片的单个封装。在通过使用这种技术在单个半导体封装中设置多个半导体芯片的情况下，必须直接丝焊多个半导体芯片本身，或者丝焊各个半导体芯片与半导体封装的引线框架。
图1为示出使用SiP技术的现有技术半导体器件的俯视图。参照图1，在现有技术半导体器件10中，在具有焊盘19的引线框架上设置第一半导体芯片11。第二半导体芯片18粘合并固定至第一半导体芯片11上。第二半导体芯片18的四个焊盘12-1至12-4分别连接至设置在第一半导体芯片11的四边的焊盘9中的焊盘9-1至9-4。第一半导体芯片11的焊盘9通过用于引线框架的焊线17连接至引线框架的焊盘19。
但是，在多个半导体芯片11和18粘合在一起的情况下，例如第一半导体芯片11的焊线13和14等焊线交叉，并且例如第一半导体芯片11的焊线15和16等焊线的线长太长。
为解决上述问题，如图2和图3所示，提出在半导体封装中设有用于通过焊线转接布线的引线芯片(terminal chip)的实例。
图2为设有引线芯片的现有技术半导体器件的第一实例的平面图。参照图2，在半导体器件20中，在第一半导体芯片11与第二半导体芯片18之间放置引线芯片25。在引线芯片25中形成8个焊盘26。此外，在引线芯片25中设置4条金属布线(metal wiring)27，其中每条金属布线27均连接两个焊盘26。例如，一对相连接的焊盘26通过第一焊线24连接至第二半导体芯片18的焊盘12，通过第二焊线28连接至第一半导体芯片11的焊盘9，以及通过第三焊线29连接至引线框架的焊盘19。在这种结构下，引线芯片25通过焊线24、28以及29转接(relay)，从而线长可以比图1所示的结构缩短很多。
图3为设有引线芯片的现有技术半导体器件的第二实例的平面图。参照图3，在半导体器件30中，在第一半导体芯片11上并排设置第二半导体芯片18与引线芯片35。在引线芯片35中形成6个焊盘36。并且，在引线芯片35中设置3条连接两个焊盘36的金属布线37。图3中，在引线芯片35的左侧和中间的金属布线37所连接的焊盘36中，焊盘36-1通过第一焊线38连接至第二半导体芯片18的焊盘12；焊盘36-2通过第二焊线39连接至第一半导体芯片11的焊盘9，并进一步通过引线框架的焊线17连接至引线框架的焊盘19。在这种结构下，引线芯片35通过焊线38和39转接，从而避免图1所示结构中的焊线交叉。参见日本特许公开No.61-112346、No.8-78467、No.2001-7278、以及No.2004-56023。
但是，引线芯片所转接的半导体芯片的尺寸以及半导体芯片中形成的焊盘的数目或排列是变化的。因此，即使引线芯片适合于某半导体封装的设计，该引线芯片也不可能总是适合其它半导体封装的设计。也就是说，图2和图3所示的引线芯片25和35并不能总是适合不同于图2和图3所示的半导体芯片的半导体芯片组合。
因此，在现有技术中，有必要制造及制备用于与安装至另一半导体芯片上的一个半导体芯片组合或其每一个设计的引线芯片。
仅可用于该安装芯片的特定组合的引线芯片需要较长的开发周期，并且制造成本高。
发明内容
因此，本发明的总体目的是提供一种新颖且实用的继电板以及具有该继电板的半导体器件。
本发明另一更具体的目的是提供一种继电板以及具有该继电板的半导体器件，该继电板不仅可广泛和普遍应用于该继电板所转接的半导体芯片的特定组合，而且可广泛和普遍应用于该半导体芯片与其它半导体芯片的多种组合。
通过在设有多个半导体芯片的半导体封装中设置继电板可实现本发明的上述目的，其中该继电板转接用于对多个半导体芯片进行布线的线(wire)或用于对该半导体封装的引线框架和该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
通过一种半导体器件也可实现本发明的上述目的，其中该半导体器件具有如下结构：在第一半导体芯片上设有继电板，该继电板上设有第二半导体芯片，并且该第一半导体芯片、该第二半导体芯片、以及该继电板被封装；
该继电板转接用于对多个半导体芯片进行布线的线或用于对该半导体器件的引线框架以及该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
通过一种半导体器件也可实现本发明的上述目的，其中该半导体器件具有如下结构：在继电板上设有第一半导体芯片，在该第一半导体芯片上设有第二半导体芯片，并且该第一半导体芯片、该第二半导体芯片、以及该继电板被封装；
该继电板转接用于对多个半导体芯片进行布线的线或用于对该半导体器件的引线框架以及该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
通过一种半导体器件也可实现本发明的上述目的，其中该半导体器件具有如下结构：第一半导体芯片和第二半导体芯片并排设置于继电板上，并且该第一半导体芯片、该第二半导体芯片、以及该继电板被封装；
该继电板转接用于对该多个半导体芯片进行布线的线或用于对该半导体器件的引线框架以及该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
通过一种半导体器件也可实现本发明的上述目的，其中该半导体器件具有如下结构：第二半导体芯片和继电板并排设置于第一半导体芯片上，并且该第一半导体芯片、该第二半导体芯片、以及该继电板被封装；
该继电板转接用于对该半导体芯片进行布线的线或用于对该半导体器件的引线框架以及该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
附图说明
图1为示出使用SiP技术的现有技术半导体器件的平面图；
图2为设有引线芯片的现有技术半导体器件的第一实例的平面图；
图3为设有引线芯片的现有技术半导体器件的第二实例的平面图；
图4为本发明第一实施例的引线芯片的平面图；
图5(A)为图4中虚线所环绕的部分的放大图，以及图5(B)为与使金属布线的焊盘的位置与另一金属布线的焊盘的位置在垂直于设置金属布线的方向的方向上均匀的情况进行比较的视图；
图6为图4所示的引线芯片的修改实施例的平面图；
图7为本发明的第二实施例的引线芯片的平面图；
图8为图7所示的本发明的第二实施例的引线芯片的第一修改实施例的引线芯片的平面图；
图9为图7所示的本发明的第二实施例的引线芯片的第二修改实施例的引线芯片的平面图；
图10为图7所示的本发明的第二实施例的引线芯片的第三修改实施例的引线芯片的平面图；
图11为本发明的第三实施例的引线芯片的平面图；
图12为本发明的第四实施例的引线芯片的平面图；
图13为本发明的第五实施例的引线芯片的平面图；
图14为本发明的第六实施例的引线芯片的平面图；
图15为本发明的第七实施例的引线芯片的平面图。
具体实施方式
以下参照图4至图15说明本发明的实施例。为方便说明，参照图4至图10说明本发明的实施例的引线芯片，然后参照图11至图15说明本发明的实施例的半导体器件。
【引线芯片】
本发明的引线芯片设置在半导体器件中，并且该引线芯片起到设置于该半导体器件中的半导体芯片的继电板的作用。
参照图4至图6说明本发明的第一实施例的引线芯片。
图4为本发明第一实施例的引线芯片的平面图。参照图4，本发明的第一实施例的引线芯片40具有基本呈矩形的结构。沿引线芯片40的四边以同心状态设有由金属制成的四条布线41-1至41-4。通过金属布线41连接焊盘45。更具体地说，在金属布线41-1至41-4中的每一条金属布线中，以指定间隙形成三个或更多焊盘45。
如以下参照图11所述，本实施例的引线芯片40例如放置在面积大于引线芯片40的某半导体芯片与面积小于引线芯片40且设置在未设有金属布线41-1至41-4的部分的另一半导体芯片之间。引线芯片40的焊盘45经由指定焊线连接至形成于各自半导体芯片中的焊盘。
如参照图2和图3所述，在现有技术的引线芯片中，为单条金属布线设置一对焊盘，即仅两个焊盘。但是，在图4所示的本实施例的引线芯片40中，在单条金属布线41中设置三个或更多焊盘45。因此，能够使用并适当选择位置适合于半导体芯片的组合的焊盘45。
此外，如上所述，在本实施例的引线芯片40中设有多条金属布线41。因此，能够适当选择适合于半导体芯片的组合的金属布线41，以及使用并适当选择设置于金属布线41中的焊盘45。
引线芯片40的衬底由用于半导体芯片的材料硅制成。因此，可以避免由于半导体芯片材料的热膨胀率的差别而产生应变。但是，本实施例的引线芯片的材料并不限于硅。例如，陶瓷、酚醛树脂(Bakelite)、玻璃环氧树脂等的薄型衬底，或者树脂膜、聚酰亚胺膜、聚乙烯对苯二甲酸酯膜等可以用作引线芯片的材料。
图5(A)为图4中虚线所环绕的部分的放大图。图5(B)为与使金属布线的焊盘的位置与另一金属布线的焊盘的位置在垂直于设置金属布线的方向的方向上均匀的情况进行比较的视图。
参照图5(A)，在图4所示的引线芯片40中，在设置金属布线41-1和41-2的方向上，金属布线41-1的焊盘45-1的位置偏离与金属布线41-1相邻的另一金属布线41-2的焊盘45-2的位置。因此，可以使得在金属布线41-1的焊盘45-1与另一金属布线41-2的焊盘45-2之间形成的间隙“a”小于在垂直于设置金属布线的方向的方向上均匀的金属布线的焊盘与相邻金属布线的焊盘之间形成的间隙“b”，即a＜b。因此，通过制造图5(A)所示的结构，能够使得引线芯片的尺寸变小。
在图5(A)和图5(B)中，通过虚线示出连接至焊盘45的焊线。在图5(B)所示的结构中，与设置于金属布线上的焊盘连接的焊线在设置于另一相邻金属布线上的焊盘上方通过。另一方面，可以使得图5(A)所示的结构中的两焊线之间的间隙“a′”大于图5(B)所示的结构中的两焊线之间的间隙“b′”，即a′＞b′。因而，通过制造图5(A)所示的结构，就能够在不通过其它焊盘上方的情况下丝焊，因此比制造图5(B)所示的结构更容易。同时，引线芯片中的焊盘的排列并不限于上述实施例。
在图4所示的实施例中，在引线芯片40中设置的金属布线41具有闭环结构。但是，本发明并不限于图4所示的实施例。例如，金属布线可具有图6所示的结构。此处，图6为图4所示的引线芯片40的修改实施例的平面图。
参照图6，在本修改实施例中，以闭环方式设置金属布线61-1，而以开环方式设置金属布线61-2，在该开环方式中，环并不完全封闭，环的一部分为打开的。
在该实施例中，设有多条金属布线61，并且单条金属布线61设有三个或更多焊盘。因此，能够选择以及使用位于适合于半导体芯片组合的良好位置的焊盘。
与图4所示的引线芯片40一样，图6所示的引线芯片60，例如放置在面积大于引线芯片60的某半导体芯片与面积小于引线芯片60且设置在未设有金属布线61的引线芯片60的中部的另一半导体芯片之间。引线芯片60的焊盘65经由指定焊线连接至形成于各自半导体芯片中的焊盘。
接下来，参照图7至图10说明本发明的引线芯片的第二实施例。
图7为本发明的第二实施例的引线芯片的平面图。参照图7，沿本发明的第二实施例的引线芯片70的长边，以平行方式设置四条金属布线71。在每条金属布线71中，以指定间隙形成三个或更多焊盘75。
如以下参照图14所述，本实施例的引线芯片70和某半导体芯片并排设置在其它半导体芯片上。引线芯片70的焊盘75经由指定焊线连接至形成于各自半导体芯片中的焊盘。
与第一实施例相同，在本实施例中，在引线芯片70中设置由金属制成的布线71。在单条金属布线71中设置三个或更多焊盘75。因此，能够选择以及使用位于适合于半导体芯片组合的良好位置的焊盘。
与第一实施例相同，在本实施例中，在设置多条金属布线的方向上，金属布线的焊盘的位置偏离与该金属布线相邻的另一金属布线的焊盘的位置。但是，本发明并不限于此。
在图7所示的实施例中，平行设置四条金属布线71。但是，本发明并不限于此。金属布线71的排列可以是图8至图10所示的结构之一。此处，图8为图7所示的本发明的第二实施例的引线芯片的第一修改实例的引线芯片的平面图。图9为图7所示的本发明的第二实施例的引线芯片的第二修改实例的引线芯片的平面图。图10为图7所示的本发明的第二实施例的引线芯片的第三修改实例的引线芯片的平面图。
参照图8，本发明的第二实施例的引线芯片70的第一修改实例的引线芯片80包括三条金属布线81-1至81-3。更具体地说，设有以基本为缺一边的矩形形成的金属布线81-2，从而包围以基本缺一边的矩形形成的金属布线81-1的一部分。此外，在与设置金属布线81-3的方向基本垂直的方向上设置金属布线81-1和81-2的一部分。因此，例如，在焊线连接至图8中虚线所示的金属布线81-2的两焊盘85-1和85-2的情况下，与没有这种结构的情况相比，焊线的线长(wire length)可以缩短长度“C”。在图8所示的实施例中，金属布线81-1和81-2的部分，即连接焊盘85-1和85-2的金属布线部分，设置在与设置金属布线81-1和81-2的其它部分的方向基本垂直的方向上。但是，本发明并不限于此。金属布线81-1和81-2的部分可以指定角度弯曲。
参照图9，本发明的第二实施例的引线芯片70的第二修改实例的引线芯片90包括三条金属布线91-1至91-3。更具体地说，设有以基本缺一边的矩形形成的金属布线91-2，以使其被以基本缺一边的矩形形成的金属布线91-1包围。此外，在与设置金属布线91-3的方向基本垂直的方向上设置金属布线91-1和91-2的一部分。因此，与图8所示的情况相同，焊线的线长可以缩短。与图8所示的实施例一样，在图9所示的实施例中，金属布线91-1和91-2的一部分设置在与设置金属布线91-1和91-2的其它部分的方向基本垂直的方向上。但是，本发明并不限于此。金属布线91-1和91-2的部分可以指定角度弯曲。
接着，参照图10，本发明的第二实施例的引线芯片70的第三修改实例的引线芯片100包括两条金属布线101-1和101-2。金属布线101-1设置在引线芯片100的第一层中。金属布线101-2设置在设置于该第一层上的第二层中。因此，通过布置设有金属布线的多层并为各分离层设置金属布线，可以设置图10所示的互相交叉的多条金属布线。
另外，在图8至图10的实例中，设置多条金属布线81-1至81-3、91-1至91-3或101-1至101-2，并在单条金属布线中设置三个或更多焊盘85、95或105。因此，在图8至图10所示的实施例中，能够使用并适当选择位置适合于半导体芯片的组合的焊盘。
与图7所示的引线芯片70一样，图8至图10所示的引线芯片80、90或100和某半导体芯片并排设置于另一半导体芯片上。引线芯片80、90或100的焊盘85、95或105通过指定焊线连接至形成于各自半导体芯片中的焊盘。
【半导体器件】
接下来，说明设有上述引线芯片的半导体器件的实施例。
在以下说明中，第一半导体芯片和第二半导体芯片具有基本呈矩形的结构。可在由例如硅制成的衬底上形成半导体存储器、半导体集成电路等(未示出)。
图11为本发明的第三实施例的引线芯片的平面图。参照图11，本发明第三实施例的半导体器件110包括第一半导体芯片11、第二半导体芯片18、以及本发明第一实施例的引线芯片40等。
第一半导体芯片11设置在具有焊盘19的引线框架上。在第一半导体芯片11上沿第一半导体芯片11的四边设有多个焊盘9。部分焊盘9连接至半导体器件110的引线框架的焊盘19。
本实施例的引线芯片40放置在面积大于引线芯片40的第一半导体芯片11与面积小于引线芯片40的第二半导体芯片18之间。引线芯片40通过粘合剂(图11未示出)固定至位于第一半导体芯片11的外边缘的焊盘9形成区的内侧。如参照图4所述，沿引线芯片40的四边以同心状态设置由金属制成的四条布线41-1至41-4。在金属布线41-1至41-4中的每一条金属布线中，以指定间隙形成三个或更多焊盘45。
第二半导体芯片18固定至未设有金属布线41-1至41-4的引线芯片40的基本中部。在第二半导体芯片18上设有四个焊盘12。每个焊盘12经由焊线111连接至引线芯片40的焊盘45。
在设置于引线芯片40上的多个焊盘45中，在设有连接至焊线111的另一焊盘(焊盘45-3a)的金属布线(例如金属布线41-3)上的焊盘45(例如焊盘45-3b)经由焊线112，连接至第一半导体芯片11的焊盘9。此外，位于第一半导体芯片11的四边的部分焊盘9通过用于引线框架的焊线117连接至半导体器件110的引线框架的焊盘19。
因此，在本实施例中，引线芯片40用于对多个半导体芯片例如第一半导体芯片11和第二半导体芯片18等进行布线，或用于对半导体芯片或半导体封装的引线框架进行布线。此外，使用设置于引线芯片40中的焊盘45。因此，能够防止图1所示的半导体器件10的状态，即焊线的交叉，从而可以缩短线长。
与具有图2所示的引线芯片25的半导体器件20的第一实例相比，在图11所示的引线芯片40上设置的焊盘多于设置在引线芯片25上的焊盘。更具体地说，在引线芯片40上设置多条金属布线41，并在每条金属布线41中形成三个或更多焊盘45。
因而，无论引线芯片所转接的半导体芯片上的焊盘的排列结构如何，均能够丝焊该引线芯片的焊盘以及该半导体芯片的焊盘。因此，按照本实施例的引线芯片，不必为所转接的半导体芯片的每一组合改变引线芯片40的结构。相反地，引线芯片40可普遍应用于半导体芯片的各种组合。因此，通过大量生产引线芯片，能够降低半导体器件的制造成本，并缩短半导体器件的开发周期。
形成于单条金属布线41上的焊盘的数目并不限于图11所示的实施例。焊盘的数目越多，引线芯片的广泛实用性就越高。
尽管在图11所示的半导体器件110中设有本发明的第一实施例的图4所示的引线芯片40，但可以设置例如图6所示的引线芯片60取代引线芯片40。
此外，在图11所示的半导体器件110中，引线芯片40设置于第一半导体芯片11上，而第二半导体芯片18设置于引线芯片40上。但是，本发明并不限于此。可以使用图12所示的结构。此处，图12为本发明的第四实施例的引线芯片的平面图。
参照图12，在本发明第四实施例的半导体器件120中，在引线芯片40上设置面积小于引线芯片40的第一半导体芯片211，并且在第一半导体芯片211上设置面积小于第一半导体芯片211的第二半导体芯片218。
因此，与本发明的第三实施例的半导体器件110一样，在本实施例中，引线芯片40用于对多个半导体芯片例如第一半导体芯片211和第二半导体芯片218等进行布线，或用于对半导体芯片和半导体封装的引线框架的焊盘19进行布线。此外，使用设置于引线芯片40中的焊盘45。因此，能够防止图1所示的半导体器件10的状态，即焊线的交叉，从而可以缩短线长。
在图12所示的一实施例中，可以使用图6所示的引线芯片60取代引线芯片40。
半导体器件110的结构可以为图13所示的结构。此处，图13为本发明的第五实施例的引线芯片的平面图。
参照图13，在本发明第五实施例的半导体器件130中，第一半导体芯片311和第二半导体芯片318并排设置在引线芯片40上。引线芯片40的面积大于第一半导体芯片311和第二半导体芯片318。
因此，与本发明的第三实施例的半导体器件110一样，在本实例中，引线芯片40用于对多个半导体芯片例如第一半导体芯片311和第二半导体芯片318等进行布线，或用于对半导体芯片和半导体封装的引线框架的焊盘19进行布线。此外，使用设置于引线芯片40中的焊盘45。因此，能够防止图1所示的半导体器件10的状态，即焊线的交叉，从而可以缩短线长。
在图13所示的实例中，可以使用图6所示的引线芯片60取代引线芯片40。
图14为本发明的第六实施例的引线芯片的平面图。
参照图14，本发明的第六实施例的半导体器件140包括本发明第二实施例的引线芯片70。在半导体器件140中，引线芯片70和第二半导体芯片18并排设置于第一半导体芯片11上。引线芯片70和第二半导体芯片18通过粘合剂(图14中未示出)固定至第一半导体芯片11。
由于本实施例的第一半导体芯片11和第二半导体芯片18的结构与第三实施例的第一半导体芯片11和第二半导体芯片18的结构相同，因此省略其说明。
如上所述，沿本发明的第二实施例的引线芯片70的长边，以平行方式设置四条金属布线71。在每条金属布线71中以指定间隙形成三个或更多焊盘75。
在设置于引线芯片70上的多个焊盘75中，在设有连接至焊线171的另一焊盘75-1的金属布线71上的焊盘75-2经由焊线172，连接至第一半导体芯片11的焊盘9。此外，焊盘9通过焊线173连接至半导体器件110的引线框架的焊盘19。
因此，在本实施例中，引线芯片70用于对多个半导体芯片例如第一半导体芯片11和第二半导体芯片18等进行布线，或用于对半导体芯片和半导体封装的引线框架的焊盘19进行布线。此外，使用设置于引线芯片70中的焊盘75。因此，能够防止图1所示的半导体器件10的状态，即焊线的交叉，从而可以缩短布线长度。
与具有图3所示的引线芯片35的半导体器件30的第二实例相比，在图14所示的半导体器件140的引线芯片70上设置的焊盘多于在引线芯片35上设置的焊盘。更具体地说，在引线芯片70上设置多条金属布线71，并在每条金属布线71中形成三个或更多焊盘75。
因而，与本发明的第三实施例的半导体器件110一样，无论引线芯片所转接的半导体芯片上的焊盘的排列结构如何，均能够丝焊该引线芯片的焊盘以及该半导体芯片的焊盘。因此，与图3所示的引线芯片35相比，本实施例的引线芯片70具有更高的广泛实用性，以及通过大量生产引线芯片，能够降低半导体器件的制造成本并缩短半导体器件的开发周期。
与本发明的第三实施例的半导体器件110一样，在本实施例中，在单条金属布线71上形成的焊盘的数目并不限于图14所示数目。焊盘的数目越多，引线芯片的广泛实用性就越高。
图15为本发明的第七实施例的引线芯片的平面图。
参照图15，本发明的第七实施例的半导体器件150包括本发明第二实施例的两个引线芯片70。引线芯片70和第二半导体芯片18并排设置于第一半导体芯片11上。
如上所述，与图3所示的引线芯片35相比，引线芯片70可广泛应用，并且如本实施例，通过设置多个引线芯片70，能够符合与所需半导体芯片的组合。
因此，与本发明的第六实施例的半导体器件140一样，在本实施例中，引线芯片70用于通过焊线171和焊线172布线多个半导体芯片，例如第一半导体芯片11和第二半导体芯片18，或用于通过焊线174布线半导体封装的半导体芯片和引线框架的焊盘19。此外，使用设置于引线芯片70中的焊盘75。因此，能够防止图1所示的半导体器件10的状态，即焊线的交叉，从而可以缩短布线长度。
在图14和图15所示的实施例中，在第一半导体芯片11上并排设置引线芯片70和第二半导体芯片18。但是，本发明并不限于此。例如，可在相同表面上适当设置第一半导体芯片11、引线芯片70以及第二半导体芯片18。在这种情况下，可以获得相同效果。
因而，本发明的引线芯片不仅可以广泛和普遍应用于与该继电板所转接的半导体芯片的特定组合，而且可广泛和普遍应用于该半导体芯片与其它半导体芯片的多种组合。因此，本发明的引线芯片可广泛应用并可容易地大量制造。因此，通过大量生产引线芯片，能够降低半导体器件的制造成本并缩短半导体器件的开发周期。
本发明并不限于这些实施例，但可以在不偏离本发明的范围的情况下做改变和修改。
例如，在上述实施例中，设置引线芯片、第一半导体芯片以及第二半导体芯片，以暴露引线芯片、第一半导体芯片以及第二半导体芯片的焊盘。但是，本发明并不限于此。例如，本发明可用于如下结构：在单个半导体芯片下设置形成有印刷线路的衬底，并且该半导体芯片的焊盘通过焊球等连接至该印刷线路，以使该引线芯片设置于该半导体芯片上。
本专利申请基于2005年7月20日申请的日本优先权专利申请No.2005-210390，在此通过参考援引其全部内容。

Claims (16)

1.一种继电板，该继电板设置于设有多个半导体芯片的半导体封装中，该继电板转接用于对所述多个半导体芯片进行布线的线或用于对该半导体封装的引线框架和该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
2.如权利要求1所述的继电板，其中所述多条布线中的至少一条布线以同心方式设置于该继电板的主表面上。
3.如权利要求2所述的继电板，其中以同心方式设置于该继电板的该主表面上的该布线的一部分以开环方式设置于该继电板的该主表面上。
4.如权利要求1所述的继电板，其中所述多条布线中的至少两条布线以互相平行的方式设置于该继电器板的主表面上。
5.如权利要求1所述的继电板，其中所述多条布线中的至少一条布线以该布线的一部分弯曲成指定角度的状态设置于该继电板的主表面上。
6.如权利要求1所述的继电板，其中由所述多条布线的第一布线连接的焊盘的位置，在设置所述多条布线的方向上偏离由与所述多条布线的第一布线相邻的所述多条布线的第二布线连接的焊盘的位置。
7.如权利要求1所述的继电板，其中该继电板还包含：
多个层；
其中所述多条布线中的至少一条布线设置在与设有另一布线的层不同的层中。
8.如权利要求1所述的继电板，其中该继电器板还包含：
单个层；
其中所述多条布线设置在该单个层中。
9.如权利要求1所述的继电板，其中该继电板的材料选自由硅、陶瓷、酚醛树脂、玻璃环氧树脂、聚酰亚胺膜、和聚乙烯对苯二甲酸酯膜构成的组。
10.一种半导体器件，该半导体器件具有如下结构：在第一半导体芯片上设有继电板，该继电板上设有第二半导体芯片，并且该第一半导体芯片、该第二半导体芯片、和该继电器板被封装；
该继电板转接用于对所述半导体芯片进行布线的线或用于对该半导体器件的引线框架和该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
11.如权利要求10所述的半导体器件，其中所述多条布线中的至少一条布线以同心方式设置于该继电板的主表面上。
12.如权利要求11所述的半导体器件，其中由所述多条布线的第一布线连接的焊盘的位置，在设置所述多条布线的方向上偏离由与所述多条布线的第一布线相邻的所述多条布线的第二布线连接的焊盘的位置。
13.一种半导体器件，该半导体器件具有如下结构：第二半导体芯片和继电板并排设置于第一半导体芯片上，并且该第一半导体芯片、该第二半导体芯片、和该继电板被封装；
该继电板转接用于对所述半导体芯片进行布线的线或用于对该半导体器件的引线框架和该半导体芯片进行布线的线，该继电板包括：
多条布线，每条布线连接至少三个焊盘。
14.如权利要求13所述的半导体器件，其中在该第一半导体芯片上设有多个该继电板。
15.如权利要求13所述的半导体器件，其中所述多条布线中的至少两条布线以互相平行的方式设置于该继电板的主表面上。
16.如权利要求1所述的半导体器件，其中由所述多条布线的第一布线连接的焊盘的位置，在设置所述多条布线的方向上偏离由与该第一布线相邻的所述多条布线的第二布线连接的焊盘的位置。
CN2005101136368A 2005-07-20 2005-10-11 继电板及具有继电板的半导体器件 Expired - Fee Related CN1901178B (zh)

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CN106098659A (zh) * 2015-04-28 2016-11-09 株式会社东芝 半导体装置
CN106098659B (zh) * 2015-04-28 2018-12-14 东芝存储器株式会社 半导体装置
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US20070018339A1 (en) 2007-01-25
JP4703300B2 (ja) 2011-06-15
KR100773842B1 (ko) 2007-11-06
US7608925B2 (en) 2009-10-27
CN1901178B (zh) 2010-05-05

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