CN106098659B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106098659B
CN106098659B CN201610016717.4A CN201610016717A CN106098659B CN 106098659 B CN106098659 B CN 106098659B CN 201610016717 A CN201610016717 A CN 201610016717A CN 106098659 B CN106098659 B CN 106098659B
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China
Prior art keywords
semiconductor chip
wiring
terminal
convex block
face
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CN201610016717.4A
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CN106098659A (zh
Inventor
稻垣真野
小柳胜
伊东干彦
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Kioxia Corp
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Toshiba Memory Corp
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Priority to CN201811382712.9A priority Critical patent/CN110010583B/zh
Publication of CN106098659A publication Critical patent/CN106098659A/zh
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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Abstract

实施方式的半导体装置具备：第1半导体芯片；第1配线及第2配线，设置在所述第1半导体芯片的第1面的上方；第1端子，与所述第1配线的一端及所述第2配线的一端连接，且与外部连接；第2端子，与所述第1配线的另一端连接；及第3端子，与所述第2配线的另一端连接，且与所述第2端子连接。

Description

半导体装置
相关申请案
本申请案享有以美国临时专利申请案62/153,925号(申请日：2015年4月28日)及美国专利申请案14/844,602号(申请日：2015年9月3日)为基础申请案的优先权。本申请案通过参照这些基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
为了在半导体装置中增大存储器容量而提出有多芯片封装。在多芯片封装中，将多个核心芯片(半导体芯片)积层在封装基板上而进行封装。作为将多个核心芯片积层的方式，提出有TSV(Through Silicon Via，硅穿孔)方式。
在TSV方式中，在各核心芯片设置有TSV，且核心芯片间的TSV通过凸块(焊球)而连接。另外，在最下层的核心芯片的下表面上设置有再配线层(RDL：Re-DistributionLayer)，经由该再配线层而将核心芯片与封装基板连接。另外，在封装基板与核心芯片之间设置有接口芯片。接口芯片经由再配线层而连接于封装基板及核心芯片。经由这种再配线层而在芯片与基板之间传输电源电压、接地电压、及各种信号等。
再配线层的配线的配线宽度由设计规则决定。因此，为了降低配线电阻而无法自由地增大配线宽度。因此，尤其是在对再配线层供给电源电压或接地电压的情况下，为了降低配线电阻，作为同一电源电压用或同一接地电压用的再配线层而需要多条(例如2条)配线。这些多条配线将核心芯片侧的端子或接口芯片侧的端子与封装基板侧的端子连接。此时，因再配线层的制程上的制约而无法通过多条配线设置闭合回路(必须设置开口部)。其原因在于，通过形成闭合回路而配线间的宽度变小或者形成有锐角的图案，由此树脂(绝缘层)难以均匀地埋入至配线间。
相对于此，如图6所示，在比较例中，在作为同一电源电压用或同一接地电压用的再配线层而形成有2条(一对)配线(配线330a、330b或配线330c、330d)时，在封装基板100侧设置有2个端子(凸块110f、110e或凸块110c、110d)。2条配线330各自的一端连接于该2个端子110的各者。由此，在封装基板100侧的端子110，2条配线330具有开口部。另一方面，2条配线330的另一端均连接于积层核心芯片300侧或接口芯片200侧的1个端子(通孔360或凸块210)。
然而，通过在封装100侧设置有多个(此处为2个)端子110，封装100侧的端子110的总数变多。通常，封装基板100侧的端子110的尺寸/间距较积层核心芯片300侧的端子360或接口芯片200侧的端子210的尺寸/间距大。因此，若封装基板100侧的端子110的数量变多，则封装尺寸变大。
另外，若封装基板100侧的端子110的数量变多，则通过端子110的布局而从一部分端子110至积层核心芯片300侧的端子360或接口侧的端子210为止的距离变远。其结果，产生如下问题，即端子间的配线330变长而引起信号、电源电压、及接地电压等的配线电阻、电容、及电感的增加。
此外，对于IO等高速信号，为了减少IO间的偏斜而必须使配线长度一致。在该情况下，必须使其他配线330的长度与最长的配线(端子间的距离较远的配线)330一致。因此，即使是端子间的距离较近的配线330，也必须设置虚设配线而使其长度与最长的配线330一致。其结果，配线330混杂而难以进行设计。
发明内容
本发明的实施方式提供一种能够缩小封装尺寸的半导体装置。
实施方式的半导体装置具备：第1半导体芯片；第1配线及第2配线，设置在所述第1半导体芯片的第1面的上方；第1端子，与所述第1配线的一端及所述第2配线的一端连接，且与外部连接；第2端子，与所述第1配线的另一端连接；及第3端子，与所述第2配线的另一端连接，且与所述第2端子连接。
附图说明
图1是表示实施方式的半导体装置的俯视图。
图2是表示实施方式的半导体装置的剖视图，且为沿着图1的A-A线的剖视图。
图3是将图2中的虚线部放大所得的剖视图。
图4是表示实施方式的半导体装置的剖视图，且为沿着图1的B-B线的剖视图。
图5是将图4中的虚线部放大所得的剖视图。
图6是表示比较例的半导体装置的俯视图。
具体实施方式
以下，参照附图对实施方式进行说明。在附图中对相同部分标注相同的参照符号。
＜实施方式＞
以下，利用图1至图5对实施方式的半导体装置进行说明。
在本实施方式中，在再配线层380内设置有例如同一电源电压用或同一接地电压用的2条配线330a、330b(或330c、330d)。针对这些配线330a、330b(或330c、330d)，在封装基板100侧设置有1个凸块110a(或凸块110b)，在接口芯片200侧设置有2个凸块210a、210b(或在积层核心芯片300侧设置有2个通孔360c、360d)。由此，可减少较大尺寸的凸块110的数量，从而可获得减短再配线层380内的配线330等效果。以下，对实施方式详细地进行说明。
[实施方式中的构成]
利用图1至图5对实施方式的半导体装置的构成进行说明。
图1是表示实施方式的半导体装置的俯视图。
如图1所示，实施方式的半导体装置包括封装基板100、接口芯片200、及积层核心芯片300。
封装基板100安装接口芯片200及积层核心芯片300。封装基板100与外部连接，从外部对封装基板100供给电源电压VCC或接地电压VSS。封装基板100将来自外部的电源电压VCC或接地电压VSS直接供给至积层核心芯片300。封装基板100将电源电压VCC或接地电压VSS供给至接口芯片200。或者，封装基板100将电源电压VCC或接地电压VSS经由接口芯片200供给至积层核心芯片300。此外，在经由接口芯片200的情况下，封装基板100并非仅供给电压，也将来自外部的信号(数据信号及指令信号等)IO供给至核心芯片300。
积层核心芯片300包含例如NAND(Not AND，与非)闪存等存储器电路、及存储器控制器。积层核心芯片300存储来自外部的数据等。
接口芯片200包含接口电路。接口电路包含逻辑电路、及模拟电路等。接口芯片200在封装基板100与积层核心芯片300之间传输信号IO、电源电压、及接地电压。
在俯视下，积层核心芯片300设置在封装基板100内。另外，接口芯片200设置在积层核心芯片300内的中央部。封装基板100的尺寸由积层核心芯片300的尺寸决定，并由这些决定封装尺寸。
在俯视下，在积层核心芯片300的平面尺寸内设置有多个凸块110、多条配线330、及多个通孔360。另外，在接口芯片200内设置有多个凸块210。
多个凸块110设置在第1方向(附图左右方向)上的积层核心芯片300的两端部，在两端部的各者沿着第2方向(附图上下方向)排列成例如2列。另外，排列在第1列的多个凸块110与排列在第2列的多个凸块110相互交错地配置。多个凸块110是与封装基板100电连接的端子。从外部对各凸块110供给信号IO、电源电压VCC、或接地电压VSS中的任一者。
多个凸块210设置在第1方向上的接口芯片200的两端部，且在两端部的各者沿着第2方向排列成2列。多个凸块210是经由接口芯片200而与积层核心芯片300电连接的端子。对排列在第1方向的一对凸块210a、210b供给同一信号IO、同一电源电压VCC、或同一接地电压VSS。
多个通孔360在接口芯片200外沿着第2方向与多个凸块210排列于同列。多个通孔360是与核心芯片300电连接的端子。对排列在第1方向的一对通孔360c、360d供给同一电源电压VDD或同一接地电压VCC。
配线330将任一凸块110与一对凸块210或者任一凸块110与一对通孔360连接。
更具体地说，配线330a的一端及配线330b的一端与同一凸块110a电连接。另外，配线330a的另一端与凸块210a电连接，配线330b的另一端与凸块210b电连接。由此，配线330a与配线330b在接口芯片200侧(凸块210a、210b侧)具有开口部。凸块210a与凸块210b在接口芯片200内电连接。另外，凸块210a及凸块210b也可经由接口芯片200而与积层核心芯片300电连接。
另外，配线330c的一端及配线330d的一端与同一凸块110b电连接。另外，配线330c的另一端与通孔360c电连接，配线330d的另一端与通孔360d电连接。由此，配线330c与配线330d在积层核心芯片300侧(通孔360c、360d侧)具有开口部。通孔360c与通孔360d在积层核心芯片300内电连接。
另外，信号IO用的多个凸块110与多个凸块210之间分别具有不同的距离。这些全部利用同一长度的配线330电连接。因此，在距离较短的凸块110与凸块210之间的一部分设置有冗余配线部分。
此处，所谓冗余配线部分是指配线330中在凸块110与凸块210之间多余地加长的部分，实际上具有传输信号IO的功能。
此外，通过2条(一对)配线330将凸块110与凸块210或通孔360连接，但也可利用3条以上的配线连接。在该情况下，配线330的数量与凸块210或通孔360的数量相同。另外，在图1中，作为信号IO用而使用有1条配线330，但也可与电源电压用及接地电压用同样地使用2条(一对)配线330。
图2是表示实施方式的半导体装置的剖视图，且为沿着图1的A-A线的剖视图。
如图2所示，在A-A线剖面中，在封装基板(半导体基板)100的下表面上设置有凸块120。在半导体装置为BGA(Ball Grid Array，球栅阵列)封装的情况下，凸块120为焊球。封装基板100经由凸块120而与外部电连接。
在封装基板100的上表面上设置有接口芯片(半导体芯片)200。
在接口芯片200及封装基板100的上表面的上方设置有积层核心芯片300。积层核心芯片300包含多个核心芯片(半导体芯片)300a-300h。多个核心芯片300a-300h从下方侧依次积层。在除最上层的核心芯片300h以外的各核心芯片300a-300g设置有从其上表面到达至下表面的TSV(贯通电极)310。而且，在各TSV310间设置有凸块320。
在最下层的核心芯片300a的下表面上设置有配线330。在该配线330与接口芯片200之间设置有凸块210。另一方面，在配线330与封装基板100之间设置有凸块110。配线330与接口芯片200之间的距离小于配线330与封装基板100的距离。因此，凸块210的尺寸(例如平面尺寸)小于凸块110的尺寸。
以下，利用图3对封装基板100、接口芯片200、及核心芯片300的更详细的连接剖面进行说明。
图3是将图2中的虚线部放大所得的剖视图。此外，在图3中，为了便于说明而表示配置在不同的剖面的凸块110a、及凸块210a、210b、210c。
如图3所示，在封装基板100的上表面上设置有绝缘层120。在该绝缘层120上设置有接口芯片200。因此，封装基板100的上表面与接口芯片200的下表面之间被绝缘分离。另外，在封装基板100的上表面上设置有电极垫130。
在接口芯片200的上表面上设置有电极垫220、240及绝缘层230。
在最下层的核心芯片300a的下表面上设置有绝缘层350，在该绝缘层350的下表面上设置有再配线层380。再配线层380包含配线330(配线330a、330b、330c)及绝缘层340。绝缘层340包含例如树脂。
在配线330a、330b与电极垫130之间设置有凸块110a。另外，在配线330a与电极垫220之间设置有凸块210a，在配线330b与电极垫220之间设置有凸块210b。
也就是说，封装基板100与接口芯片200经由电极垫130、凸块110a、配线330a、凸块210a、及电极垫220而电连接，并且经由电极垫130、凸块110a、配线330b、凸块210b、及电极垫220而电连接。
另外，电极垫220经由接口芯片200内而与电极垫240电连接。在配线330e与电极垫240之间设置有凸块210e。也就是说，电极垫220还经由接口芯片200、电极垫240、凸块210e、及配线330e而与核心芯片300a(积层核心芯片300)电连接。
图4是表示实施方式的半导体装置的剖视图，且为沿着图1的B-B线的剖视图。
如图4所示，在B-B线剖面中，不同于A-A线剖面，而未在封装基板100的上表面上设置接口芯片200及凸块210。另外，配线330的一部分未经由接口芯片200而与核心芯片300a电连接。
以下，利用图5对封装基板100及核心芯片300的更详细的连接剖面进行说明。
图5是将图4中的虚线部放大所得的剖视图。此外，在图5中，为了便于说明而表示配置在不同的剖面的凸块110b、及通孔360c、360d。
如图5所示，在封装基板100的上表面上设置有绝缘层120及电极垫140。
在最下层的核心芯片300a的下表面上设置有电极垫370。电极垫370与核心芯片300a内的TSV310电连接。以覆盖电极垫370的方式设置有绝缘层350，在该绝缘层350的下表面上设置有再配线层380。再配线层380包含配线330(配线330c、330d)与绝缘层340。
在配线330c、330d与电极垫140之间设置有凸块110b。另外，在绝缘层350内且在配线330c与电极垫370之间设置有通孔360c，在绝缘层350内且在配线330d与电极垫370之间设置有通孔360d。此处，通孔360的尺寸(例如平面尺寸)小于凸块110的尺寸。
也就是说，封装基板100与核心芯片300a(积层核心芯片300)经由电极垫140、凸块110b、配线330c、通孔360c、及电极垫370而电连接，并且经由电极垫140、凸块110b、配线330d、通孔360d、及电极垫370而电连接。
[实施方式的效果]
根据本实施方式，在再配线层380内设置有例如同一电源电压用或同一接地电压用的2条配线330a、330b。配线330a、330b对接口芯片200供给电源电压VCC或接地电压VSS。针对这些配线330a、330b，在封装基板100侧设置有1个端子(凸块110a)，且在接口芯片200侧设置有2个端子(凸块210a、210b)。而且，配线330a、330b的一端共通地连接于凸块110a，另一方面，配线330a、330b的另一端分别连接于凸块210a、210b的各者。由此，通过增加接口芯片200侧的凸块210的数量而设置配线330a、330b的开口部。也就是说，不增加封装基板100侧的大尺寸的凸块110的数量而设置配线330a、330b。
根据所述构造，可相对于图6所示的比较例而减少较大尺寸的凸块110的数量。由此，可缩小积层核心芯片300及封装基板100的尺寸，从而可谋求封装尺寸的缩小。
另外，通过减少凸块110的数量，而位于芯片端的凸块110与凸块210的距离与比较例相比变近。其结果，端子间的配线330变短，从而可使配线电阻、电容、及电感降低。
另外，可使IO用的多条配线330中的最长的配线330较比较例短。由此，可减小IO用的多条配线间的配线长度的差，从而可削减多余的冗余配线部分。
另外，通过减短配线长度或者削减冗余配线部分而可容易进行配线设计。此外，通过配线设计的自由度提高，而可容易改善装置特性。
另外，根据本实施方式，在再配线层380内设置有例如同一电源电压用或同一接地电压用的2条配线330c、330d。配线330c、330d对积层核心芯片300供给电源电压或接地电压。针对这些配线330c、330d，在封装基板100侧设置有1个端子(凸块110)，且在积层核心芯片300侧设置有2个端子(通孔360c、360d)。而且，配线330c、330d的一端共通地连接于凸块110，另一方面，配线330c、330d的另一端分别连接于通孔360c、360d的各者。由此，可获得与所述相同的效果。
对本发明的若干实施方式进行了说明，但这些实施方式是作为例而提出来者，并未意图限定发明的范围。这些新颖的实施方式能以其他多种方式实施，且可在不脱离发明的主旨的范围内进行各种省略、置换、变更。这些实施方式或其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。

Claims (13)

1.一种半导体装置，其特征在于具备：
第1半导体芯片；
第1配线及第2配线，设置在所述第1半导体芯片的第1面的上方；
第1端子，与所述第1配线的一端及所述第2配线的一端电连接，且与外部电连接；
第2端子，与所述第1配线的另一端电连接；及
第3端子，与所述第2配线的另一端电连接，且与所述第2端子电连接；
所述第2端子及所述第3端子电连接于所述第1半导体芯片的内部；
所述第2端子是在所述第1配线与所述第1半导体芯片之间设置的第1通孔；
所述第3端子是在所述第2配线与所述第1半导体芯片之间设置的第2通孔。
2.根据权利要求1所述的半导体装置，其特征在于：所述第1端子的尺寸大于所述第2端子及所述第3端子的尺寸。
3.根据权利要求1所述的半导体装置，其特征在于：还具备第1电极垫，该第1电极垫设置在所述第1半导体芯片与所述第1通孔及所述第2通孔之间，且将所述第1通孔与所述第2通孔电连接。
4.根据权利要求1所述的半导体装置，其特征在于：还具备基板，
所述基板的第1面经由第1凸块与外部电连接，所述基板的第2面与所述第1半导体芯片的所述第1面对向，
所述第1端子是在所述第1配线及所述第2配线与所述基板之间设置的第2凸块。
5.根据权利要求1所述的半导体装置，其特征在于还具备：
第3半导体芯片，设置在所述第1半导体芯片的第2面的上方；
第5凸块，设置在所述第1半导体芯片与所述第3半导体芯片之间；及
第1贯通电极，从所述第1半导体芯片的上表面到达至下表面；
所述第1半导体芯片与所述第3半导体芯片经由所述第1贯通电极及所述第5凸块而电连接。
6.根据权利要求1所述的半导体装置，其特征在于：所述第1半导体芯片包含存储数据的存储器电路。
7.根据权利要求5所述的半导体装置，其特征在于：所述第1半导体芯片、所述第3半导体芯片、及设置在所述第3半导体芯片的上方的第4半导体芯片包含存储数据的存储器电路。
8.一种半导体装置，其特征在于具备：
第1半导体芯片；
第1配线及第2配线，设置在所述第1半导体芯片的第1面的上方；
第1端子，与所述第1配线的一端及所述第2配线的一端电连接，且与外部电连接；
第2端子，与所述第1配线的另一端电连接；
第3端子，与所述第2配线的另一端电连接，且与所述第2端子电连接；
基板，具有经由第1凸块与外部电连接的第1面及与所述第1半导体芯片的所述第1面对向的第2面；及
第2半导体芯片，设置在所述基板与所述第1半导体芯片之间且所述基板的所述第2面上，
所述第2端子及所述第3端子与所述第2半导体芯片的内部连接，
所述第1端子是在所述第1配线及所述第2配线与所述基板之间设置的第2凸块，所述第2端子是在所述第1配线与所述第2半导体芯片之间设置的第3凸块，
所述第3端子是在所述第2配线与所述第2半导体芯片之间设置的第4凸块。
9.根据权利要求8所述的半导体装置，其特征在于：还具备第2电极垫，该第2电极垫设置在所述第2半导体芯片与所述第3凸块及所述第4凸块之间，且将所述第3凸块与所述第4凸块电连接。
10.根据权利要求9所述的半导体装置，其特征在于：所述第2电极垫经由所述第2半导体芯片而电连接于所述第1半导体芯片。
11.根据权利要求8所述的半导体装置，其特征在于：所述第2半导体芯片包含有在所述基板与所述第1半导体芯片之间传输信号及电压的接口电路。
12.一种半导体装置，其特征在于具备：
基板，具有第1面及与所述第1面对向的第2面；
第1凸块，设置在所述第1面；
第1半导体芯片，具有第1面及与所述第1面对向的第2面，该第1面与所述基板的第2面对向地配置；
第1配线及第2配线，设置在所述第1半导体芯片的所述第1面的上方；
第1端子，与所述第1配线的一端及所述第2配线的一端电连接，且与外部电连接；
第2端子，与所述第1配线的另一端电连接；
第3端子，与所述第2配线的另一端电连接，且与所述第2端子电连接；
第3半导体芯片，设置在所述第1半导体芯片的所述第2面的上方；
第5凸块，设置在所述第1半导体芯片与所述第3半导体芯片之间；
第1贯通电极，从所述第1半导体芯片的上表面到达至下表面；
第4半导体芯片，设置在所述第3半导体芯片的上方；
第6凸块，设置在所述第3半导体芯片与所述第4半导体芯片之间；
第2贯通电极，从所述第3半导体芯片的上表面到达至下表面；及
第2半导体芯片，设置在所述基板与所述第1半导体芯片之间且所述基板的所述第2面上，
所述第1半导体芯片、所述第3半导体芯片、及所述第4半导体芯片经由所述第1、第2贯通电极、及所述第5、第6凸块而电连接，
所述第2端子及所述第3端子与所述第2半导体芯片的内部连接，
所述第1端子是在所述第1配线及所述第2配线与所述基板之间设置的第2凸块，
所述第2端子是在所述第1配线与所述第2半导体芯片之间设置的第3凸块，
所述第3端子是在所述第2配线与所述第2半导体芯片之间设置的第4凸块。
13.根据权利要求12所述的半导体装置，其特征在于：所述第2半导体芯片包含有在所述基板与所述第1半导体芯片、所述第3半导体芯片、及所述第4半导体芯片之间传输信号及电压的接口电路。
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