CN106098659A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN106098659A CN106098659A CN201610016717.4A CN201610016717A CN106098659A CN 106098659 A CN106098659 A CN 106098659A CN 201610016717 A CN201610016717 A CN 201610016717A CN 106098659 A CN106098659 A CN 106098659A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (16)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811382712.9A CN110010583B (zh) | 2015-04-28 | 2016-01-11 | 半导体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562153925P | 2015-04-28 | 2015-04-28 | |
US62/153,925 | 2015-04-28 | ||
US14/844,602 | 2015-09-03 | ||
US14/844,602 US9589946B2 (en) | 2015-04-28 | 2015-09-03 | Chip with a bump connected to a plurality of wirings |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811382712.9A Division CN110010583B (zh) | 2015-04-28 | 2016-01-11 | 半导体装置 |
Publications (2)
Publication Number | Publication Date |
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CN106098659A true CN106098659A (zh) | 2016-11-09 |
CN106098659B CN106098659B (zh) | 2018-12-14 |
Family
ID=57205182
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811382712.9A Active CN110010583B (zh) | 2015-04-28 | 2016-01-11 | 半导体装置 |
CN201610016717.4A Active CN106098659B (zh) | 2015-04-28 | 2016-01-11 | 半导体装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811382712.9A Active CN110010583B (zh) | 2015-04-28 | 2016-01-11 | 半导体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9589946B2 (zh) |
CN (2) | CN110010583B (zh) |
TW (1) | TWI607543B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110447102A (zh) * | 2017-03-15 | 2019-11-12 | 东芝存储器株式会社 | 半导体存储装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6759874B2 (ja) * | 2016-09-01 | 2020-09-23 | 富士電機株式会社 | 電力変換装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861742B2 (en) * | 2001-01-18 | 2005-03-01 | Renesas Technology Corp. | Wafer level chip size package having rerouting layers |
CN1901178A (zh) * | 2005-07-20 | 2007-01-24 | 富士通株式会社 | 继电板及具有继电板的半导体器件 |
JP2008166408A (ja) * | 2006-12-27 | 2008-07-17 | Toshiba Corp | 回路板及び回路板の製造方法、並びに回路板を備えた電子機器 |
US20140038406A1 (en) * | 2006-04-24 | 2014-02-06 | Micron Technology, Inc. | Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer |
US20140264852A1 (en) * | 2008-08-08 | 2014-09-18 | Stmicroelectronics S.R.L. | Method for forming bumps in substrates with through vias |
JP2015018897A (ja) * | 2013-07-10 | 2015-01-29 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4746770B2 (ja) | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4068838B2 (ja) * | 2001-12-07 | 2008-03-26 | 株式会社日立製作所 | 半導体装置の製造方法 |
JP2004031790A (ja) * | 2002-06-27 | 2004-01-29 | Hitachi Maxell Ltd | 半導体チップ |
JP2004064016A (ja) * | 2002-07-31 | 2004-02-26 | Hitachi Maxell Ltd | 半導体チップ |
JP4615189B2 (ja) * | 2003-01-29 | 2011-01-19 | シャープ株式会社 | 半導体装置およびインターポーザチップ |
TW200504895A (en) * | 2003-06-04 | 2005-02-01 | Renesas Tech Corp | Semiconductor device |
US7078792B2 (en) * | 2004-04-30 | 2006-07-18 | Atmel Corporation | Universal interconnect die |
JP2005340741A (ja) * | 2004-05-31 | 2005-12-08 | Renesas Technology Corp | 半導体装置 |
US7342312B2 (en) | 2004-09-29 | 2008-03-11 | Rohm Co., Ltd. | Semiconductor device |
JP4890827B2 (ja) | 2004-09-29 | 2012-03-07 | ローム株式会社 | 半導体装置 |
JP4268607B2 (ja) * | 2005-09-30 | 2009-05-27 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置に配設される中継部材及び半導体装置 |
JP4595823B2 (ja) * | 2006-01-24 | 2010-12-08 | 株式会社デンソー | ボールグリッドアレイ |
JP2009170561A (ja) * | 2008-01-15 | 2009-07-30 | Panasonic Corp | 配線基板およびその製造方法 |
JP5405785B2 (ja) * | 2008-09-19 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5355499B2 (ja) | 2010-06-03 | 2013-11-27 | 株式会社東芝 | 半導体装置 |
JP2011258867A (ja) * | 2010-06-11 | 2011-12-22 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
JP6114577B2 (ja) * | 2013-03-06 | 2017-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2015
- 2015-09-03 US US14/844,602 patent/US9589946B2/en active Active
- 2015-12-11 TW TW104141792A patent/TWI607543B/zh active
-
2016
- 2016-01-11 CN CN201811382712.9A patent/CN110010583B/zh active Active
- 2016-01-11 CN CN201610016717.4A patent/CN106098659B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6861742B2 (en) * | 2001-01-18 | 2005-03-01 | Renesas Technology Corp. | Wafer level chip size package having rerouting layers |
CN1901178A (zh) * | 2005-07-20 | 2007-01-24 | 富士通株式会社 | 继电板及具有继电板的半导体器件 |
US20140038406A1 (en) * | 2006-04-24 | 2014-02-06 | Micron Technology, Inc. | Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer |
JP2008166408A (ja) * | 2006-12-27 | 2008-07-17 | Toshiba Corp | 回路板及び回路板の製造方法、並びに回路板を備えた電子機器 |
US20140264852A1 (en) * | 2008-08-08 | 2014-09-18 | Stmicroelectronics S.R.L. | Method for forming bumps in substrates with through vias |
JP2015018897A (ja) * | 2013-07-10 | 2015-01-29 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110447102A (zh) * | 2017-03-15 | 2019-11-12 | 东芝存储器株式会社 | 半导体存储装置 |
CN110447102B (zh) * | 2017-03-15 | 2024-03-05 | 铠侠股份有限公司 | 半导体存储装置 |
Also Published As
Publication number | Publication date |
---|---|
CN110010583B (zh) | 2023-11-21 |
CN110010583A (zh) | 2019-07-12 |
US20160322341A1 (en) | 2016-11-03 |
TW201639107A (zh) | 2016-11-01 |
US9589946B2 (en) | 2017-03-07 |
CN106098659B (zh) | 2018-12-14 |
TWI607543B (zh) | 2017-12-01 |
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