TWI607543B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI607543B
TWI607543B TW104141792A TW104141792A TWI607543B TW I607543 B TWI607543 B TW I607543B TW 104141792 A TW104141792 A TW 104141792A TW 104141792 A TW104141792 A TW 104141792A TW I607543 B TWI607543 B TW I607543B
Authority
TW
Taiwan
Prior art keywords
wiring
semiconductor wafer
terminal
bump
wafer
Prior art date
Application number
TW104141792A
Other languages
English (en)
Other versions
TW201639107A (zh
Inventor
稲垣真野
小柳勝
伊東幹彥
Original Assignee
東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝記憶體股份有限公司 filed Critical 東芝記憶體股份有限公司
Publication of TW201639107A publication Critical patent/TW201639107A/zh
Application granted granted Critical
Publication of TWI607543B publication Critical patent/TWI607543B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

半導體裝置 [相關申請案]
本申請案享受以美國臨時專利申請案62/153,925號(申請日：2015年4月28日)及美國專利申請案14/844,602號(申請日：2015年9月3日)為基礎申請案之優先權。本申請案藉由參照該等基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置。
為了於半導體裝置中增大記憶體容量而提出有多晶片封裝。於多晶片封裝中，將複數個核心晶片(半導體晶片)積層於封裝基板上而進行封裝。作為將複數個核心晶片積層之方式，提出有TSV(Through Silicon Via，矽穿孔)方式。
於TSV方式中，於各核心晶片設置有TSV，且核心晶片間之TSV藉由凸塊(焊球)而連接。又，於最下層之核心晶片之下表面上設置有再配線層(RDL：Re-Distribution Layer)，經由該再配線層而將核心晶片與封裝基板連接。又，於封裝基板與核心晶片之間設置有介面晶片。介面晶片經由再配線層而連接於封裝基板及核心晶片。經由此種再配線層而於晶片與基板之間傳輸電源電壓、接地電壓、及各種信號等。
再配線層之配線之配線寬度由設計規則決定。因此，為了降低 配線電阻而無法自由地增大配線寬度。因此，尤其是於對再配線層供給電源電壓或接地電壓之情形時，為了降低配線電阻，作為同一電源電壓用或同一接地電壓用之再配線層而需要複數條(例如2條)配線。該等複數條配線將核心晶片側之端子或介面晶片側之端子與封裝基板側之端子連接。此時，因再配線層之製程上之制約而無法藉由複數條配線設置閉合迴路(必須設置開口部)。其原因在於，藉由形成閉合迴路而配線間之寬度變小或者形成有銳角之圖案，從而樹脂(絕緣層)難以均勻地埋入至配線間。
相對於此，如圖6所示，於比較例中，於作為同一電源電壓用或同一接地電壓用之再配線層而形成有2條(一對)配線(配線330a、330b或配線330c、330d)時，於封裝基板100側設置有2個端子(凸塊110f、110e或凸塊110c、110d)。2條配線330各自之一端連接於該2個端子110之各者。藉此，於封裝基板100側之端子110，2條配線330具有開口部。另一方面，2條配線330之另一端均連接於積層核心晶片300側或介面晶片200側之1個端子(通孔360或凸塊210)。
然而，藉由在封裝100側設置有複數個(此處為2個)端子110，而封裝100側之端子110之總數變多。通常，封裝基板100側之端子110之尺寸/間距較積層核心晶片300側之端子360或介面200側之端子210之尺寸/間距大。因此，若封裝基板100側之端子110之數量變多，則封裝尺寸變大。
又，若封裝基板100側之端子110之數量變多，則藉由端子110之佈局而自一部分端子110至積層核心晶片300側之端子360或介面側之端子210為止之距離變遠。其結果，產生如下問題，即端子間之配線330變長而引起信號、電源電壓、及接地電壓等之配線電阻、電容、及電感之增加。
進而，對於IO等高速信號，為了減少IO間之偏斜而必須使配線 長度一致。於該情形時，必須使其他配線330之長度與最長之配線(端子間之距離較遠之配線)330一致。因此，即便為端子間之距離較近之配線330，亦必須設置虛設配線而使其長度與最長之配線330一致。其結果，配線330混雜而難以進行設計。
本發明之實施形態提供一種能夠縮小封裝尺寸之半導體裝置。
實施形態之半導體裝置具備：第1半導體晶片；第1配線及第2配線，其等設置於上述第1半導體晶片之第1面之上方；第1端子，其與上述第1配線之一端及上述第2配線之一端連接，且連接於外部；第2端子，其與上述第1配線之另一端連接；及第3端子，其與上述第2配線之另一端連接，且與上述第2端子連接。
100‧‧‧封裝基板
110‧‧‧端子
110a‧‧‧凸塊
110b‧‧‧凸塊
110c‧‧‧凸塊
110d‧‧‧凸塊
110e‧‧‧凸塊
110f‧‧‧凸塊
120‧‧‧凸塊
130‧‧‧電極墊
140‧‧‧電極墊
200‧‧‧介面晶片
210‧‧‧凸塊
210a‧‧‧凸塊
210b‧‧‧凸塊
210e‧‧‧凸塊
220‧‧‧電極墊
230‧‧‧絕緣層
240‧‧‧電極墊
300‧‧‧積層核心晶片
300a‧‧‧核心晶片
300b‧‧‧核心晶片
300c‧‧‧核心晶片
300d‧‧‧核心晶片
300e‧‧‧核心晶片
300f‧‧‧核心晶片
300g‧‧‧核心晶片
300h‧‧‧核心晶片
310‧‧‧TSV
320‧‧‧凸塊
330‧‧‧配線
330a‧‧‧配線
330b‧‧‧配線
330c‧‧‧配線
330d‧‧‧配線
330e‧‧‧配線
340‧‧‧絕緣層
350‧‧‧絕緣層
360‧‧‧通孔
360c‧‧‧通孔
360d‧‧‧通孔
370‧‧‧電極墊
380‧‧‧再配線層
IO‧‧‧信號
VCC‧‧‧電源電壓
VSS‧‧‧接地電壓
圖1係表示實施形態之半導體裝置之俯視圖。
圖2係表示實施形態之半導體裝置之剖視圖，且為沿著圖1之A-A線之剖視圖。
圖3係將圖2中之虛線部放大所得之剖視圖。
圖4係表示實施形態之半導體裝置之剖視圖，且為沿著圖1之B-B線之剖視圖。
圖5係將圖4中之虛線部放大所得之剖視圖。
圖6係表示比較例之半導體裝置之俯視圖。
以下，參照圖式對實施形態進行說明。於圖式中對相同部分標註相同之參照符號。
<實施形態>
以下，利用圖1至圖5對實施形態之半導體裝置進行說明。
於本實施形態中，於再配線層380內設置有例如同一電源電壓用 或同一接地電壓用之2條配線330a、330b(或330c、330d)。針對該等配線330a、330b(或330c、330d)，於封裝基板100側設置有1個凸塊110a(或凸塊110b)，於介面側200設置有2個凸塊210a、210b(或於積層核心晶片300側設置有2個通孔360c、360d)。藉此，可減少較大尺寸之凸塊110之數量，從而可獲得減短再配線層380內之配線330等效果。以下，對實施形態詳細地進行說明。
[實施形態中之構成]
利用圖1至圖5對實施形態之半導體裝置之構成進行說明。
圖1係表示實施形態之半導體裝置之俯視圖。
如圖1所示，實施形態之半導體裝置包括封裝基板100、介面晶片200、及積層核心晶片300。
封裝基板100安裝介面晶片200及積層核心晶片300。封裝基板100與外部連接，自外部對封裝基板100供給電源電壓VCC或接地電壓VSS。封裝基板100將來自外部之電源電壓VCC或接地電壓VSS直接供給至積層核心晶片300。封裝基板100將電源電壓VCC或接地電壓VSS供給至介面晶片200。或者，封裝基板100將電源電壓VCC或接地電壓VSS經由介面晶片200供給至積層核心晶片300。再者，於經由介面晶片200之情形時，封裝基板100並非僅供給電壓，亦將來自外部之信號(資料信號及指令信號等)IO供給至核心晶片300。
積層核心晶片300包含例如NAND(Not AND，反及)快閃記憶體等記憶體電路、及記憶體控制器。積層核心晶片300記憶來自外部之資料等。
介面晶片200包含介面電路。介面電路包含邏輯電路、及類比電路等。介面晶片200於封裝基板100與積層核心晶片300之間傳輸信號IO、電源電壓、及接地電壓。
於俯視下，積層核心晶片300設置於封裝基板100內。又，介面 晶片200設置於積層核心晶片300內之中央部。封裝基板100之尺寸由積層核心晶片300之尺寸決定，並由該等決定封裝尺寸。
於俯視下，於積層核心晶片300之平面尺寸內設置有複數個凸塊110、複數條配線330、及複數個通孔360。又，於介面晶片200內設置有複數個凸塊210。
複數個凸塊110設置於第1方向(圖式左右方向)上之積層核心晶片300之兩端部，於兩端部之各者沿著第2方向(圖式上下方向)排列成例如2行。又，排列於第1行之複數個凸塊110與排列於第2行之複數個凸塊110相互交錯地配置。複數個凸塊110係與封裝基板100電性連接之端子。自外部對各凸塊110供給信號IO、電源電壓VCC、或接地電壓VSS中之任一者。
複數個凸塊210設置於第1方向上之介面晶片200之兩端部，且於兩端部之各者沿著第2方向排列成2行。複數個凸塊210係經由介面晶片200而與積層核心晶片300電性連接之端子。對排列於第1方向之一對凸塊210a、210b供給同一信號IO、同一電源電壓VCC、或同一接地電壓VSS。
複數個通孔360係於介面晶片200外沿著第2方向與複數個凸塊210排列於同行。複數個通孔360係與核心晶片300電性連接之端子。對排列於第1方向之一對通孔360c、360d供給同一電源電壓VDD或同一接地電壓VCC。
配線330將任一凸塊110與一對凸塊210、或者任一凸塊110與一對通孔360連接。
更具體而言，配線330a之一端及配線330b之一端與同一凸塊110a電性連接。又，配線330a之另一端與凸塊210a電性連接，配線330b之另一端與凸塊210b電性連接。藉此，配線330a與配線330b於介面晶片200側(凸塊210a、210b側)具有開口部。凸塊210a與凸塊210b於介面晶 片200內電性連接。又，凸塊210a及凸塊210b亦可經由介面晶片200而與積層核心晶片300電性連接。
又，配線330c之一端及配線330d之一端與同一凸塊110b電性連接。又，配線330c之另一端與通孔360c電性連接，配線330d之另一端與通孔360d電性連接。藉此，配線330c與配線330d於積層核心晶片300側(通孔360c、360d側)具有開口部。通孔360c與通孔360d於積層核心晶片300內電性連接。
又，信號IO用之複數個凸塊110與複數個凸塊210之間分別具有不同之距離。該等全部由同一長度之配線330電性連接。因此，於距離較短之凸塊110與凸塊210之間之一部分設置有冗餘配線部分。此處，所謂冗餘配線部分係指配線330中於凸塊110與凸塊210之間多餘地加長之部分，實際上具有傳輸信號IO之功能。
再者，藉由2條(一對)配線330將凸塊110與凸塊210或通孔360連接，但亦可利用3條以上之配線連接。於該情形時，配線330之數量與凸塊210或通孔360之數量相同。又，於圖1中，作為信號IO用而使用有1條配線330，但亦可與電源電壓用及接地電壓用同樣地使用2條(一對)配線330。
圖2係表示實施形態之半導體裝置之剖視圖，且為沿著圖1之A-A線之剖視圖。
如圖2所示，於A-A線剖面中，於封裝基板(半導體基板)100之下表面上設置有凸塊120。於半導體裝置為BGA(Ball Grid Array，球狀柵格陣列)封裝之情形時，凸塊120為焊球。封裝基板100經由凸塊120而與外部電性連接。
於封裝基板100之上表面上設置有介面晶片(半導體晶片)200。
於介面晶片200及封裝基板100之上表面之上方設置有積層核心晶片300。積層核心晶片300包含複數個核心晶片(半導體晶片)300a- 300h。複數個核心晶片300a-300h自下方側依次積層。於除最上層之核心晶片300h以外之各核心晶片300a-300g設置有自其上表面到達至下表面之TSV(貫通電極)310。而且，於各TSV310間設置有凸塊320。
於最下層之核心晶片300a之下表面上設置有配線330。於該配線330與介面晶片200之間設置有凸塊210。另一方面，於配線330與封裝基板100之間設置有凸塊110。配線330與介面晶片200之間之距離小於配線330與封裝基板100之距離。因此，凸塊210之尺寸(例如平面尺寸)小於凸塊110之尺寸。
以下，利用圖3對封裝基板100、介面晶片200、及核心晶片300之更詳細之連接剖面進行說明。
圖3係將圖2中之虛線部放大所得之剖視圖。再者，於圖3中，為了便於說明而表示配置於不同之剖面之凸塊110a、及凸塊210a、210b、210c。
如圖3所示，於封裝基板100之上表面上設置有絕緣層120。於該絕緣層120上設置有介面晶片200。因此，封裝基板100之上表面與介面200之下表面之間被絕緣分離。又，於封裝基板100之上表面上設置有電極墊130。
於介面200之上表面上設置有電極墊220、240及絕緣層230。
於最下層之核心晶片300a之下表面上設置有絕緣層350，於該絕緣層350之下表面上設置有再配線層380。再配線層380包含配線330(配線330a、330b、330c)及絕緣層340。絕緣層340包含例如樹脂。
於配線330a、330b與電極墊130之間設置有凸塊110a。又，於配線330a與電極墊220之間設置有凸塊210a，於配線330b與電極墊220之間設置有凸塊210b。
即，封裝基板100與介面晶片200經由電極墊130、凸塊110a、配線330a、凸塊210a、及電極墊220而電性連接，並且經由電極墊130、 凸塊110a、配線330b、凸塊210b、及電極墊220而電性連接。
又，電極墊220經由介面晶片200內而與電極墊240電性連接。於配線330e與電極墊240之間設置有凸塊210e。即，電極墊220進而經由介面晶片200、電極墊240、凸塊210e、及配線330e而與核心晶片300a(積層核心晶片300)電性連接。
圖4係表示實施形態之半導體裝置之剖視圖，且為沿著圖1之B-B線之剖視圖。
如圖4所示，於B-B線剖面中，不同於A-A線剖面，而未於封裝基板100之上表面上設置介面晶片200及凸塊210。又，配線330之一部分未經由介面晶片200而與核心晶片300a電性連接。
以下，利用圖5對封裝基板100及核心晶片300之更詳細之連接剖面進行說明。
圖5係將圖4中之虛線部放大所得之剖視圖。再者，於圖5中，為了便於說明而表示配置於不同之剖面之凸塊110b、及通孔360c、360d。
如圖5所示，於封裝基板100之上表面上設置絕緣層120及電極墊140。
於最下層之核心晶片300a之下表面上設置電極墊370。電極墊370與核心晶片300a內之TSV310電性連接。以覆蓋電極墊370之方式設置絕緣層350，於該絕緣層350之下表面上設置再配線層380。再配線層380包含配線330(配線330c、330d)與絕緣層340。
於配線330c、330d與電極墊140之間設置凸塊110b。又，於絕緣層350內且於配線330c與電極墊370之間設置通孔360c，於絕緣層350內且於配線330d與電極墊370之間設置通孔360d。此處，通孔360之尺寸(例如平面尺寸)小於凸塊110之尺寸。
即，封裝基板100與核心晶片300a(積層核心晶片300)經由電極墊 140、凸塊110b、配線330c、通孔360c、及電極墊370而電性連接，並且經由電極墊140、凸塊110b、配線330d、通孔360d、及電極墊370而電性連接。
[實施形態之效果]
根據本實施形態，於再配線層380內設置有例如同一電源電壓用或同一接地電壓用之2條配線330a、330b。配線330a、330b對介面晶片200供給電源電壓VCC或接地電壓VSS。相對於該等配線330a、330b，於封裝基板100側設置有1個端子(凸塊110a)，且於介面晶片200側設置有2個端子(凸塊210a、210b)。而且，配線330a、330b之一端共通地連接於凸塊110a，另一方面，配線330a、330b之另一端分別連接於凸塊210a、210b之各者。藉此，藉由增加介面晶片200側之凸塊210之數量而設置配線330a、330b之開口部。即，不增加封裝基板100側之較大尺寸之凸塊110之數量而設置配線330a、330b。
根據上述構造，可相對於圖6所示之比較例而減少較大尺寸之凸塊110之數量。藉此，可縮小積層核心晶片300及封裝基板100之尺寸，從而可謀求封裝尺寸之縮小。
又，藉由減少凸塊110之數量，而位於晶片端之凸塊110與凸塊210之距離與比較例相比變近。其結果，端子間之配線330變短，從而可使配線電阻、電容、及電感降低。
又，可使IO用之複數條配線330中之最長之配線330較比較例短。藉此，可減小IO用之複數條配線間之配線長度之差，從而可削減多餘之冗餘配線部分。
又，藉由減短配線長度或者削減冗餘配線部分而可容易進行配線設計。進而，藉由配線設計之自由度提高，而可容易改善裝置特性。
又，根據本實施形態，於再配線層380內設置有例如同一電源電 壓用或同一接地電壓用之2條配線330c、330d。配線330c、330d對積層核心晶片300供給電源電壓或接地電壓。針對該等配線330c、330d，於封裝基板100側設置有1個端子(凸塊110)，且於積層核心晶片300側設置有2個端子(通孔360c、360d)。而且，配線330c、330d之一端共通地連接於凸塊110，另一方面，配線330c、330d之另一端分別連接於通孔360c、360d之各者。藉此，可獲得與上述相同之效果。
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並未意圖限定發明之範圍。該等新穎之實施形態能以其他多種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
100‧‧‧封裝基板
110a‧‧‧凸塊
110b‧‧‧凸塊
200‧‧‧介面晶片
210‧‧‧凸塊
210a‧‧‧凸塊
210b‧‧‧凸塊
300‧‧‧積層核心晶片
330‧‧‧配線
330a‧‧‧配線
330b‧‧‧配線
330c‧‧‧配線
330d‧‧‧配線
360‧‧‧通孔
360c‧‧‧通孔
360d‧‧‧通孔
IO‧‧‧信號
VCC‧‧‧電源電壓
VSS‧‧‧接地電壓

Claims (15)

  1. 一種半導體裝置，其具備：第1半導體晶片；第1配線及第2配線，其等設置於上述第1半導體晶片之第1面之上方；第1端子，其與上述第1配線之一端及上述第2配線之一端連接，且與外部連接；第2端子，其與上述第1配線之另一端連接；及第3端子，其與上述第2配線之另一端連接，且與上述第2端子連接；上述第2端子及上述第3端子係與上述第1半導體晶片之內部連接，上述第2端子係設置於上述第1配線與上述第1半導體晶片之間之第1通孔，上述第3端子係設置於上述第2配線與上述第1半導體晶片之間之第2通孔。
  2. 如請求項1之半導體裝置，其中上述第1端子之尺寸大於上述第2端子及上述第3端子之尺寸。
  3. 如請求項1之半導體裝置，其進而具備第1電極墊，該第1電極墊設置於上述第1半導體晶片與上述第1通孔及上述第2通孔之間，且將上述第1通孔與上述第2通孔連接。
  4. 如請求項1之半導體裝置，其進而具備基板，上述基板之第1面經由第1凸塊與外部連接，上述基板之第2面與上述第1半導體晶片之上述第1面對向，上述第1端子係設置於上述第1配線及上述第2配線與上述基板 之間之第2凸塊。
  5. 如請求項1之半導體裝置，其中上述第1半導體晶片包含記憶資料之記憶體電路。
  6. 一種半導體裝置，其具備：第1半導體晶片；第1配線及第2配線，其等設置於上述第1半導體晶片之第1面之上方；第1端子，其與上述第1配線之一端及上述第2配線之一端連接，且與外部連接；第2端子，其與上述第1配線之另一端連接；第3端子，其與上述第2配線之另一端連接，且與上述第2端子連接；基板，其具有經由第1凸塊與外部連接之第1面及與上述第1半導體晶片之上述第1面對向之第2面；及第2半導體晶片，其設置於上述基板與上述第1半導體晶片之間且於上述基板之上述第2面上，上述第1端子係設置於上述第1配線及上述第2配線與上述基板之間之第2凸塊，上述第2端子係設置於上述第1配線與上述第2半導體晶片之間之第3凸塊，上述第3端子係設置於上述第2配線與上述第2半導體晶片之間之第4凸塊。
  7. 如請求項6之半導體裝置，其進而具備第2電極墊，該第2電極墊設置於上述第2半導體晶片與上述第3凸塊及上述第4凸塊之間，且將上述第3凸塊與上述第4凸塊連接。
  8. 如請求項7之半導體裝置，其中上述第2電極墊經由上述第2半導 體晶片而連接於上述第1半導體晶片。
  9. 如請求項6之半導體裝置，其中上述第2半導體晶片包含：於上述基板與上述第1半導體晶片之間傳輸信號及電壓之介面電路。
  10. 一種半導體裝置，其具備：第1半導體晶片；第1配線及第2配線，其等設置於上述第1半導體晶片之第1面之上方；第1端子，其與上述第1配線之一端及上述第2配線之一端連接，且與外部連接；第2端子，其與上述第1配線之另一端連接；第3端子，其與上述第2配線之另一端連接，且與上述第2端子連接；第2半導體晶片，其設置於上述第1半導體晶片之第2面之上方；第1凸塊，其設置於上述第1半導體晶片與上述第2半導體晶片之間；及第1電極，其自上述第1半導體晶片之上表面到達至下表面；上述第1半導體晶片與上述第2半導體晶片係經由上述第1電極及上述第1凸塊而連接。
  11. 如請求項10之半導體裝置，其進而具備：第3半導體晶片，其設置於上述第2半導體晶片之上方；第2凸塊，其設置於上述第2半導體晶片與上述第3半導體晶片之間；及第2電極，其自上述第2半導體晶片之上表面到達至下表面；上述第1半導體晶片、上述第2半導體晶片、及上述第3半導體晶片係經由上述第1電極、上述第1凸塊、上述第2電極及上述第 2凸塊而連接。
  12. 如請求項11之半導體裝置，其中上述第1半導體晶片、上述第2半導體晶片、及上述第3半導體晶片包含記憶資料之記憶體電路。
  13. 如請求項11之半導體裝置，其進而具備基板，上述基板之第1面經由第3凸塊而與外部連接，上述基板之第2面與上述第1半導體晶片之上述第1面對向，上述第1端子係設置於上述第1配線及上述第2配線與上述基板之間之第4凸塊。
  14. 如請求項13之半導體裝置，其進而具備第4半導體晶片，該第4半導體晶片設置於上述基板與上述第1半導體晶片之間、且於上述基板之上述第2面上，上述第2端子及上述第3端子係與上述第4半導體晶片之內部連接，上述第2端子係設置於上述第1配線與上述第4半導體晶片之間之第5凸塊，上述第3端子係設置於上述第2配線與上述第4半導體晶片之間之第6凸塊。
  15. 如請求項14之半導體裝置，其中上述第4半導體晶片包含：於上述基板與上述第1半導體晶片、上述第2半導體晶片、及上述第3半導體晶片之間傳輸信號及電壓之介面電路。
TW104141792A 2015-04-28 2015-12-11 半導體裝置 TWI607543B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562153925P 2015-04-28 2015-04-28
US14/844,602 US9589946B2 (en) 2015-04-28 2015-09-03 Chip with a bump connected to a plurality of wirings

Publications (2)

Publication Number Publication Date
TW201639107A TW201639107A (zh) 2016-11-01
TWI607543B true TWI607543B (zh) 2017-12-01

Family

ID=57205182

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104141792A TWI607543B (zh) 2015-04-28 2015-12-11 半導體裝置

Country Status (3)

Country Link
US (1) US9589946B2 (zh)
CN (2) CN106098659B (zh)
TW (1) TWI607543B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6759874B2 (ja) * 2016-09-01 2020-09-23 富士電機株式会社 電力変換装置
JP6800788B2 (ja) * 2017-03-15 2020-12-16 キオクシア株式会社 半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
CN1947247A (zh) * 2004-04-30 2007-04-11 爱特梅尔股份有限公司 通用互连芯片
KR100750764B1 (ko) * 2003-01-29 2007-08-20 샤프 가부시키가이샤 반도체 장치
US7608925B2 (en) * 2005-07-20 2009-10-27 Fujitsu Microelectronics Limited Relay board with bonding pads connected by wirings

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4746770B2 (ja) 2001-06-19 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置
JP4068838B2 (ja) * 2001-12-07 2008-03-26 株式会社日立製作所 半導体装置の製造方法
JP2004031790A (ja) * 2002-06-27 2004-01-29 Hitachi Maxell Ltd 半導体チップ
JP2004064016A (ja) * 2002-07-31 2004-02-26 Hitachi Maxell Ltd 半導体チップ
TW200504895A (en) * 2003-06-04 2005-02-01 Renesas Tech Corp Semiconductor device
JP2005340741A (ja) * 2004-05-31 2005-12-08 Renesas Technology Corp 半導体装置
US7342312B2 (en) 2004-09-29 2008-03-11 Rohm Co., Ltd. Semiconductor device
JP4890827B2 (ja) 2004-09-29 2012-03-07 ローム株式会社 半導体装置
JP4268607B2 (ja) * 2005-09-30 2009-05-27 富士通マイクロエレクトロニクス株式会社 半導体装置に配設される中継部材及び半導体装置
JP4595823B2 (ja) * 2006-01-24 2010-12-08 株式会社デンソー ボールグリッドアレイ
US7659612B2 (en) * 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
JP2008166408A (ja) * 2006-12-27 2008-07-17 Toshiba Corp 回路板及び回路板の製造方法、並びに回路板を備えた電子機器
JP2009170561A (ja) * 2008-01-15 2009-07-30 Panasonic Corp 配線基板およびその製造方法
IT1391239B1 (it) * 2008-08-08 2011-12-01 Milano Politecnico Metodo per la formazione di bump in substrati con through via
JP5405785B2 (ja) * 2008-09-19 2014-02-05 ルネサスエレクトロニクス株式会社 半導体装置
JP5355499B2 (ja) 2010-06-03 2013-11-27 株式会社東芝 半導体装置
JP2011258867A (ja) * 2010-06-11 2011-12-22 Casio Comput Co Ltd 半導体装置及びその製造方法
JP6114577B2 (ja) * 2013-03-06 2017-04-12 ルネサスエレクトロニクス株式会社 半導体装置
JP2015018897A (ja) * 2013-07-10 2015-01-29 マイクロン テクノロジー， インク． 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
KR100750764B1 (ko) * 2003-01-29 2007-08-20 샤프 가부시키가이샤 반도체 장치
CN1947247A (zh) * 2004-04-30 2007-04-11 爱特梅尔股份有限公司 通用互连芯片
US7608925B2 (en) * 2005-07-20 2009-10-27 Fujitsu Microelectronics Limited Relay board with bonding pads connected by wirings

Also Published As

Publication number Publication date
CN106098659A (zh) 2016-11-09
US9589946B2 (en) 2017-03-07
TW201639107A (zh) 2016-11-01
CN106098659B (zh) 2018-12-14
US20160322341A1 (en) 2016-11-03
CN110010583B (zh) 2023-11-21
CN110010583A (zh) 2019-07-12

Similar Documents

Publication Publication Date Title
US10811387B2 (en) Methods of operating microelectronic devices including a controller
US9136204B2 (en) Semiconductor device having penetrating electrodes each penetrating through substrate
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
US9252091B2 (en) Semiconductor device having penetrating electrodes each penetrating through semiconductor chip
US9362262B2 (en) Semiconductor device
US20130161836A1 (en) Semiconductor package having interposer comprising a plurality of segments
US20180158771A1 (en) Semiconductor device
US10083937B2 (en) Semiconductor devices and packages and methods of forming semiconductor device packages
US9595489B2 (en) Semiconductor package with bonding wires of reduced loop inductance
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
US11315886B2 (en) Semiconductor package having stiffening structure
US20160079219A1 (en) Semiconductor device
US9362263B2 (en) Semiconductor device
US10964669B2 (en) Semiconductor package including stress-equalizing chip
TWI607543B (zh) 半導體裝置
US20220320053A1 (en) Semiconductor package
US20220392833A1 (en) Substrate for noise prevention and semiconductor package including the substrate
US20240047389A1 (en) Semiconductor chip and semiconductor package
US9633980B2 (en) Semiconductor device