TWI766464B - 半導體裝置、半導體裝置封裝、包括上述之電子系統、及相關方法 - Google Patents
半導體裝置、半導體裝置封裝、包括上述之電子系統、及相關方法 Download PDFInfo
- Publication number
- TWI766464B TWI766464B TW109142788A TW109142788A TWI766464B TW I766464 B TWI766464 B TW I766464B TW 109142788 A TW109142788 A TW 109142788A TW 109142788 A TW109142788 A TW 109142788A TW I766464 B TWI766464 B TW I766464B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor die
- substrate
- semiconductor
- die
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 455
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 176
- 239000000463 material Substances 0.000 claims description 85
- 239000008393 encapsulating agent Substances 0.000 claims description 57
- 238000001514 detection method Methods 0.000 claims description 15
- 238000000465 moulding Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 description 12
- 239000004020 conductor Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 239000002861 polymer material Substances 0.000 description 3
- 241000724291 Tobacco streak virus Species 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
半導體裝置及半導體裝置封裝可包括支撐於一基板之一第一側上之至少一個第一半導體晶粒。該至少一個第一半導體晶粒可包括一第一主動表面。一第二半導體晶粒可經支撐於該基板之一第二相對側上。該第二半導體晶粒可包括定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。該第二半導體晶粒可經組態以在操作期間具有高於該至少一個第一半導體晶粒之中值功耗。揭示一種併入一半導體裝置封裝之電子系統及相關方法。
Description
本發明大體上係關於半導體裝置、半導體裝置封裝、包括上述之電子系統及相關方法。更具體而言,所揭示實施例係關於可更好地管理由半導體晶粒產生之熱,可減小裝置及/或封裝大小及特別是裝置及/或封裝高度,且可改良裝置及/或封裝效能之半導體裝置及半導體裝置封裝。
半導體裝置及半導體裝置封裝可包括經組態以產生多於其他半導體晶粒之熱之一些半導體晶粒。例如,經組態為處理器、微處理器、控制器、微控制器、邏輯控制器之半導體晶粒通常產生多於經組態為記憶體裝置之半導體晶粒之熱。
半導體裝置及半導體裝置封裝演變為採用越來越小之形狀因數,此趨勢導致越來越小之可用佔用面積(即,表面積)來容納包括相對高功率(即,高功率密度)半導體晶粒之總成,舉例而言諸如,包括一控制器晶粒及多個記憶體晶粒之半導體裝置或半導體裝置封裝。在包括控制器及記憶體晶粒之當前半導體裝置及半導體裝置封裝組態中,控制器晶粒之高產熱性非期望地增加記憶體晶粒之溫度,此可能導致效能下降且最終導致故障。
分別在圖5至圖8中描繪展現此問題之兩種習知半導體封裝設計。圖5係一第一習知半導體裝置封裝500之一橫截面示意視圖,第一習知半導體裝置封裝500在一基板506上包括位於一記憶體晶粒堆疊504下方之一控制器晶粒502。在此一組態中,控制器晶粒502可經內插於基板506與記憶體晶粒堆疊504之間。圖6係一第二習知半導體裝置封裝600之一橫截面示意視圖,第二習知半導體裝置封裝600在一基板606上包括與一記憶體晶粒堆疊604相鄰之一控制器晶粒602。在此一組態中,控制器晶粒602可在基板606之一主表面上定位成側向相鄰於記憶體晶粒堆疊604。
圖7係繪示控制器晶粒602以一並排組態對記憶體晶粒604進行加熱之一俯視熱圖,圖8係繪示控制器晶粒502以一控制器在頂部組態對記憶體晶粒504進行加熱之一俯視熱圖。共同參考圖7及圖8,由相對較高之功率密度控制器晶粒502或602產生之熱可透過傳導傳遞至記憶體晶粒504或604。因此,控制器晶粒502或602及記憶體晶粒504或604之各者之接面溫度可增加,尤其是在控制器晶粒502或602及記憶體晶粒504或604之靠近彼此(例如,經定位成彼此之間距離最短)之彼等部分中。
此等配置將諸如一控制器晶粒之一高功率密度晶粒放置於一記憶體晶粒堆疊正下方或放置成側向緊鄰一記憶體晶粒堆疊。另外,此等習知裝置及封裝設計之高度或佔用面積可能非期望地大。
在一些實施例中,根據本發明之特定實施例之半導體裝置及半導體裝置封裝可包括支撐於一基板之一第一側上之一第一半導體晶粒。該第一半導體晶粒可包括一第一主動表面。一第二半導體晶粒可經支撐於該基板之一第二相對側上。該第二半導體晶粒可包括定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。該第二半導體晶粒可經組態以在操作期間具有高於該第一半導體晶粒之中值功耗。
根據本發明之其他實施例之半導體裝置封裝可包括支撐於一基板之一第一側上之一第一半導體晶粒堆疊,該堆疊之各第一半導體晶粒包含一第一主動表面。焊線接合可自該堆疊之各第一半導體晶粒延伸至該堆疊之直接下伏第一半導體晶粒或延伸至該基板。一第二半導體晶粒可經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。一囊封劑材料可將該第一半導體晶粒堆疊及該等焊線接合至少部分地囊封於該基板之該第一側上。不同於該囊封劑材料之一模製底膠材料可至少部分地包圍該基板之該第二側上之該第二半導體晶粒。
在其他實施例中,根據本發明之特定實施例之製造半導體裝置及半導體裝置封裝之方法可涉及將包含一第一主動表面之一第一半導體晶粒支撐於一基板之一第一側上。可將一第二半導體晶粒支撐於該基板之一第二相對側上且可將該第二半導體晶粒之一第二主動表面定位於該第二半導體晶粒之面向該基板之一側上。該第二半導體晶粒可經組態以在操作期間具有高於該第一半導體晶粒之中值功耗。
在其他實施例中,根據本發明之電子系統可包括例如一探測單元及一控制單元。該探測單元及該控制單元之至少一者可包括經組態以至少部分地處理或儲存由該探測單元產生之一電信號之一半導體裝置或半導體裝置封裝。該半導體裝置或半導體裝置封裝可包括支撐於一基板之一第一側上之包含一第一主動表面之至少一個第一半導體晶粒。一第二半導體晶粒可經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。該第二半導體晶粒可經組態以在操作期間具有高於該至少一個第一半導體晶粒之中值功耗。
優先權主張
本申請案主張2019年12月17日申請之標題為「Semiconductor Devices, Semiconductor Device Packages, Electronic Systems Including Same, and Related Methods」之美國專利申請案第16/717,827號之優先日期之權益。
本發明中所呈現之圖解並不意在係任何特定半導體裝置、半導體裝置封裝或其組件之實際視圖,而僅僅係用於描述闡釋性實施例之理想化表示。因此,圖式不一定按比例繪製。
所揭示實施例通常係關於可更好地管理由半導體晶粒產生之熱,可減小裝置及/或封裝大小且尤其是裝置及/或封裝高度,且可改良裝置及/或封裝效能。更具體而言,揭示半導體裝置及半導體裝置封裝之實施例,其等可包括在一基板之與一較高產熱第二半導體晶粒相對之一側上之較低產熱第一半導體晶粒,可將第一半導體晶粒及第二半導體晶粒至少部分地包圍於不同保護材料中,且可將第二半導體晶粒定位成更接近將半導體裝置或半導體裝置封裝連接至其他裝置及結構之導電元件。
如本文中所使用,關於一給定參數、性質或條件之術語「實質上」及「約」表示及包括在一般技術者將理解之程度上給定參數、性質或條件在一定程度之差異下予以滿足,諸如在可接受製造容限範圍內予以滿足。例如,實質上或約為一經指定值之一參數可為經指定值之至少約90%、經指定值之至少約95%、經指定值之至少約99%或甚至經指定值之至少約99.9%。
如本文中所使用,相對定位術語,諸如「側向」、「縱向」、「上」、「下」等指代如圖紙上定向之相對定位,且絕不限制一設備或其任何部分之定向,除非很明顯設備之特定方向鑑於重力對於操作而言係必要的或期望的。例如,當參考圖中所繪示之元件時,術語「側向」、「縱向」、「上」及「下」可指代一半導體裝置封裝之元件之一定向,其中彼封裝之一基板水平地定向且導電元件用於將該封裝連接至定位於該封裝之一底部處之其他裝置及結構。
圖1係根據本發明之一第一半導體裝置封裝100之一橫截面示意視圖。第一半導體裝置封裝100可包括例如第一半導體裝置封裝100之其他組件可經支撐於其上之一基板102。基板102可經組態為例如一印刷電路板或一中介層基板且基板核心內之電路系統可用作一重布結構,其包含用於在封裝內部在半導體晶粒之間路由資料、功率及偏壓(例如,接地信號)及在外部與更高級封裝路由資料、功率及偏壓(例如,接地信號)之一或多個重布層(RDL)。
基板102可包括例如一介電材料104及至少部分地延伸穿過介電材料104之電互連件106。介電材料104可包括例如一電及熱絕緣材料,以將至少一些電互連件106彼此電隔離,將支撐基板102上並固定至基板102之組件彼此電隔離,且抑制跨基板102之熱流動。更具體而言,介電材料104可包括例如具有約1 W/mK或更小(例如,在約0.5 W/mK與約0.75 W/mK之間)之一熱導率之一玻璃纖維增強聚合物材料。作為一特定非限制性實例,介電材料104可包括一環氧聚合物材料。
電互連件106可提供自基板102之一第一側上之一第一主表面108至基板102之一第二相對側上之一第二主表面110之一電通道。電互連件106可包括例如藉由介電材料104之層而分離之導電材料之跡線、線、通孔及/或其他佈線構件。電互連件106之導電材料可包括例如銅、金、鋁及包括此等材料之合金之一或多者。
一第一半導體晶粒112可在第一主表面108上或上方支撐於一基板102之一第一側上。在一些實施例中,多於一個第一半導體晶粒112可經支撐於基板102之第一側上,使得第一半導體晶粒112之一堆疊可經支撐於基板102之第一側上。該堆疊中相鄰於基板102之至少最底部第一半導體晶粒112可包括例如定位於第一半導體晶粒112之與基板102相對之一側上之一第一主動表面114及定位於第一半導體晶粒112之靠近基板102之一側上之一第一非主動表面116。更具體而言,該堆疊中之各第一半導體晶粒112可包括定位於第一半導體晶粒112之與基板102相對之一側上之一第一主動表面114及定位於第一半導體晶粒112之靠近基板102之一側上之一第一非主動表面116。
為了促進此組態,該堆疊之各第一半導體晶粒112可例如相對於該堆疊之一直接下伏第一半導體晶粒112側向偏移。更具體而言,其第一主動表面114之一側向周邊處之一下伏第一半導體晶粒112之至少一部分可側向延伸超出一上覆第一半導體晶粒112之一側向側表面118,從而形成一台階形狀,其亦可被稱為瓦堆疊。第一主動表面114之沿著各半導體晶粒112之一周邊邊緣之彼等部分上之接合墊經暴露而側向超出一緊接上覆第一半導體晶粒112,且可同樣地經暴露以對電連接件提供端子。
焊線接合120可自該堆疊之各第一半導體晶粒112延伸至該堆疊之直接下伏第一半導體晶粒112或延伸至基板102。例如,一焊線接合120可自暴露於該堆疊之最底部第一半導體晶粒112之一側向周邊處之一接合墊延伸至呈基板102之第一主表面108處之電互連件106之一端子墊之形式之一經暴露接觸件,且焊線接合120可自暴露於各上覆第一半導體晶粒112之側向周邊處之接合墊延伸,側向超出上覆第一半導體晶粒112之側向側表面118,且縱向向下延伸至暴露於直接下伏第一半導體晶粒112之側向周邊處之一接合墊,此大體上遵循該堆疊之第一半導體晶粒112之台階組態。此一組態可將各焊線接合120之長度維持為通常較短,從而降低在囊封期間使相鄰焊線接合120彼此短接或切斷或移開一給定焊線接合120之風險。在其他實施例中,各第一半導體晶粒112之焊線接合120可直接自彼第一半導體晶粒112之接合墊延伸至基板102。在一些實施例中,焊線接合120可在第一半導體晶粒112之堆疊之一個側向側上定位於該堆疊之第一半導體晶粒112上且連接至該堆疊之第一半導體晶粒112。在其他實施例中,假定第一半導體晶粒112之大小及相對放置暴露於第一主動表面114上之用於連接至在多於一個側向側上之焊線接合120之接合墊,則焊線接合120可在多個側向側上定位於該堆疊之一或多個第一半導體晶粒112上且連接至該堆疊之一或多個第一半導體晶粒112。
在其他實施例中,可採用不同技術來暴露第一半導體晶粒112之第一主動表面114上之接合墊及/或以其他方式將該堆疊中之第一半導體晶粒112彼此連接及/或連接至基板102。例如,該堆疊中之不同第一半導體晶粒112可具有彼此不同之側向佔用面積,且第一半導體晶粒112之間的大小差異可使側向周邊處之第一主動表面114上之接合墊相對於上覆第一半導體晶粒112側向暴露(例如,呈一階梯狀金字塔形)。作為另一實例,可省略焊線接合120,且可利用矽穿孔將該堆疊中之第一半導體晶粒112彼此連接及/或連接至基板102,此可減少(例如,消除)暴露第一半導體晶粒112之第一主動表面114上之接合墊之需要。更具體而言,第一半導體晶粒112之一或多者可呈一覆晶定向,使第一主動表面114定向成面向基板102且利用導電材料(例如,凸塊、球、柱或其他形狀之焊接材料)連接至直接下伏組件(例如,基板102或另一第一半導體晶粒112)。覆晶定向可特別用於該堆疊中之最底部第一半導體晶粒112,使得定位成相鄰於基板102且直接電及機械連接至基板102之第一半導體晶粒112可呈一覆晶定向,其中該堆疊中之其他第一半導體晶粒112亦呈一覆晶定向(利用通孔)或如圖1及圖2中大體上展示般定向。在採用矽穿孔之實施例中,第一半導體晶粒112可具有相同側向佔用面積且可至少實質上彼此側向對準,使得除最遠離基板102之最頂部第一半導體晶粒112外之所有第一半導體晶粒112之第一主動表面114可至少實質上隱藏於緊接下伏第一半導體晶粒112之第一非主動表面116下方且與該第一非主動表面116側向對準。在又其他實施例中,額外半導體晶粒(例如,具有相同或不同於第一半導體晶粒112之操作組態)可舉例而言諸如與第一半導體晶粒112或第一半導體晶粒112之堆疊呈一並排組態支撐於基板102上。
各第一半導體晶粒112之第一主動表面114可包括嵌入於其中或定位於其上之積體電路系統,且各第一半導體晶粒112之第一非主動表面116可缺少此積體電路系統。各第一半導體晶粒112之積體電路系統可以可操作地組態各自第一半導體晶粒112以執行一或若干任務。例如,各第一半導體晶粒112之積體電路系統可以可操作地組態各自第一半導體晶粒112以操作為一記憶體裝置。更具體而言,各第一半導體晶粒112之積體電路系統可以可操作地組態各自第一半導體晶粒112以操作為經組態為一「反及」(NAND)、動態隨機存取記憶體(DRAM)、「反或」(NOR)或3D XPoint記憶體裝置之FLASH記憶體。作為一特定非限制性實例,各第一半導體晶粒112之積體電路系統可以可操作地組態各自第一半導體晶粒112以操作為一受管理NAND (mNAND)、嵌入式多媒體卡(eMMC)或嵌入式多晶片封裝(eMCP)記憶體封裝內之記憶體。如本文中所使用,術語「記憶體」及「記憶體裝置」應被解釋為排除暫態信號。在一些實施例中,各第一半導體晶粒112可至少彼此實質上相同,而額外第一半導體晶粒112增加容量及頻寬。在其他實施例中,一或多個第一半導體晶粒112可不同於一或多個其他第一半導體晶粒112,而額外第一半導體晶粒112具有擴展功能性之不同操作組態。
呈一介電模製化合物之形式之一囊封劑材料122可至少部分地囊封第一半導體晶粒112之堆疊及在基板102之第一側上之焊線接合120。例如,囊封劑材料122可至少實質上側向覆蓋基板102之第一主表面108,且可自第一主表面108縱向延伸至至少該堆疊中之最高第一半導體晶粒112之第一主動表面114之層級,且視情況在連接至該堆疊中在第一主表面108上方之最高第一半導體晶粒112之焊線接合120之最高層級上方。更具體而言,囊封劑材料122可與基板102之側向側表面124側向齊平且可完全地覆蓋否則將為基板102之第一主表面108、焊線接合120以及該堆疊之第一半導體晶粒112之第一主動表面114及側向側表面118之經暴露部分之部分。囊封劑材料122可包括例如一介電聚合物材料。更具體而言,囊封劑材料122可包括具有高於基板102之介電材料104之熱導率之一模製化合物,諸如一環氧樹脂材料。作為一特定非限制性實例,囊封劑材料122可包括具有約1.0 W/mK或更大(例如,在約1 W/mK與約7 W/mK之間)之一熱導率之一環氧樹脂材料。
一第二半導體晶粒126可經支撐於基板102之一第二相對側上。第二半導體晶粒126可包括定位於第二半導體晶粒126之面向基板102之一側上之一第二主動表面128及定位於第二半導體晶粒126之與第一半導體晶粒112相對之一側上之一第二非主動表面130。例如,導電元件132可自第二半導體晶粒126之第二主動表面128上之接合墊延伸至基板102之電互連件106之經對準接觸件,其中第二半導體晶粒126之第二主動表面128經定位成靠近且面向基板102。更具體而言,第二半導體晶粒126可呈一覆晶定向及/或利用直接晶片附接技術經由導電元件132連接且直接固定至基板102。導電元件132可包括例如焊料凸塊、銅柱、焊料加蓋之銅柱或由可選擇性流動之可擴散導電材料組成之其他結構。此等技術可減小自第二半導體晶粒126至第一半導體裝置封裝100之一輸出之電路徑之長度,此可改良第一半導體裝置封裝100可能夠操作之速度並且改良信號品質/保真度。
第二半導體晶粒126之第二主動表面128可包括嵌入於其中或定位於其上之積體電路系統,且第二半導體晶粒126之第二非主動表面130可缺少此積體電路系統。第二半導體晶粒126之積體電路系統可以可操作地組態第二半導體晶粒126以執行與第一半導體晶粒112之操作、控制及信號路由相關之一或若干任務。例如,第二半導體晶粒126之積體電路系統可以可操作地組態第二半導體晶粒126以操作為用於一記憶體裝置之邏輯、一控制器、一邏輯控制器或一微控制器之一或多者。更具體而言,第二半導體晶粒126之積體電路系統可以可操作地組態第二半導體晶粒126以操作為用於先前所論述之記憶體裝置及記憶體封裝之任意者之一控制器。
在一些實施例中,第二半導體晶粒126可組態有以一相對高於第一半導體晶粒112之功率密度操作之電路系統,該組態可在操作期間產生實質上多於第一半導體晶粒112之熱。例如,第二半導體晶粒126可具有高於該堆疊中之第一半導體晶粒112之各者之一功率額定值之一功率額定值。更具體而言,第二半導體晶粒126之第二主動表面128處之積體電路系統通常可汲取(例如,操作可能需要)比通常由第一半導體晶粒112之任意者之第一主動表面114處之積體電路系統汲取(例如,其操作所需)之電功率更多之電功率(例如,第二半導體晶粒126可經組態以具有高於第一半導體晶粒112之一或多者之一平均及/或中值功耗)。作為特定非限制性實例,第二半導體晶粒126可具有高於該堆疊中之所有第一半導體晶粒112之組合功率額定值及/或功率密度之一功率額定值及/或一功率密度(例如,第二半導體晶粒126可占第一半導體裝置封裝100之平均及/或中值總功耗之至少一半)。在其中由第一半導體晶粒112之各者在操作期間產生之熱不同於由第二半導體晶粒126產生之熱之實施例中,基板102可抑制第二半導體晶粒126與第一半導體晶粒112之間的熱流動,此可減小由第二半導體晶粒126產生之熱傳導至第一半導體晶粒112且提高第一半導體晶粒112之溫度之程度。因此,熱可更直接地自第一半導體晶粒112及第二半導體晶粒126之各者朝向第一半導體裝置封裝100之外部流動,第一半導體晶粒112及第二半導體晶粒126之接面溫度更可能保持在所建議極限內,且可減少(例如,消除)壓制該半導體晶粒封裝之效能以保持在所建議操作溫度內之需要。
在一些實施例中,第二半導體晶粒126至少部分地定位於自第二側延伸至基板102中之一凹口134內。例如,凹口134可自基板102之第二側上之基板102之第二主表面110朝向第一側且朝向第一主表面108延伸至基板102中。更具體而言,凹口134可具有大體上匹配待至少部分地定位於其中之第二半導體晶粒126之形狀之幾何形狀且可大於第二半導體晶粒126以促進將第二半導體晶粒126至少部分地定位於其中。又更具體而言,凹口134可經成形為例如一直角多邊形稜鏡,其具有大於第二半導體晶粒126之對應側向尺寸之側向尺寸及如在垂直於第一主表面108及/或第二主表面110之一方向上量測之小於、等於或大於共同部分地或完全地定位於凹口134內之第二半導體晶粒126及導電元件132之對應深度之一深度。作為一特定非限制性實例,凹口134可經成形為一直角矩形稜鏡,其具有在第二半導體晶粒126之對應側向尺寸之約101%與約125%之間的側向尺寸及小於至少部分地定位於凹口134內之第二半導體晶粒126及導電元件132之組合深度(例如,在其約50%與約90%之間)之一深度。因此,與具有等效功能性之習知半導體封裝之高度及佔用面積相比,凹口134藉由容納第二半導體裝置之一組合厚度之至少一部分及導電元件132之高度可允許一更小封裝高度及佔用面積。
在一些實施例中,第一半導體晶粒112之一第一側向佔用面積可大於第二半導體晶粒126之一第二側向佔用面積。例如,如在平行於基板102之第一主表面108及/或第二主表面110之一方向上量測之第一半導體晶粒112之至少一個側向尺寸可大於如在相同方向上量測之第二半導體晶粒126之一對應側向尺寸。更具體而言,各第一半導體晶粒112之第一主動表面114之一第一表面積可大於第二半導體晶粒126之第二主動表面128之一第二表面積。作為一特定非限制性實例,第一半導體晶粒112之各側向尺寸可大於第二半導體晶粒126之對應側向尺寸。在其他實施例中,第一半導體晶粒112之第一側向佔用面積可小於第二半導體晶粒126之第二側向佔用面積。
第一半導體裝置封裝100可包括至少部分地填充凹口134且至少部分地包圍第二半導體晶粒126之另一囊封劑材料136。例如,另一囊封劑材料136可至少完全地填充凹口134,使得另一囊封劑材料136可延伸至與第二主表面110至少縱向齊平且與凹口134之側壁至少側向齊平之一位置。更具體而言,另一囊封劑材料136可至少完全地側向包圍第二半導體晶粒126,使得另一囊封劑材料136可延伸至與第二非主動表面130至少縱向齊平且在各側向側上側向超出第二半導體晶粒126之一位置。作為一特定非限制性實例,另一囊封劑材料136可完全地填充凹口134且完全地包圍第二半導體晶粒126,自凹口134內縱向延伸至超出第二半導體晶粒126之與基板102相對之一側上之第二非主動表面130之一位置,在凹口134之側向侷限向側向延伸,且使包圍凹口134之基板102之第二主表面110至少實質上沒有另一囊封劑材料136。
至少部分地包圍第二半導體晶粒126之另一囊封劑材料136可包括例如不同於至少部分地包圍第一半導體晶粒112之囊封劑材料122之一介電聚合物材料。更具體而言,另一囊封劑材料136可包括具有高於基板102之介電材料104之熱導率之一模製底膠材料或其他模製化合物,諸如一環氧樹脂材料。作為一特定非限制性實例,另一囊封劑材料136可包括具有約1.0 W/mK或更大(例如,在約1 W/mK與約7 W/mK之間)之一熱導率之一模製底膠材料。在一些實施例中,至少部分地包圍第二半導體晶粒126之另一囊封劑材料136之熱導率可等於或大於包圍第一半導體晶粒112之囊封劑材料122之熱導率。在其他實施例中,至少部分地包圍第二半導體晶粒126之另一囊封劑材料136之熱導率可小於包圍第一半導體晶粒112之囊封劑材料122之熱導率。
將第一半導體晶粒112及第二半導體晶粒126放置於基板102之相對側上,將第一半導體晶粒112至少部分地包圍於具有高於基板102 (或至少其介電材料104)之一熱導率之一囊封劑材料122中且將第二半導體晶粒126至少部分地包圍於具有高於基板102之一熱導率之另一囊封劑材料136中可更好地管理來自第一半導體晶粒112及第二半導體晶粒126之熱流動。例如,此一組態可定向對由第一半導體晶粒112產生之熱具有最小抵抗性之遠離基板102並遠離第二半導體晶粒126之一路徑且可定向對由第二半導體晶粒126產生之熱具有最小抵抗性之遠離基板102並遠離第一半導體晶粒112之一路徑。在其中第二半導體晶粒126經組態以產生多於第一半導體晶粒112之熱且其中另一囊封劑材料136具有高於囊封劑材料122之一熱導率之實施例中,第一半導體裝置封裝100之組態亦可更好地促進熱自第一半導體裝置封裝100之最高產熱組件(即,第二半導體晶粒126)遠離第一半導體裝置封裝100且至操作環境之交換。
第一半導體裝置封裝100可包括支撐於基板102之第二主表面110上之導電墊上且自該等導電墊直接延伸之導電元件138。例如,導電元件138可在第二主表面110處自基板102之電互連件106之接觸件延伸縱向遠離第一半導體晶粒112。更具體而言,導電元件138可在第二主表面110處自相關聯電互連件106延伸,且與第二半導體晶粒126之至少一部分縱向重合,縱向遠離第一半導體晶粒112,至與另一囊封劑材料136之最遠離第二主表面110之一部分至少縱向齊平之一位置。作為一特定非限制性實例,導電元件138可自第二主表面110延伸至縱向超出另一囊封劑材料136之一位置,使得另一囊封劑材料136之最遠離第二主表面110之一表面或點可縱向定位於導電元件138之深度之約25%與約75%之間(例如,約50%),如在垂直於第二主表面110之一方向上量測。導電元件138可包括例如凸塊、墊、柱或由可選擇性流動之導電材料(例如,焊料)組成之其他結構。在一項實施例中,導電元件138包含駐留於經組態為凸塊下金屬化層(UBM)或接合墊之導電墊上之焊球。
總之,根據本發明之特定實施例之半導體裝置及半導體裝置封裝可包括支撐於一基板之一第一側上之一第一半導體晶粒。該第一半導體晶粒可包括一第一主動表面。一第二半導體晶粒可經支撐於該基板之一第二相對側上。該第二半導體晶粒可包括定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。該第二半導體晶粒可經組態以在操作期間具有高於該第一半導體晶粒之中值功耗。
根據本發明之其他實施例之半導體裝置封裝可包括支撐於一基板之一第一側上之一第一半導體晶粒堆疊,該堆疊之各第一半導體晶粒包含一第一主動表面。焊線接合可自該堆疊之各第一半導體晶粒延伸至該堆疊之直接下伏第一半導體晶粒或延伸至該基板。一第二半導體晶粒可經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。一囊封劑材料可將該第一半導體晶粒堆疊及該等焊線接合至少部分地囊封於該基板之該第一側上。不同於該囊封劑材料之一模製底膠材料可至少部分地包圍該基板之該第二側上之該第二半導體晶粒。
圖2係根據本發明之一第二半導體裝置封裝200之一橫截面視圖。第二半導體裝置封裝200可至少類似於第一半導體裝置封裝100,其中下文突顯明顯差異。
在第二半導體裝置封裝200中,第二半導體晶粒126可不定位於一凹口134內(參見圖1)。例如,第二半導體晶粒126可在基板102之第二側上直接定位成相鄰於之基板102之第二主表面110。更具體而言,導電元件132可自第二半導體晶粒126之第二主動表面128上之接合墊延伸至呈暴露於基板102之第二主表面110處之電互連件106之端子墊之形式之接觸件,其中第二半導體晶粒126之第二主動表面128經定位成靠近且面向基板102。作為一特定非限制性實例,第二半導體晶粒126可呈一覆晶定向及/或利用直接晶片附接技術經由導電元件132連接且直接固定至基板102之第二主表面110。
基板102可缺少將中斷第一主表面108及第二主表面110之平面性之任何凹口134 (參見圖1)且與第一半導體裝置封裝100之基板102不同,第二半導體封裝200之基板102僅包含呈一扇出封裝(FOP)配置組態之一重布結構,該重布結構包含一或多個RDL,各RDL包含支撐於一介電材料104上之一導電材料106,該導電材料包含延伸超出最低第一半導體晶粒112之側向邊界之跡線及其他導電元件。因此,半導體裝置封裝200之基板102可實質上薄於第一半導體裝置封裝100之基板102。此一組態可減小自第二半導體晶粒126至第一半導體裝置封裝100之一輸出之電路徑之長度,此與具有等效功能性之習知半導體裝置封裝相較可改良第一半導體裝置封裝100可能夠操作之速度並且改良信號品質/保真度。此外,與此等習知封裝相較,可減小封裝高度及佔用面積。
至少部分地包圍第二半導體晶粒126之另一囊封劑材料136可不定位於一凹口134內(參見圖1)且可側向延伸超出此一凹口134之側向侷限之位置(參見圖1)。例如,另一囊封劑材料136可覆蓋基板102之第二主表面110之至少一部分。更具體而言,另一囊封劑材料136可直接定位於基板102之第二主表面110上且與該第二主表面110接觸,且可至少側向包圍第二半導體晶粒126。作為一特定非限制性實例,另一囊封劑材料136可自第二主表面110縱向延伸至比第二半導體晶粒126之第二非主動表面130更遠離第二主表面110之一位置且側向延伸以與基板102之側向側表面124至少實質上齊平。
導電元件138可不直接定位於第二主表面110上,而是可與第二主表面110縱向隔開。例如,第二半導體裝置封裝200可包括自第二主表面110處之電互連件106之接觸件延伸,穿過另一囊封劑材料136,至自另一囊封劑材料136之與基板102相對之一側突出之導電元件138之導電通孔202。通孔202可包括例如柱、支柱、圓柱或由縱向延伸穿過另一囊封劑材料136之導電材料組成之其他結構,且可以「穿模通孔(through-mold-vias)」為特徵。在一項實施例中,導電元件138可包含駐留於經組態為凸塊下金屬化層(UBM)或接合墊之導電墊上之焊球。
圖3係描繪根據本發明之製造一半導體裝置封裝100及/或200之方法300之一流程圖。組合地參考圖1至圖3,可將一第一半導體晶粒112支撐於一基板102之一第一側上,且可將第一半導體晶粒112之一第一主動表面114定位於第一半導體晶粒112之與基板102相對之一側上,如在動作302處所展示。在一些實施例中,多個第一半導體晶粒112可以其等第一主動表面114定向於相同方向上之一堆疊提供,且可藉由例如熱壓接合彼此固定並固定至基板102。自一各自第一半導體晶粒112之第一主動表面114處之接合墊延伸之焊線接合120可經形成為自彼等接合墊延伸至一直接下伏第一半導體晶粒112之接合墊或延伸至基板102之電互連件106之接觸件,此可利用習知焊線接合技術來完成。囊封劑材料122可經定位於第一半導體晶粒112之側向側表面118周圍且在第一半導體晶粒112之第一主動表面114之至少部分(例如,經暴露部分之整體)上方及在基板102之第一主表面108上方,該第一主表面108經定位成側向超出第一半導體晶粒112之側向側表面118 (例如,在所有側向側上)以與基板102之側向側表面124齊平。例如,具有支撐於其上之第一半導體晶粒112及焊線接合120之基板102可經引入至一模具中,且呈一可流動狀態之囊封劑材料122之一前驅體可流入模具內之前述位置。接著,可使前驅體材料固化以形成囊封劑材料122。
可將一第二半導體晶粒126支撐於基板102之一第二相對側上,且可將一第二半導體晶粒126之第二主動表面128放置於第二半導體晶粒126之面向基板102之一側上,如在方法300之動作304處所展示。例如,第二半導體晶粒126可至少部分地放置於自基板102之第二側上之基板102之第二主表面110朝向第一側延伸至基板102中之一凹口134內,如圖1中所展示。作為另一實例,第二半導體晶粒126可經放置成直接相鄰於基板102之第二側上之第二主表面110,如圖2中所展示。
第二半導體晶粒126可經組態以在操作期間產生多於第一半導體晶粒112之熱。例如,當選擇將經定位於基板102之相對側上之半導體晶粒時,可選擇第一半導體晶粒112以操作為記憶體裝置,而可選擇第二半導體晶粒126以操作為一記憶體控制器裝置。
另一囊封劑材料136可經定位成至少部分地包圍基板102之第二相對側上之第二半導體晶粒126。在其中第二半導體晶粒126至少部分地定位於一凹口134內之實施例中,例如,另一囊封劑材料136可至少部分地填充凹口134且至少部分地包圍第二半導體晶粒126。在其中第二半導體晶粒126經定位成直接相鄰於且直接固定至第二半導體晶粒126之第二主表面110之實施例中,另一囊封劑材料136可至少部分地包圍第二半導體晶粒126,可覆蓋第二主表面110之至少一部分,且可與第二主表面110直接接觸。另一囊封劑材料136之放置可利用類似或至少實質上相同於結合囊封劑材料122所描述之彼等程序之程序來進行。
接著,可將導電元件138放置成與第一半導體晶粒112及第二半導體晶粒126電連通。例如,在其中第二半導體晶粒126至少部分地定位於凹口134內之彼等實施例中,導電元件138可直接放置於暴露於基板102之第二主表面110處之電互連件106之接觸件上且固定至該接觸件。作為另一實例,在其中第二半導體晶粒126直接定位於基板102之第二主表面110上且直接固定至該第二主表面110 (經由其自身導電元件132)之彼等實施例中,可形成自第二主表面110處之電互連件106之接觸件延伸穿過另一囊封材料136且至另一囊封劑材料136之與基板102相對之一縱向側之通孔202。接著,可將導電元件138放置成與通孔202直接接觸且固定至通孔202。可例如藉由移除上覆於電互連件106之接觸件之另一囊封劑材料136之部分且用導電材料填充剩餘空隙來形成導電通孔202。作為另一實例,可藉由將支柱、柱、柱子或由導電材料組成之其他結構放置於第二主表面110處之電互連件106之接觸件上來形成通孔202,且可使另一囊封劑材料136在通孔202周圍側向流動並固化。可藉由平面化另一囊封劑材料136及該通孔之導電材料或藉由控制另一囊封劑材料136之放置深度來縱向暴露通孔202。
換言之,根據本發明之特定實施例之製造半導體裝置及半導體裝置封裝之方法可涉及將包含一第一主動表面之一第一半導體晶粒支撐於一基板之一第一側上。可將一第二半導體晶粒支撐於該基板之一第二相對側上且可將該第二半導體晶粒之一第二主動表面定位於該第二半導體晶粒之面向該基板之一側上。該第二半導體晶粒可經組態以在操作期間具有高於該第一半導體晶粒之中值功耗。
圖4係包括圖1或圖2之半導體裝置封裝100或200之一電子系統400之一示意圖。例如,電子系統400可包括一控制單元402及一探測單元404。探測單元404可包括經組態以產生代表且回應於一經偵測到之物理現象之一電信號之一感測器裝置406。探測單元404可為一可擕式裝置,舉例而言例如,一手持式裝置。在一些實施例中,探測單元404可包括根據本發明之定位於探測單元404內之一半導體裝置封裝100或200 (參見圖1、2),該半導體裝置封裝100或200經組態以至少部分地處理電信號或將電信號本端地儲存於探測單元404內。探測單元404可以可操作地連接至控制單元402 (例如,透過一有線或無線連接)且可將原始、部分經處理或完全經處理之電信號發送至控制單元402。在一些實施例中,控制單元402可包括根據本發明之另一半導體裝置封裝100或200 (參見圖1、2)或一微處理器408,該微處理器408可儲存、處理或進一步處理電信號。控制單元404可包括經組態以儲存完全經處理之電信號之結果之一記憶體裝置410 (即,並非暫態信號之一實體、硬體記憶體裝置),其亦可經組態為或包括根據本發明之一半導體裝置封裝100或200 (參見圖1、2)。控制單元402可視情況包括經組態以輸出完全經處理之電信號之結果之一輸出裝置412 (例如,一電子顯示器、一音訊揚聲器、一列印機等)。
總之,根據本發明之電子系統可包括例如一探測單元及一控制單元。該探測單元及該控制單元之至少一者可包括經組態以至少部分地處理或儲存由該探測單元產生之一電信號之一半導體裝置或半導體裝置封裝。該半導體裝置或半導體裝置封裝可包括支撐於基板之一第一側上之包含一第一主動表面之至少一個第一半導體晶粒。一第二半導體晶粒可經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面。該第二半導體晶粒可經組態以在操作期間具有高於該至少一個第一半導體晶粒之中值功耗。
在藉由本申請案中先前論述之組態及方法解決之其他問題當中,根據本發明之半導體裝置及半導體裝置封裝可更好地解決與熱管理、操作速度及信號品質相關之問題。例如,藉由將半導體晶粒放置於內插於半導體晶粒之間的一基板之相對側上,基板之熱絕緣材料可重定向對來自半導體晶粒之熱具有最小抵抗性之遠離彼此且離開半導體裝置或半導體裝置封裝之路徑。作為另一實例,藉由縮短自半導體晶粒之至少一者及可能自該裝置或封裝中之所有半導體晶粒至輸出導電元件之電通道之長度,可改良由彼等電通道攜帶之電信號之品質及該電信號可行進之速度。
雖然已結合附圖描述特定闡釋性實施例,但一般技術者將認知及明白,本發明之範疇不限於本發明中明確地展示及描述之彼等實施例。相反,可對本發明中所描述之實施例進行諸多添加、刪除及修改以產生在本發明之範疇內之實施例,諸如特殊主張之彼等實施例,包括合法等效物。另外,來自一項所揭示實施例之特徵可與另一所揭示實施例之特徵組合,同時仍在本發明之範疇內,如本發明人所考量。
100:第一半導體裝置封裝
102:基板
104:介電材料
106:電互連件
108:第一主表面
110:第二主表面
112:第一半導體晶粒
114:第一主動表面
116:第一非主動表面
118:側向側表面
120:焊線接合
122:囊封劑材料
124:側向側表面
126:第二半導體晶粒
128:第二主動表面
130:第二非主動表面
132:導電元件
134:凹口
136:囊封劑材料
138:導電元件
200:第二半導體裝置封裝
202:導電通孔
300:方法
302:動作
304:動作
400:電子系統
402:控制單元
404:探測單元
406:感測器裝置
408:微處理器
410:記憶體裝置
412:輸出裝置
500:第一習知半導體裝置封裝
502:控制器晶粒
504:記憶體晶粒堆疊或記憶體晶粒
506:基板
600:第二習知半導體裝置封裝
602:控制器晶粒
604:記憶體晶粒堆疊
606:基板
雖然本發明以特別指出且明確主張特定實施例之發明申請專利範圍作為結尾,但當結合隨附圖式閱讀時,根據以下描述可更容易地確認在本發明之範疇內之實施例之各種特徵及優點,在隨附圖式中:
圖1係根據本發明之一第一半導體裝置封裝100之一橫截面示意視圖;
圖2係根據本發明之一第二半導體裝置封裝200之一橫截面示意視圖;
圖3係描繪根據本發明之製造一半導體裝置封裝之一方法之一流程圖;
圖4係根據本發明之一實施例之併入一半導體裝置封裝之一電子系統之一示意圖;
圖5係在一基板上包括位於一記憶體晶粒堆疊下方之一控制器晶粒之一第一習知半導體裝置封裝之一橫截面示意視圖;
圖6係在一基板上包括與一記憶體晶粒堆疊相鄰之一控制器晶粒之一第二習知半導體裝置封裝設計之一橫截面示意視圖;
圖7係繪示控制器晶粒對記憶體晶粒之加熱之一俯視熱圖;及
圖8係繪示控制器晶粒對記憶體晶粒之加熱之一俯視熱圖。
100:第一半導體裝置封裝
102:基板
104:介電材料
106:電互連件
108:第一主表面
110:第二主表面
112:第一半導體晶粒
114:第一主動表面
116:第一非主動表面
118:側向側表面
120:焊線接合
122:囊封劑材料
124:側向側表面
126:第二半導體晶粒
128:第二主動表面
130:第二非主動表面
132:導電元件
134:凹口
136:囊封劑材料
138:導電元件
Claims (26)
- 一種半導體裝置,其包含:至少一個第一半導體晶粒,其經支撐於一基板之一第一側上,該至少一個第一半導體晶粒包含一第一主動表面;一第二半導體晶粒,其經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面;其中該第二半導體晶粒經組態以在操作期間具有高於該至少一個第一半導體晶粒之中值功耗(median power consumption);及導電元件,其在該第二相對側上連接至該基板,該等導電元件經組態以將該半導體裝置連接至更高級(higher-level)封裝。
- 如請求項1之半導體裝置,其中該第二半導體晶粒至少部分地定位於自該基板之該第二相對側上之該基板之一主表面朝向該第一側延伸至該基板中之一凹口內。
- 如請求項2之半導體裝置,其進一步包含一模製底膠材料,該模製底膠材料至少部分地填充該凹口且至少部分地包圍該第二半導體晶粒。
- 如請求項3之半導體裝置,其中該模製底膠材料至少實質上側向侷限於該凹口,使得該基板之該主表面至少實質上沒有該模製底膠材料。
- 如請求項2之半導體裝置,其中該等導電元件係經支撐於該基板之該主表面上且直接自該基板之該主表面延伸。
- 如請求項1之半導體裝置,其中該第二半導體晶粒直接相鄰於該基板之該第二側上之該基板之一主表面。
- 如請求項6之半導體裝置,其進一步包含一模製底膠材料,該模製底膠材料至少部分地包圍該第二半導體晶粒且覆蓋該基板之該主表面之至少一部分。
- 如請求項7之半導體裝置,其進一步包含導電通孔,該等導電通孔自該主表面延伸穿過該模製底膠材料至該模製底膠材料之與該基板相對之一側上之該等導電元件。
- 如請求項6之半導體裝置,其中該基板包含至少一個重布層。
- 如請求項1至9中任一項之半導體裝置,其中該至少一個第一半導體晶粒包含一記憶體裝置且其中該第二半導體晶粒包含一記憶體控制器裝置。
- 如請求項1至9中任一項之半導體裝置,其中該至少一個第一半導體晶粒包含支撐於該基板之該第一側上之一第一半導體晶粒堆疊,各第一半導體晶粒包含定位於各自第一半導體晶粒之與該基板相對之該側上之一第 一主動表面。
- 如請求項11之半導體裝置,其中該第一半導體晶粒堆疊之第一半導體晶粒在一共同方向上與下一較低第一半導體晶粒彼此側向偏移,且該堆疊之第一半導體晶粒藉由焊線接合彼此電連接且連接至該基板。
- 如請求項12之半導體裝置,其中該第一半導體晶粒包含記憶體晶粒且該第二半導體晶粒包含一控制器。
- 如請求項1至9中任一項之半導體裝置,其中當以一俯視視角檢視時該至少一個第一半導體晶粒之一第一佔用面積(footprint)大於當以該俯視視角檢視時該第二半導體晶粒之一第二佔用面積。
- 一種半導體裝置封裝,其包含:一第一半導體晶粒堆疊,其經支撐於一基板之一第一側上,該堆疊之各第一半導體晶粒包含一第一主動表面;焊線接合,其等自該堆疊之各第一半導體晶粒延伸至該堆疊之直接下伏的第一半導體晶粒或延伸至該基板;一第二半導體晶粒,其經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面;一囊封劑材料,其將該第一半導體晶粒堆疊及該等焊線接合至少部分地囊封於該基板之該第一側上; 一模製底膠材料,其不同於該囊封劑材料,該模製底膠材料至少部分地包圍該基板之該第二側上之該第二半導體晶粒;及導電元件,其在該第二相對側上連接至該基板,該等導電元件經組態以將該半導體裝置連接至更高級封裝。
- 如請求項15之半導體裝置封裝,其中該等焊線接合僅在該第一半導體晶粒堆疊之一個側向側上連接至該堆疊之該等第一半導體晶粒。
- 如請求項15或請求項16之半導體裝置封裝,其中該第二半導體晶粒呈一直接晶片附接組態電連接至該基板。
- 如請求項17之半導體裝置封裝,其中該第二半導體晶粒至少部分地接納於該基板之該第二相對側中之一凹口中。
- 如請求項16之半導體裝置封裝,其中該堆疊之該第一半導體晶粒包含NAND或DRAM記憶體裝置且該第二半導體晶粒包含一控制器裝置。
- 一種製造一半導體裝置之方法,其包含:將包含一第一主動表面之一第一半導體晶粒支撐於一基板之一第一側上;將一第二半導體晶粒支撐於該基板之一第二相對側上且將該第二半導體晶粒之一第二主動表面定位於該第二半導體晶粒之面向該基板之一側上,該第二半導體晶粒經組態以在操作期間具有高於該第一半導體晶粒之 中值功耗;及將導電元件在該第二相對側上連接至該基板,該等導電元件經組態以將該半導體裝置連接至更高級封裝。
- 如請求項20之方法,其中將該第二半導體晶粒支撐於該基板之該第二相對側上包含:將該第二半導體晶粒至少部分地放置於自該基板之該第二側上之該基板之一主表面朝向該第一側延伸至該基板中之一凹口內。
- 如請求項21之方法,其進一步包含:用一模製底膠材料至少部分地填充該凹口;及用該模製底膠材料至少部分地包圍該第二半導體晶粒。
- 如請求項20之方法,其中將該第二半導體晶粒支撐於該基板之該第二相對側上包含:將該第二半導體晶粒放置成直接相鄰於該基板之該第二側上之該基板之一主表面。
- 如請求項23之方法,其進一步包含:用一模製底膠材料至少部分地包圍該第二半導體晶粒;及用該模製底膠材料覆蓋該基板之該主表面之至少一部分。
- 如請求項24之方法,其進一步包含:形成自該主表面延伸穿過該模製底膠材料之導電通孔;及將與該等導電通孔接觸之導電元件放置於該模製底膠材料之與該基板相對之一側上。
- 一種電子系統,其包含:一探測單元;及一控制單元;該探測單元及該控制單元之至少一者包含經組態以至少部分地處理或儲存由該探測單元產生之一電信號之一半導體裝置,該半導體裝置包含:至少一個第一半導體晶粒,其經支撐於一基板之一第一側上,該至少一個第一半導體晶粒包含一第一主動表面;一第二半導體晶粒,其經支撐於該基板之一第二相對側上,該第二半導體晶粒包含定位於該第二半導體晶粒之面向該基板之一側上之一第二主動表面;其中該第二半導體晶粒經組態以在操作期間具有高於該至少一個第一半導體晶粒之中值功耗;及導電元件,其在該第二相對側上連接至該基板,該等導電元件經組態以將該半導體裝置連接至更高級封裝。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/717,827 US11587918B2 (en) | 2019-12-17 | 2019-12-17 | Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods |
US16/717,827 | 2019-12-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202143437A TW202143437A (zh) | 2021-11-16 |
TWI766464B true TWI766464B (zh) | 2022-06-01 |
Family
ID=76317005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109142788A TWI766464B (zh) | 2019-12-17 | 2020-12-04 | 半導體裝置、半導體裝置封裝、包括上述之電子系統、及相關方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US11587918B2 (zh) |
KR (1) | KR20210078415A (zh) |
CN (1) | CN112992801A (zh) |
TW (1) | TWI766464B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9627367B2 (en) * | 2014-11-21 | 2017-04-18 | Micron Technology, Inc. | Memory devices with controllers under memory packages and associated systems and methods |
US11587918B2 (en) * | 2019-12-17 | 2023-02-21 | Micron Technology, Inc. | Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods |
KR20220006807A (ko) * | 2020-07-09 | 2022-01-18 | 에스케이하이닉스 주식회사 | 적층 반도체 칩을 포함하는 반도체 패키지 |
US20230051863A1 (en) * | 2021-08-10 | 2023-02-16 | Micron Technology, Inc. | Memory device for wafer-on-wafer formed memory and logic |
US11942459B2 (en) * | 2022-02-14 | 2024-03-26 | Western Digital Technologies, Inc. | Semiconductor device package with exposed bond wires |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200913208A (en) * | 2007-06-11 | 2009-03-16 | Vertical Circuits Inc | Electrically interconnected stacked die assemblies |
US8298940B2 (en) * | 2005-06-30 | 2012-10-30 | Elpida Memory, Inc. | Semiconductor memory device and manufacturing method thereof |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100266071B1 (ko) | 1997-07-03 | 2000-09-15 | 윤종용 | 칩 온 보드 패키지용 인쇄회로기판 및 그를 이용한 칩 온 보드 패키지 |
US7872871B2 (en) | 2000-01-06 | 2011-01-18 | Super Talent Electronics, Inc. | Molding methods to manufacture single-chip chip-on-board USB device |
SG95637A1 (en) | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
KR100415279B1 (ko) | 2001-06-26 | 2004-01-16 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조 방법 |
US6639309B2 (en) | 2002-03-28 | 2003-10-28 | Sandisk Corporation | Memory package with a controller on one side of a printed circuit board and memory on another side of the circuit board |
JP2005175423A (ja) * | 2003-11-18 | 2005-06-30 | Denso Corp | 半導体パッケージ |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TW200843077A (en) | 2007-04-27 | 2008-11-01 | En-Min Jow | Package structure of memory |
KR20120089962A (ko) | 2010-12-31 | 2012-08-16 | 하나 마이크론(주) | Usb 메모리 패키지 |
KR20120110451A (ko) * | 2011-03-29 | 2012-10-10 | 삼성전자주식회사 | 반도체 패키지 |
US9305853B2 (en) * | 2013-08-30 | 2016-04-05 | Apple Inc. | Ultra fine pitch PoP coreless package |
KR20170001238A (ko) * | 2015-06-26 | 2017-01-04 | 에스케이하이닉스 주식회사 | 계단형 기판을 포함하는 반도체 패키지 |
US10366968B2 (en) | 2016-09-30 | 2019-07-30 | Intel IP Corporation | Interconnect structure for a microelectronic device |
CN108878398B (zh) * | 2017-05-16 | 2020-07-21 | 晟碟半导体(上海)有限公司 | 包括导电凸块互连的半导体器件 |
US11355485B2 (en) * | 2019-06-28 | 2022-06-07 | Western Digital Technologies, Inc. | Semiconductor die and semiconductor package |
US11587918B2 (en) * | 2019-12-17 | 2023-02-21 | Micron Technology, Inc. | Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods |
-
2019
- 2019-12-17 US US16/717,827 patent/US11587918B2/en active Active
-
2020
- 2020-12-04 TW TW109142788A patent/TWI766464B/zh active
- 2020-12-14 KR KR1020200174326A patent/KR20210078415A/ko not_active Application Discontinuation
- 2020-12-15 CN CN202011480298.2A patent/CN112992801A/zh active Pending
-
2021
- 2021-10-04 US US17/493,317 patent/US11984440B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8298940B2 (en) * | 2005-06-30 | 2012-10-30 | Elpida Memory, Inc. | Semiconductor memory device and manufacturing method thereof |
TW200913208A (en) * | 2007-06-11 | 2009-03-16 | Vertical Circuits Inc | Electrically interconnected stacked die assemblies |
Also Published As
Publication number | Publication date |
---|---|
US20210183843A1 (en) | 2021-06-17 |
KR20210078415A (ko) | 2021-06-28 |
US11984440B2 (en) | 2024-05-14 |
US20220028850A1 (en) | 2022-01-27 |
US11587918B2 (en) | 2023-02-21 |
TW202143437A (zh) | 2021-11-16 |
CN112992801A (zh) | 2021-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI766464B (zh) | 半導體裝置、半導體裝置封裝、包括上述之電子系統、及相關方法 | |
EP2996146B1 (en) | Semiconductor package assembly | |
US10276553B2 (en) | Chip package structure and manufacturing method thereof | |
KR102579876B1 (ko) | 반도체 패키지 | |
KR101640076B1 (ko) | 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법 | |
KR102605617B1 (ko) | 적층 반도체 패키지 | |
US9299689B2 (en) | Methods of fabricating semiconductor stack packages | |
KR101645507B1 (ko) | 반도체 패키지 내의 다이간 간격을 감소시키는 언더필 물질 플로우 제어 | |
US8957518B2 (en) | Molded interposer package and method for fabricating the same | |
US7888785B2 (en) | Semiconductor package embedded in substrate, system including the same and associated methods | |
US20160079205A1 (en) | Semiconductor package assembly | |
WO2017041689A1 (zh) | 传感芯片封装组件和具有该传感芯片封装组件的电子设备 | |
EP3364451B1 (en) | Semiconductor package assembly | |
US11694996B2 (en) | Semiconductor package including a pad contacting a via | |
US20140246781A1 (en) | Semiconductor device, method of forming a packaged chip device and chip package | |
KR102562315B1 (ko) | 반도체 패키지 | |
CN111128914A (zh) | 一种低翘曲的多芯片封装结构及其制造方法 | |
US20220238492A1 (en) | Interconnected stacked circuits | |
KR101494414B1 (ko) | 반도체패키지, 반도체패키지유닛 및 반도체패키지 제조방법 | |
KR20230063426A (ko) | 반도체 패키지 및 그 제조방법 | |
TWI763295B (zh) | 半導體封裝結構及其製備方法 | |
US20230209842A1 (en) | Memory system packaging structure, and method for forming the same | |
KR20230031713A (ko) | 반도체 패키지 | |
TW202247363A (zh) | 電子封裝件及其製法 |