TWI763295B - 半導體封裝結構及其製備方法 - Google Patents

半導體封裝結構及其製備方法 Download PDF

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TWI763295B
TWI763295B TW110104046A TW110104046A TWI763295B TW I763295 B TWI763295 B TW I763295B TW 110104046 A TW110104046 A TW 110104046A TW 110104046 A TW110104046 A TW 110104046A TW I763295 B TWI763295 B TW I763295B
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Taiwan
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device die
die
package substrate
active side
electrical connectors
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TW110104046A
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TW202137472A (zh
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楊吳德
尤俊煌
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體封裝結構及其製備方法。該半導體封裝結構具有一第一元件晶粒、多個第一電連接件、一第二元件晶粒以及多個第二電連接件。該第一元件晶粒貼合到一封裝基底。該第一元件晶粒的一主動側面朝該封裝基底。該等第一電連接件連接該第一元件晶粒的該主動側到該封裝基底。該第二元件晶粒的一主動側面朝該封裝基底。該第二元件晶粒之該主動側的一部份位在一區域外，該區域為重疊該第一元件晶粒。該等第二電連接件連接該第二元件晶粒之該主動側的該部分到該封裝基底。

Description

半導體封裝結構及其製備方法
本申請案主張2020年3月16日申請之美國正式申請案第16/819,709號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝結構及其製備方法。特別是有關於一種三維半導體封裝結構及其製備方法。
由於各種電子元件的積體密度的不斷改善，所以半導體產業經歷了持續的增長。此等改善主要係來自最小特徵尺寸的不斷減小，從而允許將更多元件整合到一給定的晶片面積中。
因為積體元件所佔據的體積基本上在半導體晶圓的表面上，所以這些整合的改善本質上是二維的(2D)。雖然微影技術的顯著改善已導致在二維積體電路形成中的顯著改進，但是其可在二維所達到的密度仍是有實體上的限制。當二維的縮放(scaling)仍是一些新設計的一選項，但採用利用z方向的三維封裝組合已成為業界研究的重點。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一元件晶粒，貼合到一封裝基底，其中該第一元件晶粒的一主動側面朝該封裝基底；多個第一電連接件，連接該第一元件晶粒的該主動側到該封裝基底；一第二元件晶粒，堆疊到該第一元件晶粒上，其中該第二元件晶粒的一主動側面朝該封裝基底，且該第二元件晶粒之該主動側的一部分位在一區域，該區域重疊該第一元件晶粒；以及多個第二電連接件，連接該第二元件晶粒之該主動側的該部分到該封裝基底。
在本揭露的一些實施例中，該等第二電連接件具有一高度，大於該等第一電連接件的一高度。
在本揭露的一些實施例中，該半導體封裝結構還包括：一第一黏貼材料，設置在該第一元件晶粒與該封裝基底之間；以及一第二黏貼材料，設置在該第一元件晶粒與該第二元件晶粒之間。
在本揭露的一些實施例中，該第一元件晶粒的一部分並未被該第二黏貼材料所覆蓋。
在本揭露的一些實施例中，該等第一電連接件分別包括一第一導電柱以及一第一焊料接頭(first solder joint)，該第一焊料接頭連接該第一導電柱到該封裝基底，而該等第二電連接件分別包括一第二導電柱以及一第二焊料接頭，該第二焊料接頭連接該第二導電柱到該封裝基底。
在本揭露的一些實施例中，該等第二導電柱具有一高度，大於該等第一導電柱的一高度。
在本揭露的一些實施例中，該封裝基底包括多個積層介電層的一堆疊以及多個導電圖案的多層，而該等導電圖案的該多層分別形成在其中一積層介電層的一側。
在本揭露的一些實施例中，該半導體封裝結構還包括一囊封體(encapsulant)，側向地囊封該第一元件晶粒、該第二元件晶粒、該等第一電連接件以及該等第二電連接件。
在本揭露的一些實施例中，該囊封體的一側壁大致地與該封裝基底的一側壁共面。
在本揭露的一些實施例中，該半導體封裝結構還包括多個封裝輸入/輸出(package inputs/outputs (I/Os))，形成在該封裝基底面向遠離該第一元件晶粒與該第二元件晶粒的一側處。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一元件晶粒，貼合到一封裝基底，其中該第一元件晶粒的一主動側面朝該封裝基底；多個第一電連接件，連接該第一元件晶粒的該主動側到該封裝基底；一第二元件晶粒，堆疊在該第一元件晶粒上，且在該第二元件晶粒的一主動側處具有多個導電墊以及多個重分布結構，其中該第二元件晶粒的該主動側面朝該封裝基底，該等導電墊位在該第二元件晶粒之該主動側重疊該第一元件晶粒的一中心區內，且該等重分布結構連接該等導電墊到該第二元件晶粒之該主動側未重疊該第一元件晶粒的一周圍區；以及多個第二電連接件，連接該封裝基底到該重分布結構位在該第二元件晶粒之該主動側的該周圍區內的一些部分。
在本揭露的一些實施例中，該等重分布結構分別包括：一重分布墊，位在該第二元件晶粒之該主動側的該周圍區內；以及一導電線，連接該重分布墊到其中一導電墊。
在本揭露的一些實施例中，該等第二電連接件連接該等重分布墊到該封裝基底。
在本揭露的一些實施例中，該第一元件晶粒具有多個導電墊，形成在該第一元件晶粒的該主動側處，且該等第一電連接件連接該第一元件晶粒的該等導電墊到該封裝基底。
本揭露之一實施例提供一種半導體封裝結構的製備方法。該製備方法包括貼合一第一元件晶粒到一封裝基底，其中該貼合的第一元件晶粒之一主動側面朝該封裝基底，多個第一電連接件在該第一元件晶粒的貼合前，即預先形成在該第一元件晶粒的該主動側上，且該等第一電連接件在該第一元件晶粒的貼合之後，即連接該第一元件晶粒的該主動側到該封裝基底；以及貼合一第二元件晶粒到該第一元件晶粒與該封裝基底，其中該貼合的第二元件晶粒之一主動側面朝該第一元件晶粒與該封裝基底，該貼合的第二元件晶粒之該主動側的一部分位在一區域外，該區域重疊該貼合的第一元件晶粒，多個第二電連接件在該第二元件晶粒的貼合之前，即預先形成在該第二元件晶粒之該主動側的該部分，且該等第二電連接件在該第二元件晶粒的貼合之後，即連接該第二元件晶粒之該主動側的該部分到該封裝基底。
在本揭露的一些實施例中，該製備方法還包括在該第一元件晶粒的貼合之前，即形成一第一黏貼材料在該封裝基底上，其中在該第一元件晶粒的貼合之後，該第一黏貼材料設置在該封裝基底與該第一元件晶粒的該主動側之間。
在本揭露的一些實施例中，該製備方法還包括在該第二元件晶粒的貼合之前，形成一第二黏貼材料在該第一元件晶粒上，其中在該第二元件晶粒的貼合之後，該第二黏貼材料位在該第一元件晶粒與該第二元件晶粒的該主動側之間。
在本揭露的一些實施例中，該第二元件晶粒預先形成有多個導電墊與多個重分布結構在該第二元件晶粒的該主動側處，該等導電墊位在該第二元件晶粒之該主動側重疊該第一元件晶粒的一中心區內，該等重分布結構連接該等導電墊到該第二元件晶粒之該主動側位在重疊該第一元件晶粒之一區域外的一周圍區，且該等第二電連接件在該第二元件晶粒的貼合之後，即連接該等重分布結構到該封裝基底。
在本揭露的一些實施例中，該製備方法還包括在該第二元件晶粒的貼合之後，藉由一囊封體而側向囊封該第一元件晶粒與該第二元件晶粒。
在本揭露的一些實施例中，該製備方法還包括形成多個封裝輸入/輸出在該封裝基底面向遠離該貼合的第一元件晶粒與該貼合的第二元件晶粒的一側處。
如上所述，依據本揭露之一些實施例的半導體封裝結構具有一下元件晶粒以及一上元件晶粒，該上元件晶粒堆疊在該下元件晶粒上。該下元件晶粒與該上元件晶粒經由多個電連接件而接合到一封裝基底，且該下元件晶粒與該上元件晶粒的各主動側面朝該封裝基底。與其中每個元件晶粒的主動側面向遠離該封裝基板處並通過多個接合線(bonding wires)而電性連接到該封裝基板的一多晶粒半導體封裝相比，本揭露的該等電連接件可具有一較小的長度。再者，由於具有多個導電柱而不是多個接合線，所以本揭露的該等電連接件具有一較厚的直徑。因此，可以減小該等電連接件的電阻率(resistivity)以及在高頻下之該等電連接器的阻抗(impedance)，並可改善在晶粒堆疊(die stack)(包括該下元件晶粒與該上元件晶粒)之間的電性連接。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係 用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1A為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。圖1B為如圖1A所示之該半導體封裝結構中一上元件晶粒的一主動側的平面示意圖。圖1C為如圖1A所示之該半導體封裝結構中一下元件晶粒的一主動側的平面示意圖。
請參考圖1A，在 些實施例中，半導體封裝結構10為一雙晶粒半導體封裝結構。在這些實施例中，半導體封裝結構10可具有一下元件晶粒100以及一上元件晶粒110，上元件晶粒110堆疊在下元件晶粒100上。下元件晶粒100與上元件晶粒110經由一倒裝晶片結合(flip chip bonding)程序而均接合到一封裝基底120。因此，當上元件晶粒110的一後側BS1與下元件晶粒100的一後側BS2面向遠離封裝基底120處時，上元件晶粒110的一主動側AS1與下元件晶粒100的一主動側AS2面朝封裝基底120，而後側BS1與後側BS2係相對主動側AS1與主動側AS2設置。一元件晶粒的主動側(例如上元件晶粒110的主動側AS1或下元件晶粒100的主動側AS2)表示該元件晶粒在有多個導電墊AP形成在其上的一側。該等導電墊AP當成是形成在該元件晶粒中之一積體電路的多個輸入/輸出之功能，並可經由多個內連接結構(圖未示)而電性連接到多個主動/被動元件。在一些實施例中，上元件晶粒110與下元件晶粒100為記憶體晶粒，例如動態隨機存取記憶體(DRAM)晶粒。此外，就電路與尺寸而言，上元件晶粒110可大致與下元件晶粒100相同。或者是，就電路、尺寸以及其他特徵而言，上元件晶粒110與下元件晶粒100可相互不同。
上元件晶粒110係從下元件晶粒100側向偏移，以使上元件晶粒110的一周圍部位在一區域外，而該區域係重疊下元件晶粒100，也因此上元件晶粒110可經由該周圍部而接合到封裝基底120。在一些實施例中，上元件晶粒110與下元件晶粒100藉由多個電連接件EC而接合到封裝基底120。該等電連接件EC可分別具有一導電柱CP以及一焊料接頭SJ。導電柱CP的一端子(terminal)連接到其中一導電墊AP，且導電柱CP的另一端子經由焊料接頭SJ而連接到封裝基底120。因為在上元件晶粒110與封裝基底120間的一垂直空間大於在下元件晶粒100與封裝基底120之間的一垂直空間，所以連接上元件晶粒110到封裝基底120的該等導電柱CP高於連接下元件晶粒100到封裝基底120的該等導電柱CP。在一些實施例中，當連接下元件晶粒100到封裝基底120之該等導電柱CP的一高度介於30到190μm時，連接上元件晶粒110到封裝基底120之該等導電柱CP的一高度可介於50到250μm之間。在一些實施例中，當各焊料接頭SJ由一焊錫材料(solder material)所製時，導電柱CP的一材料可包含金屬(例如銅或銅合金)。然而，本揭露並不以此為限，且所屬技術領域中具有通常知識者可依據製程所需改良該等電連接件EC的尺寸與材料。
請參考圖1A、圖1B以及圖1C，在一些實施例中，該等導電墊AP形成在上元件晶粒110與下元件晶粒100的中心部。舉例來說，如圖1B所示，在上元件晶粒110之中心部內的該等導電墊AP配置成兩行。類似地，如圖1C所示，在下元件晶粒100之中心部內的該等導電墊AP可配置成兩行。然而，本揭露並未以此為限，且所屬技術領域中具有通常知識者可依據設計需求而改良該等導電墊AP的配置。在一些實施例中，如圖1A與圖1B所示，連接上元件晶粒110的周圍部到封裝基底120的該等電連接件EC，可從在上元件晶粒110之中心部內的該等導電墊AP側向偏移。一重分布結構RS可形成在上元件晶粒110的主動側AS1上，以將上元件晶粒110的該等導電墊AP佈線到上元件晶粒110的周圍部，以便可建立位在上元件晶粒110內的該等導電墊AP與連接到上元件晶粒110的該等導電柱CP之間的一電連接。在一些實施例中，該等重分布結構RS分別具有一導電線CL以及一重分布墊RP。導電線CL從上元件晶粒110的其中一導電墊AP延伸到其中一重分布墊RP。舉例來說，如圖1A所示，導電線CL從上元件晶粒110的其中一導電墊AP的一下表面延伸，且側向接觸其中一重分布墊RP。如圖1B所示，導電線CL可形成如當作一直線(straight line)，或可沿其延伸方向而具有至少一轉彎(turn)。另一方面，連接下元件晶粒100到封裝基底120的該等電連接件EC延伸到下元件晶粒100的中心部，並接觸下元件晶粒100沒有一重分布結構在其間的該等導電墊AP。換言之，下元件晶粒100的該等導電墊AP重疊連接到下元件晶粒100的該等導電墊AP之該等電連接件EC。
請參考圖1A、圖1B以及圖1C，一黏貼材料AM1設置在下元件晶粒100與封裝基底120之間，以及一黏貼材料AM2設置在上元件晶粒110與下元件晶粒100之間。如圖1A與圖1B所示，黏貼材料AM2並未覆蓋上元件晶粒110的整個主動側AS1。反而是，黏貼材料AM2覆蓋上元件晶粒110的一部分，該部分係重疊下元件晶粒100，但黏貼材料AM2並未延伸到上元件晶粒110的周圍部，而一些電連接件EC係連接到上元件晶粒110的周圍部。因此，當每一導電線CL的餘留部分以及該等重分布墊RP未被黏貼材料AM2所覆蓋時，在上元件晶粒110的中心部內的該等導電墊AP與每一導線CL連接此等導電墊AP到該等重分布墊RP的一部分，係被黏貼材料AM2所覆蓋。應當理解，雖然黏貼材料AM2被描述成具有對準上元件晶粒110之各邊緣的多個邊緣，但是黏貼材料AM2的此等邊緣可交錯地側向從上元件晶粒110的此等邊緣突出或凹陷。另一方面，如圖1A與圖1C所示，覆蓋下元件晶粒100之主動側AS2的黏貼材料AM1，設置在該等導電墊AP位在下元件晶粒100之主動側AS2的相對側，且並未覆蓋此等導電墊AP。在一些實施例中，黏貼材料AM1具有二分離的子部分，每一個設置在該等導電墊AP位在下元件晶粒100之主動側AS2的一側。應當理解，雖然黏貼材料AM1描述成具有對準下元件晶粒100之各邊緣的多個邊緣，但是黏貼材料AM1的此等邊緣可交錯地側向從下元件晶粒100的此等邊緣突出或凹陷。
請參考圖1A，封裝基底120可為一積層基底(built-up substrate)。在一些實施例中，積層基底為一無核心(core-less)積層基底，且具有多個積層介電層122的一堆疊以及多個導電圖案124的多層，其係分別形成在其中一積層介電層122的一側。該等導電圖案124的各層可具有至少一層接地面(ground plane)、至少一層電源面(power plane)以及至少一訊號面(signal plane)與連接該等電連接件EC到形成在封裝基底120之下側處的接地面、電源面、訊號面以及多個封裝輸入/輸出126的多個佈線結構。當最下方的導電圖案124接觸該等封裝輸入/輸出126時，最上方的導電圖案124接觸該等電連接件EC。在特定實施例中，一訊號面跨越在一接地面與一電源面之間。該等佈線結構可具有多個導電跡線(conductive traces)以及多個導電通孔(conductive vias)。當該等導電通孔分別穿過一或多個積層介電層122並電性連接該等電連接件EC到接地面、訊號面、電源面或該等封裝輸入/輸出126時，該等導電跡線分別延伸在其中一積層介電層122的一表面上。因此，一些導電通孔可穿經該等積層介電層122的整個堆疊，並可表示成導電貫穿通孔(conductive through vias)。接地面係電性接地或經配置以接收一參考電壓。電源面經配置以接收一或多個電源供應電壓(power supply voltage(s))。訊號面可經配置以傳送在晶粒堆疊與該等封裝輸入/輸出126之間的輸入/輸出訊號。在一些實施例中，該等封裝輸入/輸出126可為球狀柵格陣列(ball grid array，BGA)球、受控塌陷晶片連接(controlled-collapse-chip-connection，C4)凸塊或其類似物。
或者是，封裝基底120可具有一剛性介電核心層(rigid dielectric core layer)。在此等其他實施例中，如圖1A所示的其中一積層介電層122可被介電核心層所取代。舉例來說，該等積層介電層122之該堆疊的中間一個可被介電核心層所取代。介電核心層可具有一厚度，係甚大於每一積層介電層122的一厚度。因此，可改善封裝基底120的機械強度。另一方面，如圖1A所示的無核心積層基底可具有優點，例如重量輕以及Z方向的低高度。
請參考圖1A，半導體封裝結構10還具有一囊封體(encapsulant)130。囊封體130側向囊封晶粒堆疊，而晶粒堆疊包括上元件晶粒110與下元件晶粒100。此外，囊封體130填滿上元件晶粒110與封裝基底120之間的空間，並填滿下元件晶粒100與封裝基底120之間的空間。因此，每一電連接件EC側向地被囊封體130所圍繞。在一些實施例中，晶粒堆疊(包括上元件晶粒110與下元件晶粒100)被囊封體130所過度膜封(over-molded)。在此等實施例中，上元件晶粒110的一上表面係被囊封體130的一上部所覆蓋。此外，在一些實施例中，囊封體130的一側壁大致與封裝基底120的一側壁為共面。囊封體130具有一模塑化合物(molding compound)，例如環氧樹脂(epoxy resin)。在一些實施例中，囊封體130還具有多個填充粒子(filler particles)(圖未示)，分散在模塑化合物中。該等填充粒子可典型地由一非有機材料(inorganic material)(例如矽石(silica))所製，並經配置以改良囊封體130的材料特性(例如熱膨脹係數(coefficient of thermal expansion，CTE))。
如上所述，依據本揭露的一些實施例的半導體封裝結構10係為一雙晶粒半導體封裝，並具有下元件晶粒100與上元件晶粒110，而上元件晶粒110堆疊在下元件晶粒100上。下元件晶粒100與上元件晶粒110係經由該等電連接件EC而接合到封裝基底120，且下元件晶粒100的主動側AS2與上元件晶粒110的主動側AS1均朝向封裝基底120。當相較於位在每一元件晶粒面向遠離一封裝基底並經由多個接合線(bonding wires)而電性連接到封裝基底處的一主動側之一多晶粒半導體封裝時，本揭露的該等電連接件EC可具有一較小長度。再者，該等電連接件EC可具有一較厚的直徑，所以具有該等導電柱CP，而不是該等接合線。因此，可降低該等電連接件EC的電阻率以及該等電連接件EC在高頻下的阻抗，並可改善在晶粒堆疊(包括下元件晶粒100與上元件晶粒110)之間的電性連接。為了實現在該等元件晶粒與封裝基底120之間如此的電性連接，上元件晶粒110可從下元件晶粒100側向偏移，且連接到上元件晶粒110的該等電連接件EC可具有一垂直長度，係大於連接到下元件晶粒100之該等電連接件EC的一垂直長度。換言之，具有不同垂直長度的該等電連接件EC係用於連接在晶粒堆疊中之該等元件晶粒到封裝基底120。
在其他的實施例中，晶粒堆疊可具有三或多個元件晶粒。換言之，附加的元件晶粒(圖未示)可進一步堆疊在上元件晶粒110上。如此附加的元件晶粒可從下層的一個側向偏移，且經由多個電連接件而電性連接到封裝基底120，該等電連接件係類似於如上所述之該等電連接件EC。
圖2為依據本揭露一些實施例如圖1A所示的該半導體封裝結構之製備方法的流程示意圖。圖3A到圖3F為在如圖1A所示之半導體封裝結構的製備流程期間在不同階段之結構的剖視示意圖。
請參考圖2及圖3A，執行步驟S11，並準備封裝基底120。在一些實施例中，封裝基底120為一無核心積層基底。在如此的實施例中，多個積層介電層122以及多個導電圖案124的多層係交錯地形成在一載體(carrier)(圖未示)上。每一積層介電層122的形成包括疊層製程(lamination process)。此外，該等導電圖案124之每一層的形成可包括一微影(lithography)製程以及一鍍覆(plating)製程，且還可包括一蝕刻製程，其係用於形成多個導電通孔在下層積層介電層122中。接著，載體(圖未示)可從形成上述的結構剝離(debonded)，且餘留的結構形成封裝基底120。在其他的實施例中，封裝基底120具有一核心介電層。在如此的實施例中，該等積層介電層122與該等導電圖案124的各層形成在核心介電層的一單一側或兩相對側上，且一導電貫穿通孔可藉由一鑽孔(drilling)製程(例如雷射鑽孔製程)而形成在核心介電層中。
請參考圖2及圖3B，執行步驟S13，且黏貼材料AM1提供在封裝基底120的一上側上。在一些實施例中，黏貼材料AM1施加在封裝基底120上。如參考圖1A及圖1C所描述的，可形成黏貼材料AM1當作二分離子部分。封裝基底120的一些最上方的導電圖案可暴露在黏貼材料AM1的該等子部分之間的一空間中，以便貼合該等電連接件EC，而該等電連接件EC係連接到在接下來之步驟中的下元件晶粒100(如圖3C所示)。
請參考圖2及圖3C，執行步驟S15，且下元件晶粒100經由一些電連接件EC而貼合到封裝基底120。在一些實施例中，該等電連接件EC係預先形成在下元件晶粒100的該等導電墊AP上，且該等電連接件EC貼合到該等導電圖案124暴露在黏貼材料AM1的該等子部分之間的部分。與此同時，下元件晶粒100之主動側AS2的其他部分係接觸黏貼材料AM1。在一些實施例中，一拾取及放置製程(pick and place process)係用於貼合下元件晶粒100到封裝基底120。此外，可接著執行一熱處理，以接合下元件晶粒100到封裝基底120。
在其他實施例中，在下元件晶粒100接合到封裝基底120之前，黏貼材料AM1可提供在下元件晶粒100的主動側AS2上。
請參考圖2及圖3D，執行步驟S17，且黏貼材料AM2提供在下元件晶粒100的後側BS2上。如參考圖1A及圖1B所描述的，在一些實施例中，黏貼材料AM2並非必須覆蓋下元件晶粒100的整個後側BS2，原因是接下來要貼合的上元件晶粒110係從下元件晶粒100側向偏移。舉例來說，如圖3D所示，下元件晶粒100之後側BS2的一左周圍區並未被黏貼材料AM2所覆蓋。在一些實施例中，用於提供黏貼材料AM2的一方法係包括一點膠製程(dispensing process)。
請參考圖2及圖3E，執行步驟S19，且上元件晶粒110貼合到下元件晶粒100與封裝基底120。上元件晶粒110的主動側AS1面朝下元件晶粒100與封裝基底120。上元件晶粒110的一部份經由黏貼材料AM2而貼合到下元件晶粒100，而上元件晶粒110的其他部分係經由一些電連接件EC而接觸封裝基底120。在一些實施例中，如此的電連接件EC預先形成在該等重分布結構RS的該等重分布墊RP上，而該等重分布結構RS經配置以佈線在上元件晶粒110的一中心區內的該等導電墊AP到上元件晶粒110的一周圍區，且該等電連接件EC貼合到封裝基底120之該等導電圖案124的最上方的部分。在如此的實施例中，該等導電墊AP與該等重分布結構RS的一些部分(例如該等導電線CL的一些部分)可嵌設在黏貼材料AM2中。在一些實施例中，一拾取及放置製程係用於貼合上元件晶粒110到下元件晶粒100以及封裝基底120。此外，可接著執行一熱處理，以接合上元件晶粒110到封裝基底120。
在其他實施例中，在上元件晶粒110接合到下元件晶粒100與封裝基底120之前，黏貼材料AM2可提供在上元件晶粒110的主動側AS1上。
請參考圖2及圖3F，執行步驟S21，且下元件晶粒100與上元件晶粒110係被囊封體130所囊封。在一些實施例中，一轉移模塑(transfer-molding)製程、一壓縮模塑(compression-molding)製程或其他可行的模塑製程可用來形成囊封體130。
請參考圖2及圖1A，執行步驟S23，以便形成該等封裝輸入/輸出126，並執行一單體化製程(singulation process)。該等封裝輸入/輸出126形成在封裝基底120的下表面處，且電性接觸該等導電圖案124的下部。在一些實施例中，用於形成該等封裝輸入/輸出126的一方法包括一植球製程(ball placement process)或其他可行的製程。執行單體化製程以形成半導體元件10如同其中一單體化結構，而單體化製程係例如刀片切割製程(blade sawing process)、一電漿切割製程(plasma-dicing process)或其類似製程。在一些實施例中，該等封裝輸入/輸出126的形成係先於單體化製程。然而，在其他實施例中，單體化製程係隨著在該等封裝輸入/輸出126的形成之後。
因此，完成依據一些實施例的半導體封裝結構10。
圖4為為依據本揭露一些實施例一種半導體封裝結構10a的剖視示意圖。半導體封裝結構10a類似於如圖1A所示的半導體封裝結構10；係將僅描述其差異處，且類似或相同的部分在文中不再重複描述。
請參考圖4，在一些實施例中，下元件晶粒100的該等導電墊AP形成在下元件晶粒100之主動的AS2之一周圍區內。在如此的實施例中，黏貼材料AM1覆蓋下元件晶粒100之主動側AS2的餘留部分，形成如同一連續圖案，而不是如同多個分開的子圖案。類似地，上元件晶粒110的該等導電墊AP係形成在上元件晶粒110之主動側AS1的一周圍區內。結果，可省略如參考圖1A及圖1B所描述的該等重分布結構RS，且連接上元件晶粒110到封裝基底120的該等電連接件EC係取代該等重分布電RP(如圖1A與圖1B所示)而接觸該等導電墊AP。在一些實施例中，如圖4所示，連接到上元件晶粒110的該等電連接件EC以及連接到下元件晶粒100的該等電連接件EC係位在晶粒堆疊的相同側。然而，在其他實施例中，連接到上元件晶粒110的該等電連接件EC以及連接到下元件晶粒100的該等電連接件EC係位在晶粒堆疊的不同側。在一些其他實施例中，上元件晶粒110的該等導電墊AP係位在如圖1A及圖1B所示的上元件晶粒的一中心部內，且下元件晶粒100的該等導電墊AP係位在如圖4所示的下元件晶粒100的周圍區內。
如上所述，依據本揭露的一些實施例的半導體封裝結構具有一下元件晶粒以及一上元件晶粒，而上元件晶粒堆疊在下元件晶粒上。下元件晶粒與上元件晶粒經由多個電連接件而接合到一封裝基底，且下元件晶粒與上元件晶粒的主動側均面朝封裝基底。當相較於位在每一元件晶粒面向遠離一封裝基底並經由多個接合線而電性連接到封裝基底處的一主動側中的一多晶粒半導體封裝時，本揭露的該等電連接件可具有一較小長度。再者，本揭露的該等電連接件可具有一較厚的直徑，原因是具有該等導電柱，而不是該等接合線。因此，可降低該等電連接件的電阻率以及該等電連接件在高頻下的阻抗，並可改善在晶粒堆疊(包括下元件晶粒100與上元件晶粒110)之間的電性連接。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一元件晶粒，貼合到一封裝基底，其中該第一元件晶粒的一主動側面朝該封裝基底；多個第一電連接件，連接該第一元件晶粒的該主動側到該封裝基底；一第二元件晶粒，堆疊到該第一元件晶粒上，其中該第二元件晶粒的一主動側面朝該封裝基底，且該第二元件晶粒之該主動側的一部分位在一區域，該區域重疊該第一元件晶粒；以及多個第二電連接件，連接該第二元件晶粒之該主動側的該部分到該封裝基底。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一元件晶粒，貼合到一封裝基底，其中該第一元件晶粒的一主動側面朝該封裝基底；多個第一電連接件，連接該第一元件晶粒的該主動側到該封裝基底；一第二元件晶粒，堆疊在該第一元件晶粒上，且在該第二元件晶粒的一主動側處具有多個導電墊以及多個重分布結構，其中該第二元件晶粒的該主動側面朝該封裝基底，該等導電墊位在該第二元件晶粒之該主動側重疊該第一元件晶粒的一中心區內，且該等重分布結構連接該等導電墊到該第二元件晶粒之該主動側未重疊該第一元件晶粒的一周圍區；以及多個第二電連接件，連接該封裝基底到該重分布結構位在該第二元件晶粒之該主動側的該周圍區內的一些部分。
本揭露之一實施例提供一種半導體封裝結構的製備方法。該製備方法包括貼合一第一元件晶粒到一封裝基底，其中該貼合的第一元件晶粒之一主動側面朝該封裝基底，多個第一電連接件在該第一元件晶粒的貼合前，即預先形成在該第一元件晶粒的該主動側上，且該等第一電連接件在該第一元件晶粒的貼合之後，即連接該第一元件晶粒的該主動側到該封裝基底；以及貼合一第二元件晶粒到該第一元件晶粒與該封裝基底，其中該貼合的第二元件晶粒之一主動側面朝該第一元件晶粒與該封裝基底，該貼合的第二元件晶粒之該主動側的一部分位在一區域外，該區域重疊該貼合的第一元件晶粒，多個第二電連接件在該第二元件晶粒的貼合之前，即預先形成在該第二元件晶粒之該主動側的該部分，且該等第二電連接件在該第二元件晶粒的貼合之後，即連接該第二元件晶粒之該主動側的該部分到該封裝基底。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體封裝結構 10a:半導體封裝結構 100:下元件晶粒 110:上元件晶粒 120:封裝基底 122:積層介電層 124:導電圖案 126:封裝輸入/輸出 130:囊封體 AM1:黏貼材料 AM2:黏貼材料 AP:導電墊 AS1:主動側 AS2:主動側 BS1:後側 BS:後側 CL:導電線 CP:導電柱 EC:電連接件 RP:重分布墊 RS:重分布結構 SJ:焊料接頭 S11:步驟 S13:步驟 S15:步驟 S17:步驟 S19:步驟 S21:步驟 S23:步驟
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1A為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。 圖1B為如圖1A所示之該半導體封裝結構中一上元件晶粒的一主動側的平面示意圖。 圖1C為如圖1A所示之該半導體封裝結構中一下元件晶粒的一主動側的平面示意圖。 圖2為依據本揭露一些實施例該半導體封裝結構之製備方法的流程示意圖。 圖3A到圖3F為在如圖1A所示之半導體封裝結構的製備流程期間在不同階段之結構的剖視示意圖。 圖4為為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。
10:半導體封裝結構
100:下元件晶粒
110:上元件晶粒
120:封裝基底
122:積層介電層
124:導電圖案
126:封裝輸入/輸出
130:囊封體
AM1:黏貼材料
AM2:黏貼材料
AP:導電墊
AS1:主動側
AS2:主動側
BS1:後側
BS2:後側
CL:導電線
CP:導電柱
EC:電連接件
RP:重分布墊
RS:重分布結構
SJ:焊料接頭

Claims (5)

  1. 一種半導體封裝結構的製備方法，包括：貼合一第一元件晶粒到一封裝基底，其中該貼合的第一元件晶粒之一主動側面朝該封裝基底，多個第一電連接件在該第一元件晶粒的貼合前，即預先形成在該第一元件晶粒的該主動側上，且該等第一電連接件在該第一元件晶粒的貼合之後，即連接該第一元件晶粒的該主動側到該封裝基底；貼合一第二元件晶粒到該第一元件晶粒與該封裝基底，其中該貼合的第二元件晶粒之一主動側面朝該第一元件晶粒與該封裝基底，該貼合的第二元件晶粒之該主動側的一部分位在一區域外，該區域重疊該貼合的第一元件晶粒，多個第二電連接件在該第二元件晶粒的貼合之前，即預先形成在該第二元件晶粒之該主動側的該部分，且該等第二電連接件在該第二元件晶粒的貼合之後，即連接該第二元件晶粒之該主動側的該部分到該封裝基底；以及在該第一元件晶粒的貼合之前，即形成一第一黏貼材料在該封裝基底上，其中在該第一元件晶粒的貼合之後，該第一黏貼材料設置在該封裝基底與該第一元件晶粒的該主動側之間。
  2. 如請求項1所述之製備方法，還包括在該第二元件晶粒的貼合之前，形成一第二黏貼材料在該第一元件晶粒上，其中在該第二元件晶粒的貼合之後，該第二黏貼材料位在該第一元件晶粒與該第二元件晶粒的該主動側之間。
  3. 如請求項1所述之製備方法，其中該第二元件晶粒預先形成有多個導電墊與多個重分布結構在該第二元件晶粒的該主動側處，該等導電墊位在該第二元件晶粒之該主動側重疊該第一元件晶粒的一中心區內，該等重分布結構連接該等導電墊到該第二元件晶粒之該主動側位在重疊該第一元件晶粒之一區域外的一周圍區，且該等第二電連接件在該第二元件晶粒的貼合之後，即連接該等重分布結構到該封裝基底。
  4. 如請求項1所述之製備方法，還包括在該第二元件晶粒的貼合之後，藉由一囊封體而側向囊封該第一元件晶粒與該第二元件晶粒。
  5. 如請求項1所述之製備方法，還包括形成多個封裝輸入/輸出在該封裝基底面向遠離該貼合的第一元件晶粒與該貼合的第二元件晶粒的一側處。
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