CN104037167A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN104037167A CN104037167A CN201410078414.6A CN201410078414A CN104037167A CN 104037167 A CN104037167 A CN 104037167A CN 201410078414 A CN201410078414 A CN 201410078414A CN 104037167 A CN104037167 A CN 104037167A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- chip
- interface
- semiconductor
- contact site
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0239—Material of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一种半导体器件,包括:半导体芯片;从半导体芯片的边界横向延伸的延伸层;布置在延伸层和半导体芯片的至少一侧之上的再分布层,其中再分布层将半导体芯片的至少一个接触部电耦合到接口的至少一个接触部,其中接口的至少一部分横向地延伸超出半导体芯片的边界。
Description
技术领域
本公开内容总地涉及半导体器件。
背景技术
在三维(3D)芯片堆叠体中,两个或多个半导体芯片可堆叠在彼此的顶部上。堆叠体中的相邻芯片可经由接口彼此电耦合。接口的物理设计可以根据给定的标准而被预先确定或固定。例如,接口的几何尺寸,例如长度、宽度、焊盘间距等,可由标准规定。例如,随着在半导体技术中的增加的规模,芯片尺寸可接近或变得甚至小于接口的规定几何尺寸。例如,芯片可具有比由标准所规定的接口的长度小的长度。在这种情况下,修改芯片以适合于部分地较大的接口可能是合乎需要的。
发明内容
提供了半导体器件,其可包括:半导体芯片;从半导体芯片的边界横向延伸的延伸层;布置在延伸层和半导体芯片的至少一侧上的再分布层,其中再分布层将半导体芯片的至少一个接触部电耦合到接口的至少一个接触部,其中接口的至少一部分横向地延伸超出半导体芯片的边界。
附图说明
在附图中,相似的附图标记通常在不同的视图中始终指相同的部件。附图不一定按比例,相反重点通常在于说明本发明的原理。在下面的描述中,参考下面的附图描述了各种方案,其中:
图1是常规三维(3D)逻辑-存储器堆叠体的横截面视图;
图2是在一般“宽I/O”DRAM存储器上的标准化JEDEC“宽I/O”的平面图;
图3是示出增加小逻辑芯片的芯片尺寸以适合于“宽I/O”接口的常规方法的平面图;
图4是根据本文描述的一个或多个方案的半导体器件的例子的平面图,该半导体器件包括从半导体器件的第一半导体芯片的边界横向延伸的延伸层;
图5是包括从第一半导体芯片的两个相对的横向侧延伸的延伸层的半导体器件的例子的平面图;
图6是包括从第一半导体芯片的至少一个横向侧延伸的延伸层的半导体器件的例子的平面图;
图7是半导体器件的例子的平面图,该半导体器件包括用于使布置在第一半导体芯片的边界外部的接口连接改线(reroute)到第一半导体芯片的边界内部的导电接触部的再分布层;
图8是被配置为三维(3D)逻辑-存储器堆叠体的半导体器件的例子的横截面视图;
图9是半导体器件的例子的横截面视图,该半导体器件包括布置在第一半导体芯片的背面和正面之上的再分布层和用于使接口连接改线的穿通过孔;
图10是半导体器件的例子的平面图,该半导体器件包括布置在第一半导体芯片的背面和正面上的再分布层和用于使接口连接改线的穿通过孔。
具体实施方式
下面的详细描述涉及通过举例说明示出本公开内容的特定细节和方案的附图,在本公开内容中,本发明可被实施。本公开内容的这些方案被足够详细地描述以使本领域中的技术人员能够实施本发明。本公开内容的其它方案可被利用,且结构、逻辑和电气变化可被做出而不偏离本发明的范围。本公开内容的各种方案不一定是相互排他的,因为本公开内容的一些方案可与本公开内容的一个或多个其它方案组合以形成新的方案。
在本文中用于描述“在”侧面或表面“之上”形成特征(例如层)的短语“在……之上”可用于意指该特征(例如该层)可“直接”布置或形成在所指的(implied)侧面或表面“上”,例如与所指的侧面或表面直接接触。在本文中用于描述“在”侧面或表面“之上”形成特征(例如层)的短语“在……之上”可用于意指该特征(例如该层)可“间接”布置或形成在所指的侧面或表面“上”,有一个或多个额外的层布置在所指的侧面或表面和所形成的层之间。
术语“耦合”和/或“电耦合”和/或“连接”和/或“电连接”在本文中用于描述一个特征连接到至少一个其它所指的特征,并不打算意指该特征和至少一个其它所指的特征必须直接耦合或连接在一起;介于中间的特征可设置在该特征和至少一个其它所指的特征之间。
术语“至少一个”和“一个或多个”可被理解为包括大于或等于一的任何整数,即,“一”、“二”、“三”、“四”等。
术语“多个”可被理解为包括大于或等于二的任何整数,即,“二”、“三”、“四”、“五”等。
如在本文中使用的术语“标准化”可例如被理解为意指“根据标准”或“由标准定义”,例如根据由标准化委员会、主体或组织例如JEDEC(联合电子设备工程会议)等开发的标准或由该标准定义。
在一个或多个方案中,本公开内容涉及三维(3D)芯片堆叠体,例如逻辑和存储器芯片的堆叠体。下面的描述将主要涉及逻辑/存储器芯片堆叠体作为例子,然而本公开内容不限于这种情况,并通常可适用于任两个或多个芯片的堆叠。例如,逻辑芯片在逻辑芯片上的堆叠;逻辑芯片与RF芯片、模拟/混合信号芯片或功率芯片的堆叠;芯片与传感器、与微电机系统(MEMS)或CMOS图像传感器的堆叠,以及3D堆叠体的任何其它组合。
存储器芯片或存储器芯片的堆叠体可例如包括具有“宽I/O(输入/输出)”接口(JEDEC标准)的动态随机存取存储器(DRAM)存储器芯片或由具有“宽I/O(输入/输出)”接口(JEDEC标准)的动态随机存取存储器(DRAM)存储器芯片构成。如将容易理解的,本公开内容可不限于这种特定的情况。
具有“宽I/O”接口的3D逻辑/存储器芯片堆叠体的一个重要方案是下列事实:逻辑/存储器接口的尺寸根据JEDEC标准被固定到0.52mm×5.25mm。
然而,特别是在移动应用中,很多逻辑芯片(特别是在未来技术中的超过28nm的节点)可具有可接近或甚至小于“宽I/O”标准的长度(5.25mm)的芯片尺寸。因此,可能需要成本有效的解决方案来修改小逻辑芯片以适合于堆叠在顶部上的部分地较大的“宽I/O”接口。
如在图1中的横截面视图100中示出的,例如移动应用的3D逻辑存储器堆叠体可包括具有TSV(硅穿通过孔)102的逻辑芯片101(例如CPU等),TSV102由“宽I/O接口”103连接到单个存储器芯片或存储器芯片104的堆叠体。一般地,这个3D逻辑/存储器芯片堆叠体可通过倒装芯片连接而连接到(多层)球栅阵列(BGA)层压封装,如图1所示。在图1所示的3D逻辑存储器堆叠体中,逻辑芯片101的尺寸大于“宽I/O”接口103的延伸部分(例如,在这里具有μ-凸起和TSV)。
图2在平面图200中示出在一般的“宽I/O”DRAM存储器204上的标准化JEDEC“宽I/O”逻辑-存储器接口(LMI)103。“宽I/O”接口103可包括高密度接触部栅格205,其包括多个导电接触部。
如JEDEC标准所定义的一般DRAM存储器(例如存储器204)的“宽I/O”接口的细节包括例如:
-“宽I/O”可定义LMI上的4个存储器通道(图2中的“通道A”、“通道B”、“通道C”和“通道D”)。
-每个通道可以是128个数据位宽,导致总共512个位;
-每个通道可包括该通道的所有控制、功率和接地;功率连接可在通道之间被共享;
-每个通道可以被独立地控制,例如独立的控制、时钟和数据;
-每个通道可具有布置在6行×50列中的300个连接,导致在所有4个通道中的总共1200个连接;
-引脚位置可以在通道之间是对称的;
-1.2V CMOS信号电平可被无终止地使用;
-焊盘间距可以是40μm×50μm;
-总LMI尺寸可以是0.52mm×5.25mm(如图2所示)。
也就是说,根据JEDEC标准的“宽I/O”接口可具有5.25mm的长度和0.52mm的宽度。
如果例如图1中的逻辑芯片101的相应尺寸小于“宽I/O”接口103的长度,则接口103将不再安装到逻辑芯片101上。处理前述问题的常规方法可以是增加芯片尺寸(在这里是芯片的长度),直到它长/大到足以适合于“宽I/O”接口标准,如图3所示。
图3以平面图300示出小逻辑芯片的芯片尺寸可延长(在硅上),直到它适合于“宽I/O”接口103的尺寸,其中附图标记301表示具有原始芯片尺寸的逻辑芯片,而附图标记301’表示具有延长的芯片尺寸的逻辑尺寸。如可看到的,具有原始芯片尺寸的逻辑芯片301具有比接口103的长度107短的长度106,而具有延长的芯片尺寸的逻辑芯片301’具有比接口103的长度107长的长度108。
如图3所示的延长芯片尺寸的常规方法可能非常昂贵,因为它需要额外的“伪”芯片面积(即,有源或无源电路所不需要的芯片面积),其可能需要用昂贵的硅晶片技术(例如,超过28nm节点)来制造。
在一个或多个方案中,本公开内容提供了相对廉价的(成本有效的)方式来增加逻辑芯片或通常任何第一芯片的尺寸(面积),第一芯片应经由部分地大于第一芯片的芯片尺寸的接口耦合到第二芯片。例如,根据本文所述的一个或多个方案的半导体器件可应用相对廉价的(成本有效的)扇出WLP(晶片级封装)或eWLB(嵌入式晶片级封装球栅阵列)方法来为接口或连接到接口(例如逻辑-存储器接口,例如“宽I/O”接口)的一个或多个导电接触部(例如焊盘)的放置得到足够的空间。
特别是,包括相对廉价的芯片封装材料(例如,诸如模制材料等的塑料材料)或由相对廉价的芯片封装材料构成的延伸层可用于增加芯片尺寸或面积,且布置在延伸层之上的再分布层(RDL)可用于使布置在芯片的边界外部(例如至少部分地在外部,例如完全在外部)(换言之,在原始芯片区域外部)的一个或多个接口连接改线到在芯片的边界内部(在原始芯片区域内部)的芯片的一个或多个导电接触部。RDL可以是单层(singlelevel)RDL或多层RDL(即,具有两个或更多个层次或层的RDL)。多层RDL可例如在相对大数量的接口互连位于芯片的边界外部(在原始芯片区域外部)的情况下被使用。
根据一个或多个方案,本公开内容提议小于标准化芯片到芯片接口(例如标准化逻辑-存储器接口,例如根据JEDEC标准的“宽I/O”存储器接口)的延伸部分的芯片(例如逻辑芯片),以利用具有单层或多层RLD的扇出WLP(eWLB)芯片延伸部分来提供到较大的接口(例如存储器接口)的连接。这种方法可能比增加芯片的面积(例如增加极为先进的逻辑芯片的硅面积的常规方法明显更成本有效(廉价)。
eWLB RDL能够将一个或多个接口连接(例如“宽I/O”连接)改线到小芯片的适当区域,其中穿通过孔(例如硅穿通过孔(TSV))或穿通过孔(例如TSV)的阵列的放置是可能的。
扇出eWLB RDL可只布置在芯片的一侧(例如背面)之上,或可选地可布置在芯片的两侧之上(即,芯片(例如逻辑芯片)的背面之上和正面之上)。
作为芯片(例如逻辑芯片)上的穿通过孔(例如TSV)连接的备选方案,连接的全部或一部分可由穿过在EWLB封装的扇出区域中的延伸层(例如模制化合物)延伸的穿通过孔(例如模制体穿通过孔(through mold via,TMV))提供。这些穿通过孔(例如TMV)与RDL层次(level)结合能够使接口接触部(例如“宽I/O”焊盘)与小芯片(例如逻辑芯片)的正面(有源电路区域)连接并连接到插入层(interposer)(例如层压插入层)(如果必要,甚至绕过小芯片(例如逻辑芯片))。
图4是根据本文描述的一个或多个方案的半导体器件的例子的平面图400。
半导体器件可包括第一半导体芯片401。根据所示例子,第一半导体芯片401可以是类似于图3中的逻辑芯片301的(小)逻辑芯片。然而,第一半导体芯片401可以是不同于逻辑芯片的另一类型的芯片,且通常可以是任何类型的芯片。
第一半导体芯片401将经由标准化芯片到芯片接口403电耦合到第二半导体芯片404。根据所示例子,第二半导体芯片404可以是存储器芯片(例如DRAM芯片)。因此,芯片到芯片接口403可以是逻辑-存储器接口,例如类似于图3所示的接口103的“宽I/O”逻辑-存储器接口。然而,第二半导体芯片404可以是不同于存储器芯片的另一类型的芯片,且通常可以是任何类型的芯片,并且接口403可以是另一类型的接口,例如不同类型的逻辑-存储器接口或不同于逻辑-存储器接口的一种类型的接口,且可以例如是具有至少部分地比第一半导体芯片401的尺寸(面积)大的预定或固定尺寸(由某个标准规定)的任何类型的接口。
如图4所示,第一半导体芯片401可具有小于标准化芯片到芯片接口403的长度407的长度406。例如,在芯片到芯片接口403是“宽I/O”逻辑-存储器接口的情况下,第一半导体芯片401的长度406可小于5.25mm。对于具有不同尺寸的其它类型的接口,长度406可小于不同于5.25mm的某个值,如将容易理解的。
因此,如可从图4中看到的,芯片到芯片接口403的一部分横向延伸超出第一半导体芯片401的边界401a。换句话说,接口403不完全安装到半导体器件的第一半导体芯片401的区域上。特别是,接口403可以比芯片401长。
如图所示,半导体器件还可包括从第一半导体芯片401的边界401a横向延伸的延伸层405。如图4所示,延伸层405可从第一半导体芯片401的所有横向侧(在所示例子中,从芯片401的所有四个横向侧)延伸。也就是说,延伸层405可横向围住第一半导体芯片401。然而,也可能延伸层405只从一些横向侧延伸,例如从第一半导体芯片401的四个横向侧中的一个、两个或三个横向侧,例如从如在示出半导体器件的另一例子的图5中的平面图500所示的两个相对的横向侧或从如在示出半导体器件的另一例子的图6中的平面图600中所示的一个横向侧延伸。
通常,延伸层405可形成为使得第一半导体芯片401和延伸层405的组合面积可大到足以适合标准化芯片到芯片接口403的尺寸或面积,例如“宽I/O”逻辑-存储器接口的尺寸或面积。例如,根据图4到6所示的例子,延伸层405可形成为使得第一半导体芯片401和延伸层405的组合长度408可大于接口403的长度。
延伸层405可包括不同于第一半导体芯片401的材料(或多种材料),例如绝缘材料,例如芯片封装材料,例如塑料材料,例如模制材料(模制化合物),或者可以由这些材料构成。例如,模制材料(模制化合物)可以是由树脂(例如环氧树脂)和填充材料(例如熔融硅石)构成的复合材料。
延伸层405可用作第一半导体芯片401的扇出延伸部分(扇出区)以容纳耦合到接口403的位于芯片401’a的边界401a外部的一个或多个导电接触部(例如焊盘)的一个或多个导电接触部(例如焊盘)。换句话说,由于第一半导体芯片401的小尺寸而不再安装到半导体芯片401上的接口403的导电接触部现在可耦合到布置在延伸层405上的导电接触部,且再分布层(在图4到6中未示出,见例如图7到10)可用于提供那些接触部与第一半导体芯片401的电耦合。
根据一个或多个方案,可提供扇出WLP(eWLB)封装,其可具有单层或——如果需要——多层再分布层(RDL),其中导电接触部(例如接触焊盘)在顶部RDL金属化层中。通过这种方法,将所有必要的接触部(例如焊盘)放置到在扇出区之上或在原始芯片区域之上的芯片(例如逻辑芯片)的RDL中的标准化芯片到芯片接口(例如逻辑-存储器接口,例如(存储器芯片或芯片堆叠体的)“宽I/O”接口变得可能。在原始芯片(例如逻辑芯片)上,不适合的导电接触部(例如不适合的“宽I/O”焊盘)可被移动或重新布置到其它地方,并可通过单层或多层RDL布线来连接,如在本文中参考图7到10描述的。
图7是半导体器件的例子的平面图700,该半导体器件包括再分布层409,再分布层409被配置成将接口连接,例如布置在第一半导体芯片401的边界401a外部的标准化芯片到芯片接口403的导电接触部410改线到在第一半导体芯片401的边界401a内部的(第一半导体芯片401的)导电接触部(例如焊盘)411a。例如,通过存储器芯片404(或存储器芯片堆叠体)上的再分布层409的逻辑-存储器接口连接(例如“宽I/O”接口连接),例如在逻辑芯片401上不适合的“宽I/O”DRAM芯片可被改线到在逻辑芯片401上重新布置或移动的导电接触部(例如焊盘)411a。再分布层409可布置在延伸层405和第一半导体芯片401的至少一侧上。再分布层409可包括导电材料,例如,诸如铜、铝或含铜和/或铝的合金之类的金属或金属合金或可由这些材料构成。再分布层409可包括耦合到芯片到芯片接口403的相应电接触部的一个或多个导电接触部(例如焊盘),并可包括将再分布层409的导电接触部(例如焊盘)连接到第一半导体芯片401的导电接触部(例如焊盘)的一个或多个导电迹线。
说明性地,如图7所示,不是标准化芯片到芯片接口403的所有导电接触部都适合于第一半导体芯片401的原始尺寸或面积,如在本例中的,第一半导体芯片401比接口403短。完全位于第一半导体芯片401的边界401a外部的接口403的一个或多个导电接触部410a可通过再分布层409被改线到位于边界401a内部的一个或多个导电接触部411a。也可以将位于芯片边界401a内部但接近于芯片边界401a的接口403的一个或多个导电接触部410b(例如具有小于或等于大约100μm,例如小于或等于大约50μm的横向距离的接触部410b)改线到完全布置在芯片边界401a内部的第一半导体芯片401的一个或多个导电接触部411a(例如具有大于大约50μm,例如大于大约100μm的离芯片边界401a的横向距离的接触部410a),如图所示。另一方案,完全位于第一半导体芯片401的边界401a内的接口403的导电接触部(例如焊盘)410c可以或可以不被改线,并可耦合到第一半导体芯片401的相应的导电接触部(例如焊盘)411b(未在图7中示出,见例如图8)。
图8是可被配置为三维(3D)逻辑-存储器堆叠体的半导体器件的横截面视图800。
半导体器件可包括可被配置为逻辑芯片(例如中央处理单元(CPU)、图形处理单元(GPU)、应用处理器(AP)、基带调制解调器、微控制器等)的第一半导体芯片401和可被配置为存储器芯片,例如配置为DRAM芯片并经由可以是逻辑-存储器接口(例如“宽I/O”逻辑-存储器接口)的标准化芯片到芯片接口403耦合到第一半导体芯片401的第二半导体芯片404。第二半导体芯片404可以是芯片堆叠体804的部分,例如存储器芯片堆叠体,例如“宽I/O”存储器堆叠体,例如DRAM堆叠体,包括堆叠在第二半导体芯片404的顶部上的至少一个额外的半导体芯片(例如存储器芯片,例如DRAM芯片)。在图8示出的例子中,三个额外的半导体芯片404’、404’’和404’’’堆叠在第二半导体芯片404的顶部上,导致总共四个芯片,然而堆叠体804中的芯片的数量可不同于四个,例如两个、三个、五个、六个、七个等。可选地,只有第二半导体芯片404可布置在第一半导体芯片401之上。
逻辑-存储器接口(例如“宽I/O”接口)403可在原始逻辑芯片尺寸之上延伸。换句话说,接口403可延伸超出第一半导体芯片401的(横向)边界401a,如图所示。延伸层405(例如扇出eWLB延伸部分)可从小逻辑芯片401的边界401a横向延伸以增加逻辑芯片401的芯片面积。延伸层405的一部分可布置在第一半导体芯片401和第二半导体芯片404之间,例如在面向第二半导体芯片404的逻辑芯片401的第一侧401b之上。第一侧401b可以是第一半导体芯片401的背面。也就是说,第一半导体芯片401可如在一般的倒装芯片布置中那样布置,其中第一半导体芯片401的第二侧401c(正面或有源侧)面向下(在这种情况下背离接口403),例如如图8所示朝着球栅阵列。
单层再分布层(RDL)409可布置在延伸层405之上,用于将接口连接(例如“宽I/O”连接),例如位于逻辑芯片401的边界401a外部的接口403的导电接触部(例如焊盘)410(见图7)改线到图8的绘制平面之外的芯片区域,例如到第一半导体芯片401(见图7)的重新布置或移动的导电接触部411。作为单层RDL的备选方案,可使用多层RDL。
再分布层409或再分布层409的一个或多个导电接触部(例如焊盘)409a可通过延伸层405中的一个或多个穿通过孔412(例如封装穿通过孔,例如模制体穿通过孔(TMV))耦合到第一半导体芯片401的相应的导电接触部(例如焊盘)411a、411b。耦合到再分布层409(或耦合到再分布层409的导电接触部409a)的第一半导体芯片401的导电接触部411a、411b可布置在面向第二半导体芯片404的第一半导体芯片401的第一侧401b(例如背面)之上,如图所示。第一半导体芯片401可包括耦合到布置在第一侧401b之上的导电接触部411a、411b并延伸到与第一侧401b相对的第一半导体芯片401的第二侧401c(例如正面)的一个或多个穿通过孔417(例如硅穿通过孔(TSV))。
芯片堆叠体804例如“宽I/O”存储器堆叠体的芯片(除了最上面的芯片以外),即,第二半导体芯片404和额外的半导体芯片404’和404’’还可包括在每种情况下从相应的芯片404、404’、404’’的正面延伸到背面的一个或多个穿通过孔418(例如硅穿通过孔(TSV))以允许芯片堆叠体804的单独芯片之间的电耦合并因而允许经由接口403电耦合到第一半导体芯片401。
穿过第一半导体芯片401的穿通过孔417和穿过芯片堆叠体804(例如“宽I/O”存储器堆叠体)的穿通过孔418也可位于接口403(例如具有40μm×50μm焊盘间距的“宽I/O”逻辑/存储器接口)的相应导电接触部(例如焊盘)之下(或之上),如图8所示。
然而,穿通过孔417可位于其它地方,且在接口403(例如“宽I/O”接口焊盘)的导电接触部(例如焊盘)和相应的穿通过孔417之间的连接可通过扇出eWLB封装的单层或多层RDL409中的改线和/或通过第一半导体芯片401的背面金属化提供。通过使用RDL层的改线能力和/或背面金属化,可能将穿通过孔417或穿通过孔阵列放置在芯片上的任何任意的和用户定义的位置上。此外,通过这种方法,小得多的穿通过孔(即,具有较小的直径)和/或较小的穿通过孔间距(独立于接口焊盘间距(例如“宽I/O”焊盘间距))可被实现(例如通过使用小于5μm的穿通过孔直径和/或小于10μm的穿通过孔间距)。通过这种方法,可节省相当大的量的宝贵的芯片面积。
如在一般倒装芯片布置中那样,第一半导体芯片401(例如芯片401的第二侧,例如正面401c)可耦合到(例如多层)球形栅极阵列(BGA)封装,包括例如通过一个或多个电连接器414(例如焊料凸起(如图所示)或金属(例如Cu)柱)连接到第一半导体芯片401的第二侧(例如正面)401c上的一个或多个导电接触部(例如焊盘)的插入层413(例如具有一个或多个金属化或互连层的层压插入层)和通过一个或多个电连接器416(例如焊料凸起,如图所示)连接到插入层413的印刷电路板(PCB)415。
作为倒装芯片布置(其中第一半导体芯片401的正面(或有源侧)面向球栅阵列(BGA))的备选方案,半导体芯片401也可布置成使得其正面(或有源侧)背离BGA并朝着第二半导体芯片404或芯片堆叠体804。
在另一例子中,可使用在两侧上都具有单层或多层RDL的双侧eWLB延伸部分。这意味着可在连接到标准化接口403,例如逻辑-存储器接口,例如“宽I/O存储器接口”(如图8所示)的第一半导体芯片(例如逻辑芯片)的背面上使用eWLB RDL,并此外在芯片正面上使用eWLB RDL,以连接到插入层413,例如BGA层压体(laminate),如图9和10所示。
图9和图10分别示出包括用于使标准化芯片到芯片接口403的接口连接(例如导电接触部,例如焊盘)改线的再分布层409的半导体器件的横截面视图900和平面图1000,其中再分布层409的第一部分409’布置在第一侧(例如背面)401b上,而再分布层409的第二部分409’’布置在第一半导体芯片401的第二侧(例如正面)401c上。延伸层405(例如eWLB芯片延伸部分)可从第一半导体芯片401的边界401a,例如从第一半导体芯片401的所有横向侧,如图10所示,可选地从第一半导体芯片401的仅仅一些(例如一、二或三个)横向侧横向延伸。延伸层405的一部分可布置在第一半导体芯片401的第一侧401b之上(面向芯片到芯片接口403),而延伸层405的另一部分可布置在第一半导体芯片401的第二侧401c上。延伸层405可因此至少部分地(例如完全)围住第一半导体芯片401。
如在图8的例子中那样,半导体器件可被配置为三维(3D)逻辑-存储器堆叠体,其中第一半导体芯片401可以是逻辑芯片并可耦合(经由芯片到芯片接口403,例如逻辑-存储器接口,例如“宽I/O”接口)到存储器芯片堆叠体804(例如DRAM堆叠体),其包括第二半导体芯片404和可被配置为存储器芯片(例如DRAM芯片)的一个或多个额外的半导体芯片404’、404’’、404’’’。与图8中的附图标记相同的附图标记可表示与那里相同的元件,且为了简洁起见将不在这里再次详细地描述。参考上面的描述。
标准化接口403的一个或多个导电接触部(例如焊盘)410可经由再分布层409被改线。接触部410可包括至少部分地位于第一半导体芯片401的边界401a的外部(例如全部在外部)的一个或多个接触部410a,并且还可能包括位于芯片边界401a内部但接近于芯片边界401a的一个或多个接触部410b,如上所述。
一个或多个穿通过孔412c(例如封装穿通过孔,例如模制体穿通过孔(TMV))可设置在延伸层405中以将改线的接触部410(例如接触部410a和/或410b)电耦合到布置在第二侧(例如正面)401c之上的第一半导体芯片401的一个或多个导电接触部(例如焊盘)。为此目的,相应的穿通过孔412c可耦合到布置在第一半导体芯片401的第一侧401b上的再分布层409的第一部分409’和布置在第一半导体芯片401的第二侧401c上的再分布层409的第二部分409’’,且再分布层409的第二部分409’’还可例如通过布置在延伸层405的部分中的一个或多个穿通过孔412b(例如封装穿通过孔,例如模制体穿通过孔(TMV))进一步耦合到布置在第一半导体芯片401的第二侧401c之上的第一半导体芯片401的一个或多个导电接触部(例如焊盘),延伸层405的所述部分布置在第一半导体芯片401的第二侧401c上,即,在第一半导体芯片401和再分布层409的第二部分409’’之间。再分布层409的第二部分409’’(或再分布层409的第二部分409’’的至少一部分)可例如经由一个或多个电连接器414(例如焊料凸起(如图所示)或金属柱(例如Cu柱))进一步耦合到插入层413,以提供半导体器件到外部器件的电耦合。
穿过延伸层405的一个或多个穿通过孔412c也可能耦合到再分布层409的第二部分409’’的一部分,其可耦合到插入层413而不耦合到第一半导体芯片401。例如,在图9所示的例子中,在图的右手侧上的穿通过孔412c耦合到再分布层409的第二部分409’’的一部分,其耦合到插入层413而不耦合到第一半导体芯片401,而在图的左手侧上的穿通过孔412c耦合到再分布层409的第二部分409’’的一部分,其(通过穿通过孔412)耦合到第一半导体芯片401。说明性地,可能引导在第一半导体芯片401周围的一个或多个接口连接(换句话说,绕过第一半导体芯片401)并将它们直接耦合到插入层413或球栅阵列,而不与第一半导体芯片401进行电接触。
完全位于芯片边界410a内部(例如具有大于或等于大约5μm,例如大于或等于大约10μm的离芯片边界401a的距离)的接口403的一个或多个导电接触部(例如焊盘)410c可例如通过布置在延伸层405的部分中的一个或多个穿通过孔(例如TMV)412a耦合到布置在第一半导体芯片401的第一侧(例如背面)401b之上的第一半导体芯片401的一个或多个导电接触部411b,延伸层405的所述部分布置在第一半导体芯片401的第一侧(例如背面)401b之上。
说明性地,图9和10示出半导体器件的例子,其中标准化芯片到芯片接口403(例如逻辑-存储器接口,例如“宽I/O”接口)在第一半导体芯片(例如逻辑芯片)401的原始芯片尺寸之上延伸,在两侧上(即,在连接到接口(例如“宽I/O”接口)的芯片背面401b上以及在芯片正面上)(例如在后段工艺(BEOL)层之上)的具有单层RDL409的第一半导体芯片(例如(小)逻辑芯片)401的延伸层405(例如扇出eWLB延伸部分)连接到插入层(例如层压插入层)413和第一半导体芯片(例如逻辑芯片)401,且穿通过孔(例如模制体穿通过孔(TMV))412c经由再分布层409(例如eWLB RDL)(在背面401b和正面401c上)使接口403(例如“宽I/O”接口焊盘)的导电接触部与芯片(见图9中的左穿通过孔412c)的有源侧(例如片上互连BEOL)或直接与绕过第一半导体芯片(例如逻辑芯片)401(见图9中的右穿通过孔412c)的插入层(例如层压插入层)413耦合。
上面在本文中结合附图描述的例子主要讨论下列情况:第一半导体芯片的仅仅一个横向尺寸(例如长度)小于标准化芯片到芯片接口的相应尺寸。然而,如将容易理解的,在本文中讨论的一个或多个方案可同样适用于下列情况:第一半导体芯片的多于一个横向尺寸(例如长度和宽度)小于标准化芯片到芯片接口的相应尺寸。例如,如果第一半导体芯片的长度和宽度都小于标准化接口的相应长度和宽度,则延伸层(例如eWLB扇出区)可配置成增加原始芯片面积,使得接口安装到具有延伸部分的芯片上。
可例如使用用于制造eWLB封装的已知制造工艺来形成延伸层和再分布层。
根据一个或多个方案,半导体器件可包括:半导体芯片;从半导体芯片的边界横向延伸的延伸层;布置在延伸层和半导体芯片的至少一侧上的再分布层,其中再分布层将半导体芯片的至少一个接触部电耦合到接口的至少一个接触部,其中接口的至少一部分横向延伸超出半导体芯片的边界。
接口的至少一个接触部可至少部分地布置在半导体芯片的边界外部。
再分布层可包括至少一种导电材料,例如至少一种金属和/或合金,例如铝、铜、铝合金和/或铜合金,或者可由这些材料构成。
再分布层可包括至少一个金属化层。例如,再分布层可具有单个金属化层(单层RDL)。可选地,再分布层可具有多个金属化层(多层RDL)。
半导体芯片的至少一个接触部可包括或可以是至少一个导电接触部。半导体芯片的至少一个接触部可包括或可以是至少一个焊盘(也被称为接触焊盘),例如多个焊盘(接触焊盘)。
半导体芯片可以是逻辑芯片,例如CPU(中央处理单元)等。
半导体芯片可包括任何适当的半导体材料或可由任何适当的半导体材料构成,所述半导体材料包括化合物半导体。例如,半导体芯片可包括硅或可以是硅芯片。
接口可以是标准化接口,例如标准化芯片到芯片接口。标准化芯片到芯片接口可以是标准化逻辑-存储器接口,例如“宽I/O”逻辑-存储器-接口。
标准化接口(例如标准化芯片到芯片接口)可具有标准化几何尺寸,例如标准化长度和/或宽度和/或标准化焊盘间距。焊盘间距例如指在两个相邻焊盘的相应中心之间的距离。在焊盘沿着两个主要轴(例如长度轴和宽度轴)布置在矩形阵列中的情况下,对于这两个轴,焊盘间距可以是相同的或可以是不同的。
半导体芯片的至少一个几何尺寸可以小于标准化芯片到芯片接口的相应几何尺寸。
半导体芯片可具有比标准化接口(例如标准化芯片到芯片接口)小的长度。换句话说,半导体芯片可以比标准化接口(例如标准化芯片到芯片接口)短。
延伸层可由不同于半导体芯片的材料(或多种材料)构成。
延伸层可包括封装材料(例如芯片封装材料)或可由封装材料(例如芯片封装材料)构成。
延伸层可包括绝缘材料或可由绝缘材料构成。
延伸层可包括塑料材料(例如模制材料(例如模制化合物))或由塑料材料(例如模制材料(例如模制化合物))构成。
再分布层可包括耦合到至少部分地布置在半导体芯片的边界外部的接口(例如标准化接口,例如标准化芯片到芯片接口)的至少一个接触部(例如导电接触部)的至少一个接触部(例如导电接触部)。
再分布层还可包括耦合到布置在半导体芯片的边界内部的接口(例如标准化接口,例如标准化芯片到芯片接口)的至少一个接触部(例如导电接触部)的至少一个接触部(例如导电接触部)。布置在半导体芯片的边界内部的接口(例如标准化接口,例如标准化芯片到芯片接口)的至少一个接触部(例如导电接触部)可具有大于或等于大约5μm(例如大于或等于大约10μm)的离边界的距离。
接口(例如标准化接口,例如标准化芯片到芯片接口)的至少一个接触部(例如导电接触部)可被配置为焊盘,例如金属焊盘。
再分布层的一个或多个接触部(例如导电接触部)可被配置为焊盘,例如金属焊盘。
再分布层的一个或多个焊盘可布置在再分布层的顶部金属化层中。
半导体芯片可具有比接口(例如标准化接口,例如标准化芯片到芯片接口)小的焊盘间距。换句话说,半导体芯片的焊盘可布置在比接口(例如标准化接口,例如标准化芯片到芯片接口)的焊盘小的间距(距离)处。
再分布层可布置在半导体芯片的第一侧之上和/或与第一侧相对的半导体芯片的第二侧之上。例如,再分布层的第一部分可布置在半导体芯片的第一侧之上,而再分布层的第二部分可布置在半导体芯片的第二侧之上。
第一侧可以是半导体芯片的背面,而第二侧可以是半导体芯片的正面。(例如半导体芯片的)芯片的正面可以是芯片的有源侧(或有源区域近侧的侧面),而(例如半导体芯片的)芯片的背面可以是与芯片(例如半导体芯片)的有源侧(或在有源区域远侧的侧面)相对的侧面。
半导体芯片的正面(例如有源侧)可背离接口(例如标准化接口,例如标准化芯片到芯片接口)。可选地,半导体芯片的正面(例如有源侧)可面向接口(例如标准化接口,例如标准化芯片到芯片接口)。
半导体芯片可包括从半导体芯片的第一侧(例如背面)延伸到第二侧(例如正面)的至少一个穿通过孔,例如多个穿通过孔,例如一个或多个硅穿通过孔(TSV),穿通过孔可电耦合到半导体芯片的至少一个接触部(例如导电接触部(例如焊盘))。穿通过孔(例如TSV)可例如具有小于或等于大约10μm的直径,例如在从大约2μm到大约10μm的范围内的直径,例如小于或等于大约5μm的直径,例如在从大约2μm到大约5μm的范围内的直径,虽然其它值也是可能的。
延伸层可布置在半导体芯片和再分布层之间的半导体芯片的第一侧(例如背面)之上。
延伸层可包括使半导体芯片的至少一个接触部(例如导电接触部)与再分布层(例如与再分布层的至少一个焊盘)电耦合的至少一个穿通过孔(例如封装穿通过孔(TEV),例如模制体穿通过孔(TMV)),例如使半导体芯片的多个接触部(例如导电接触部)与再分布层(例如与再分布层的多个焊盘)电耦合的多个穿通过孔(例如TEV,例如TMV)。
穿通过孔可例如具有在从大约50μm到大约100μm的范围内的直径,例如大约50μm的直径,虽然其它值也是可能的。
再分布层可包括布置在半导体芯片的第一侧(例如背面)之上的第一部分和布置在与第一侧相对的半导体芯片的第二侧(例如正面)之上的第二部分。
再分布层的第一部分可包括耦合到至少部分地布置在半导体芯片的边界外部的接口(例如标准化接口,例如标准化芯片到芯片接口)的至少一个接触部(例如导电接触部)的至少一个接触部(例如导电接触部),且延伸层可包括使再分布层的第一部分与再分布层的第二部分电耦合的至少一个穿通过孔(例如封装穿通过孔(TEV),例如模制体穿通过孔(TMV))。
半导体芯片可包括布置在半导体芯片的第二侧(例如正面)之上并与再分布层的第二部分电耦合的至少一个接触部(例如导电接触部)。
半导体芯片的第二侧(例如正面)可背离接口(例如标准化接口,例如标准化芯片到芯片接口)。
半导体芯片的第二侧(例如正面)和接口(例如标准化接口,例如标准化芯片到芯片接口)可布置在半导体器件的相对侧处。
延伸层可从半导体芯片的至少一个横向侧延伸。
延伸层可从半导体芯片的至少四个侧面,例如从半导体芯片的至少所有横向侧延伸。
延伸层的一部分可布置在半导体芯片的第一侧(例如背面)之上。
延伸层的一部分可布置在半导体芯片的第二侧(例如正面)之上。
延伸层可至少部分地封装半导体芯片。
例如,延伸层可横向围住半导体芯片,并可布置在半导体芯片的背面之上和/或半导体芯片的正面之上。
半导体芯片可以是第一半导体芯片,且半导体器件还可包括具有接口(例如标准化接口,例如标准化芯片到芯片接口)并经由接口(例如标准化接口,例如标准化芯片到芯片接口)电耦合到第一半导体芯片的第二半导体芯片。
第二半导体芯片可包括任何适当的半导体材料或可由任何适当的半导体材料构成,所述半导体材料包括化合物半导体。例如,第二半导体芯片可包括硅或可以是硅芯片。
第二半导体芯片可布置在再分布层之上,其中根据接口(例如标准化接口,例如标准化芯片到芯片接口)布置的第二半导体芯片的一个或多个接触部(例如导电接触部)可电耦合到根据接口(例如标准化接口,例如标准化芯片到芯片接口)布置的再分布层的一个或多个接触部(例如导电接触部)。
第二半导体芯片可以是存储器芯片,例如DRAM(动态随机存取存储器)芯片,可选地任何其它类型的(易失性或非易失性)存储器芯片。第一半导体芯片可以是逻辑芯片(例如CPU等),且第二半导体芯片可以是存储器芯片(例如DRAM芯片或任何其它类型的存储器芯片)。
半导体器件还可包括布置在第二半导体芯片的背离第一半导体芯片的一侧之上并电耦合到第二半导体芯片的至少一个额外的半导体芯片。
至少一个额外的半导体芯片可以是存储器芯片(例如DRAM芯片或任何其它类型的存储器芯片)。
半导体器件可被配置为包括第一半导体芯片的三维(3D)芯片堆叠体,其可例如是逻辑芯片(例如CPU等)和一个堆叠在另一个之上的、布置在再分布层之上并经由标准化芯片到芯片接口(例如逻辑到存储器接口)电耦合到第一半导体芯片(例如逻辑芯片)的多个芯片(例如存储器芯片,例如DRAM芯片或任何其它类型的存储器芯片)。
半导体器件还可包括布置在第一半导体芯片的背离第二半导体芯片的一侧之上并电耦合到第一半导体芯片的插入层。
插入层可布置在第一半导体芯片的第二侧(例如正面)之上。
插入层可包括电绝缘材料。
插入层可包括层压材料或层压体或者由层压材料或层压体构成。
插入层可包括印刷电路板(PCB)或由印刷电路板(PCB)构成。
插入层可包括至少一个互连层。
插入层可包括多个互连层。
插入层可以是硅插入层。
插入层可以是玻璃插入层。
半导体器件还可包括布置在插入层和第一半导体芯片之间并将插入层电耦合到第一半导体芯片的至少一个电连接器。
至少一个电连接器可包括多个焊料凸起。
至少一个电连接器可包括多个金属柱(例如铜柱)。
半导体器件还可包括布置在背离第一半导体芯片的插入层的一侧之上的球栅阵列。
根据一个或多个方案,半导体器件可包括:具有电耦合到具有有着标准化几何尺寸的接口(例如芯片到芯片接口)的第二半导体芯片的至少一个接触部(例如导电接触部)的第一半导体芯片,其中第一半导体芯片沿着至少一个方向的横向尺寸小于接口(例如芯片到芯片接口)沿着至少一个方向的横向尺寸;沿着至少一个方向从第一半导体芯片的至少一侧横向延伸的延伸层,其中第一半导体芯片和延伸层沿着至少一个方向的组合横向尺寸大于或等于接口(例如芯片到芯片接口)沿着至少一个方向的横向尺寸;布置在延伸层和第一半导体芯片的至少一侧上的再分布层,再分布层将第一半导体芯片的至少一个接触部(例如导电接触部)电耦合到至少部分地布置在第一半导体芯片的边界外部的接口(例如芯片到芯片接口)的至少一个接触部(例如导电接触部)。
半导体器件还可包括具有有着标准化几何尺寸的接口(例如芯片到芯片接口)的第二半导体芯片,其中第二半导体芯片经由接口(例如芯片到芯片接口)电耦合到第一半导体芯片。
接口(例如芯片到芯片接口)可包括多个接触部(例如导电接触部),其中多个接触部(例如导电接触部)中的至少一个接触部(例如导电接触部)至少部分地布置在第一半导体芯片的边界外部。
第一半导体芯片可以是逻辑芯片(例如CPU等),且第二半导体芯片可以是存储器芯片(例如DRAM芯片或任何其它类型的存储器芯片)。
根据一个或多个方案,半导体器件可包括:具有第一多个接触部(例如导电接触部)的第一半导体芯片;从第一半导体芯片的横向边界延伸的延伸层;布置在延伸层和第一半导体芯片之上并具有电耦合到第一多个接触部(例如导电接触部)的第二多个接触部(例如导电接触部)的再分布层,其中第二多个接触部(例如导电接触部)中的至少一个接触部(例如导电接触部)至少部分地布置在第一半导体芯片的横向边界外部,其中第二多个接触部(例如导电接触部)根据预定的接口标准(例如芯片到芯片接口标准)而布置。
半导体器件还可包括:具有根据预定的接口标准(例如芯片到芯片接口标准)而布置的第三多个接触部(例如导电接触部)的第二半导体芯片,其中第三多个接触部(例如导电接触部)与第二多个接触部(例如导电接触部)接触。
第一半导体芯片可以是逻辑芯片,而第二半导体芯片可以是存储器芯片,其中预定的接口标准(例如芯片到芯片接口标准)是逻辑-存储器接口标准。
延伸层可包括将第一多个接触部(例如导电接触部)中的至少一个接触部(例如导电接触部)电耦合到第二多个接触部(例如导电接触部)中的至少一个接触部(例如导电接触部)的至少一个穿通过孔。
根据一个或多个方案,半导体器件可包括:经由标准化芯片到芯片接口电耦合到第二半导体芯片的第一半导体芯片,其中标准化芯片到芯片接口的至少一部分横向延伸超出第一半导体芯片的边界;从第一半导体芯片的边界横向延伸的延伸层;布置在延伸层和第一半导体芯片的至少一侧之上的再分布层,再分布层配置成将第一半导体芯片的至少一个导电接触部电耦合到至少部分地布置在第一半导体芯片的边界外部的标准化芯片到芯片接口的至少一个导电接触部。
根据一个或多个方案,半导体器件可包括:具有电耦合到具有有着标准化几何尺寸的芯片到芯片接口的第二半导体芯片的至少一个导电接触部的第一半导体芯片,其中第一半导体芯片沿着至少一个方向的横向尺寸小于芯片到芯片接口沿着至少一个方向的横向尺寸;沿着至少一个方向从第一半导体芯片的至少一侧横向延伸的延伸层,其中第一半导体芯片和延伸层沿着至少一个方向的组合横向尺寸大于或等于芯片到芯片接口沿着所述至少一个方向的横向尺寸;布置在延伸层和第一半导体芯片的至少一侧之上的再分布层,再分布层配置成将第一半导体芯片的至少一个导电接触部改线到至少部分地布置在第一半导体芯片的边界外部的芯片到芯片接口的至少一个导电接触部。
根据一个或多个方案,半导体器件可包括:具有第一多个导电接触部的第一半导体芯片;从第一半导体芯片的横向边界延伸的延伸层;布置在延伸层和第一半导体芯片之上并具有电耦合到第一多个导电接触部的第二多个导电接触部的再分布层,其中第二多个导电接触部的至少一个导电接触部至少部分地布置在第一半导体芯片的横向边界外部,其中第二多个导电接触部根据预定的芯片到芯片接口标准而布置。
虽然参考特定的方案特别示出和描述了本发明,本领域中的技术人员应理解,在形式和细节上的各种改变可在其中做出,而不偏离如所附权利要求限定的本发明的精神和范围。本发明的范围因此由所附权利要求表明,且因此意在包括出现在权利要求的等效性的意义和范围内的所有变化。
Claims (27)
1.一种半导体器件,包括:
半导体芯片;
延伸层,其从所述半导体芯片的边界横向延伸;
再分布层,其布置在所述延伸层和所述半导体芯片的至少一侧之上,其中所述再分布层将所述半导体芯片的至少一个接触部电耦合到接口的至少一个接触部,其中所述接口的至少一部分横向延伸超出所述半导体芯片的所述边界。
2.如权利要求1所述的半导体器件,其中所述接口的所述至少一个接触部至少部分地布置在所述半导体芯片的所述边界的外部。
3.如权利要求1所述的半导体器件,其中所述接口是标准化接口。
4.如权利要求3所述的半导体器件,其中所述标准化接口是标准化芯片到芯片接口。
5.如权利要求3所述的半导体器件,其中所述标准化接口包括标准化几何尺寸。
6.如权利要求3所述的半导体器件,其中所述半导体芯片的长度小于所述标准化接口的长度。
7.如权利要求1所述的半导体器件,其中所述延伸层由不同于所述半导体芯片的材料构成。
8.如权利要求2所述的半导体器件,其中所述再分布层包括与所述接口的、至少部分地布置在所述半导体芯片的所述边界的外部的至少一个接触部相耦合的至少一个接触部。
9.如权利要求8所述的半导体器件,其中所述再分布层还包括与所述接口的、布置在所述半导体芯片的所述边界的内部的至少一个接触部相耦合的至少一个接触部。
10.如权利要求1所述的半导体器件,其中所述再分布层布置在所述半导体芯片的背面之上。
11.如权利要求10所述的半导体器件,其中所述延伸层布置在所述半导体芯片的、位于所述半导体芯片和所述再分布层之间的所述背面之上。
12.如权利要求11所述的半导体器件,其中所述延伸层包括使所述半导体芯片的至少一个接触部与所述再分布层电耦合的至少一个穿通过孔。
13.如权利要求1所述的半导体器件,其中所述再分布层包括布置在所述半导体芯片的第一侧之上的第一部分和布置在所述半导体芯片的与所述第一侧相对的第二侧之上的第二部分。
14.如权利要求13所述的半导体器件,
其中所述再分布层的所述第一部分包括与所述接口的、至少部分地布置在所述半导体芯片的所述边界的外部的至少一个接触部相耦合的至少一个接触部,
其中所述延伸层包括使所述再分布层的所述第一部分与所述再分布层的所述第二部分电耦合的至少一个穿通过孔。
15.如权利要求14所述的半导体器件,
其中所述半导体芯片包括布置在所述半导体芯片的所述第二侧之上并与所述再分布层的所述第二部分电耦合的至少一个接触部。
16.如权利要求15所述的半导体器件,其中所述第一侧是所述半导体芯片的背面,而所述第二侧是所述半导体芯片的正面。
17.如权利要求1所述的半导体器件,其中所述延伸层至少部分地包封所述半导体芯片。
18.如权利要求1所述的半导体器件,其中所述半导体芯片是第一半导体芯片,所述半导体器件还包括具有所述接口的第二半导体芯片,其中所述第二半导体芯片经由所述接口电耦合到所述第一半导体芯片。
19.如权利要求18所述的半导体器件,
其中所述第一半导体芯片是逻辑芯片,且所述第二半导体芯片是存储器芯片。
20.如权利要求18所述的半导体器件,还包括布置在所述第二半导体芯片的背离所述第一半导体芯片的一侧之上并且电耦合到所述第二半导体芯片的至少一个额外的半导体芯片。
21.一种半导体器件,包括:
第一半导体芯片,其具有电耦合到第二半导体芯片的至少一个接触部,其中所述第二半导体芯片具有接口,所述接口具有标准化几何尺寸,其中所述第一半导体芯片沿着至少一个方向的横向尺寸小于所述接口沿着所述至少一个方向的横向尺寸;
延伸层,其沿着所述至少一个方向从所述第一半导体芯片的至少一侧横向延伸,其中所述第一半导体芯片和所述延伸层沿着所述至少一个方向的组合横向尺寸大于或等于所述接口沿着所述至少一个方向的横向尺寸;
再分布层,其布置在所述延伸层和所述第一半导体芯片的至少一侧之上,所述再分布层将所述第一半导体芯片的至少一个接触部电耦合到所述接口的、至少部分地布置在所述第一半导体芯片的边界的外部的至少一个接触部。
22.如权利要求21所述的半导体器件,还包括具有有着标准化几何尺寸的所述接口的第二半导体芯片,其中所述第二半导体芯片经由所述接口电耦合到所述第一半导体芯片。
23.如权利要求22所述的半导体器件,其中所述第一半导体芯片是逻辑芯片,且所述第二半导体芯片是存储器芯片。
24.一种半导体器件,包括:
第一半导体芯片,其具有第一多个接触部;
延伸层,其从所述第一半导体芯片的横向边界延伸;
再分布层,其布置在所述延伸层和所述第一半导体芯片之上并且具有电耦合到所述第一多个接触部的第二多个接触部,
其中所述第二多个接触部中的至少一个接触部至少部分地布置在所述第一半导体芯片的所述横向边界的外部,
其中所述第二多个接触部被根据预定的接口标准而布置。
25.如权利要求24所述的半导体器件,还包括:
第二半导体芯片,其具有被根据所述预定的接口标准而布置的第三多个接触部,
其中所述第三多个接触部与所述第二多个接触部接触。
26.如权利要求25所述的半导体器件,
其中所述第一半导体芯片是逻辑芯片,而所述第二半导体芯片是存储器芯片,
其中所述预定的接口标准是逻辑-存储器接口标准。
27.如权利要求26所述的半导体器件,其中所述延伸层包括至少一个穿通过孔,所述至少一个穿通过孔将所述第一多个接触部中的至少一个接触部电耦合到所述第二多个接触部中的至少一个接触部。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/786,538 US20140252632A1 (en) | 2013-03-06 | 2013-03-06 | Semiconductor devices |
US13/786,538 | 2013-03-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104037167A true CN104037167A (zh) | 2014-09-10 |
Family
ID=50184830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410078414.6A Pending CN104037167A (zh) | 2013-03-06 | 2014-03-05 | 半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20140252632A1 (zh) |
EP (1) | EP2775512A3 (zh) |
JP (1) | JP5940577B2 (zh) |
KR (1) | KR20140109833A (zh) |
CN (1) | CN104037167A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105391823A (zh) * | 2015-11-25 | 2016-03-09 | 上海新储集成电路有限公司 | 一种降低移动设备尺寸和功耗的方法 |
CN109509746A (zh) * | 2017-09-15 | 2019-03-22 | 东芝存储器株式会社 | 半导体装置 |
CN110033813A (zh) * | 2018-08-31 | 2019-07-19 | 济南德欧雅安全技术有限公司 | 一种翻译器设备 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324698B2 (en) | 2013-08-13 | 2016-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip structure and method of forming same |
US9263370B2 (en) * | 2013-09-27 | 2016-02-16 | Qualcomm Mems Technologies, Inc. | Semiconductor device with via bar |
US9299677B2 (en) * | 2013-12-31 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with multiple plane I/O structure |
US9721852B2 (en) * | 2014-01-21 | 2017-08-01 | International Business Machines Corporation | Semiconductor TSV device package to which other semiconductor device package can be later attached |
KR20150135611A (ko) * | 2014-05-22 | 2015-12-03 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지 및 제조 방법 |
EP3055882B1 (en) * | 2014-12-22 | 2020-09-16 | INTEL Corporation | Multilayer substrate for semiconductor packaging and method |
US10319701B2 (en) | 2015-01-07 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded 3D integrated circuit (3DIC) structure |
WO2016154526A1 (en) * | 2015-03-26 | 2016-09-29 | Board Of Regents, The University Of Texas System | Capped through-silicon-vias for 3d integrated circuits |
US9455243B1 (en) | 2015-05-25 | 2016-09-27 | Inotera Memories, Inc. | Silicon interposer and fabrication method thereof |
JP6515724B2 (ja) * | 2015-07-31 | 2019-05-22 | 富士通株式会社 | 半導体装置 |
US9607973B1 (en) * | 2015-11-19 | 2017-03-28 | Globalfoundries Inc. | Method for establishing interconnects in packages using thin interposers |
US9698108B1 (en) | 2015-12-23 | 2017-07-04 | Intel Corporation | Structures to mitigate contamination on a back side of a semiconductor substrate |
KR102605618B1 (ko) * | 2016-11-14 | 2023-11-23 | 삼성전자주식회사 | 이미지 센서 패키지 |
US20180166417A1 (en) * | 2016-12-13 | 2018-06-14 | Nanya Technology Corporation | Wafer level chip-on-chip semiconductor structure |
US20180175004A1 (en) * | 2016-12-18 | 2018-06-21 | Nanya Technology Corporation | Three dimensional integrated circuit package and method for manufacturing thereof |
US10410969B2 (en) * | 2017-02-15 | 2019-09-10 | Mediatek Inc. | Semiconductor package assembly |
JP6649308B2 (ja) * | 2017-03-22 | 2020-02-19 | キオクシア株式会社 | 半導体装置およびその製造方法 |
US10861773B2 (en) * | 2017-08-30 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
JP6892360B2 (ja) * | 2017-09-19 | 2021-06-23 | キオクシア株式会社 | 半導体装置 |
KR102382860B1 (ko) | 2017-12-13 | 2022-04-06 | 삼성전자주식회사 | 이미지 센싱 시스템 및 이의 동작 방법 |
US10980127B2 (en) * | 2019-03-06 | 2021-04-13 | Ttm Technologies Inc. | Methods for fabricating printed circuit board assemblies with high density via array |
JP7326192B2 (ja) * | 2020-03-17 | 2023-08-15 | キオクシア株式会社 | 配線基板及び半導体装置 |
US11302674B2 (en) * | 2020-05-21 | 2022-04-12 | Xilinx, Inc. | Modular stacked silicon package assembly |
US11978723B2 (en) | 2021-03-31 | 2024-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical interconnect structures in three-dimensional integrated circuits |
US11791326B2 (en) * | 2021-05-10 | 2023-10-17 | International Business Machines Corporation | Memory and logic chip stack with a translator chip |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090026629A1 (en) * | 2007-07-27 | 2009-01-29 | Min Suk Suh | Semiconductor package having a stacked wafer level package and method for fabricating the same |
US20100255614A1 (en) * | 2006-06-30 | 2010-10-07 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method of same |
US20110159639A1 (en) * | 2009-12-31 | 2011-06-30 | Kuo-Chung Yee | Method for Making a Stackable Package |
US20120168917A1 (en) * | 2010-12-31 | 2012-07-05 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3772066B2 (ja) * | 2000-03-09 | 2006-05-10 | 沖電気工業株式会社 | 半導体装置 |
JP4343727B2 (ja) * | 2004-02-13 | 2009-10-14 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2007036104A (ja) * | 2005-07-29 | 2007-02-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2010161102A (ja) * | 2009-01-06 | 2010-07-22 | Elpida Memory Inc | 半導体装置 |
JP5543125B2 (ja) * | 2009-04-08 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置および半導体装置の製造方法 |
JP2012069734A (ja) * | 2010-09-24 | 2012-04-05 | Toshiba Corp | 半導体装置の製造方法 |
-
2013
- 2013-03-06 US US13/786,538 patent/US20140252632A1/en not_active Abandoned
-
2014
- 2014-02-28 EP EP14157382.4A patent/EP2775512A3/en active Pending
- 2014-03-05 CN CN201410078414.6A patent/CN104037167A/zh active Pending
- 2014-03-05 KR KR1020140026165A patent/KR20140109833A/ko not_active Application Discontinuation
- 2014-03-06 JP JP2014043675A patent/JP5940577B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100255614A1 (en) * | 2006-06-30 | 2010-10-07 | Fujitsu Microelectronics Limited | Semiconductor device and manufacturing method of same |
US20090026629A1 (en) * | 2007-07-27 | 2009-01-29 | Min Suk Suh | Semiconductor package having a stacked wafer level package and method for fabricating the same |
US20110159639A1 (en) * | 2009-12-31 | 2011-06-30 | Kuo-Chung Yee | Method for Making a Stackable Package |
US20120168917A1 (en) * | 2010-12-31 | 2012-07-05 | Samsung Electronics Co., Ltd. | Stack type semiconductor package and method of fabricating the same |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105391823A (zh) * | 2015-11-25 | 2016-03-09 | 上海新储集成电路有限公司 | 一种降低移动设备尺寸和功耗的方法 |
CN105391823B (zh) * | 2015-11-25 | 2019-02-12 | 上海新储集成电路有限公司 | 一种降低移动设备尺寸和功耗的方法 |
CN109509746A (zh) * | 2017-09-15 | 2019-03-22 | 东芝存储器株式会社 | 半导体装置 |
CN109509746B (zh) * | 2017-09-15 | 2022-11-25 | 铠侠股份有限公司 | 半导体装置 |
CN110033813A (zh) * | 2018-08-31 | 2019-07-19 | 济南德欧雅安全技术有限公司 | 一种翻译器设备 |
Also Published As
Publication number | Publication date |
---|---|
EP2775512A3 (en) | 2017-04-19 |
EP2775512A2 (en) | 2014-09-10 |
JP5940577B2 (ja) | 2016-06-29 |
US20140252632A1 (en) | 2014-09-11 |
KR20140109833A (ko) | 2014-09-16 |
JP2014175662A (ja) | 2014-09-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104037167A (zh) | 半导体器件 | |
EP2996146B1 (en) | Semiconductor package assembly | |
US9991221B2 (en) | Semiconductor integrated circuit device | |
US9947624B2 (en) | Semiconductor package assembly with through silicon via interconnect | |
TWI703704B (zh) | 堆疊式封裝、行動電腦裝置以及電子裝置 | |
US9252141B2 (en) | Semiconductor integrated circuit, method for fabricating the same, and semiconductor package | |
KR20170075125A (ko) | 반도체 패키지 및 제조 방법 | |
US10903198B2 (en) | Semiconductor package assembly and method for forming the same | |
KR20180055566A (ko) | 관통 실리콘 비아 기술을 적용한 반도체 패키지 및 제조 방법 | |
US20140246781A1 (en) | Semiconductor device, method of forming a packaged chip device and chip package | |
US9818724B2 (en) | Interposer-chip-arrangement for dense packaging of chips | |
US11942455B2 (en) | Stacked semiconductor dies for semiconductor device assemblies | |
US10049999B2 (en) | Electronic device | |
EP4020554A1 (en) | Semiconductor device with dummy thermal features on interposer | |
KR20160047841A (ko) | 반도체 패키지 | |
CN103311214A (zh) | 一种用于叠层封装的基板 | |
EP4135032A1 (en) | Semiconductor package with reduced connection length | |
TW201431040A (zh) | 三維直通矽晶貫孔結構 | |
TW202109800A (zh) | 具有微細間距矽穿孔封裝的扇出型封裝晶片結構以及扇出型封裝單元 | |
US20240096861A1 (en) | Semiconductor package assembly | |
KR100851108B1 (ko) | 웨이퍼 레벨 시스템 인 패키지 및 그 제조 방법 | |
TWI588940B (zh) | 封裝疊層及其製造方法 | |
CN117747593A (zh) | 半导体封装组件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Neubiburg, Germany Applicant after: Intel Mobile Communications GmbH Address before: Neubiburg, Germany Applicant before: Intel Mobile Communications GmbH |
|
COR | Change of bibliographic data | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140910 |