CN109509746B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109509746B
CN109509746B CN201810154959.9A CN201810154959A CN109509746B CN 109509746 B CN109509746 B CN 109509746B CN 201810154959 A CN201810154959 A CN 201810154959A CN 109509746 B CN109509746 B CN 109509746B
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semiconductor
semiconductor device
semiconductor layer
logic chip
chips
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CN109509746A (zh
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河崎一茂
栗田洋一郎
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供一种能够使包含多个半导体芯片的积层体的良品率提高的半导体装置。实施方式的半导体装置具备：部件，包含第1面、与所述第1面为相反侧的第2面、及在沿所述第1面的第1方向上延伸的至少一条配线；两个以上的积层体，在所述第1面上，在所述第1方向上排列而配置；及两个以上的逻辑芯片，分别电连接在所述积层体。所述两个以上的积层体分别包含在与所述第1面垂直的第2方向上积层的多个半导体芯片。所述多个半导体芯片分别包含第1半导体层及第2半导体层。所述第1半导体层及第2半导体层具有设置着功能元件的元件面、及与所述元件面为相反侧的背面，且以所述第2半导体层的元件面面向所述第1半导体层的元件面的方式贴合。

Description

半导体装置
[相关申请案]
本申请享有以日本专利申请2017-178301号(申请日：2017年9月15日)为基础申请的优先权。本申请是通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及一种半导体装置。
背景技术
存在积层多个半导体芯片并进行树脂密封而成的半导体装置。这种半导体装置的制造良率主要取决于包含多个半导体芯片的积层体的良品率。例如，随着电路规模的大型化、或存储装置的存储容量的扩大，而各半导体芯片的尺寸变大。伴随于此，各半导体芯片中包含构造缺陷的概率变高，良品率降低。因此，存在包含多个半导体芯片的积层体的良品率大幅度降低，而使半导体装置的制造成本上升的情况。
发明内容
实施方式提供一种能够使包含多个半导体芯片的积层体的良品率提高的半导体装置。
实施方式的半导体装置具备：部件，包含第1面、与所述第1面为相反侧的第2面、及在沿所述第1面的第1方向上延伸的至少一条配线；两个以上的积层体，在所述第1面上，在所述第1方向上排列而配置；及两个以上的逻辑芯片，分别电连接在所述积层体。所述两个以上的积层体分别包含在与所述第1面垂直的第2方向上积层的多个半导体芯片。所述多个半导体芯片分别包含第1半导体层及第2半导体层。所述第1半导体层及第2半导体层具有设置着功能元件的元件面、及与所述元件面为相反侧的背面，且以所述第2半导体层的元件面面向所述第1半导体层的元件面的方式贴合。
附图说明
图1是表示第1实施方式的半导体装置的示意性剖视图。
图2是表示半导体芯片的积层构造的示意性剖视图。
图3是表示第1实施方式的半导体装置的构成的示意图。
图4(a)及(b)是表示半导体芯片与外部电路的连接方法的示意图。
图5是表示半导体芯片与外部电路的另一连接方法的示意图。
图6(a)及(b)是表示第2实施方式的半导体装置的示意性剖视图。
图7是表示第2实施方式的半导体装置的构成的示意图。
图8是表示半导体芯片的积层体与逻辑芯片的位置关系的示意性俯视图。
图9是表示第2实施方式的另一半导体装置的示意性剖视图。
具体实施方式
以下，一边参照附图，一边对实施方式进行说明。对附图中的相同的部分标注相同的编号而适当省略其详细的说明，并针对不同的部分进行说明。此外，附图是示意性或概念性图，各部分的厚度与宽度的关系、部分间的大小的比率等未必与实物相同。另外，即便在表示相同的部分的情况下，有时也根据附图而使相互的尺寸或比率不同地表示。
此外，使用各图中所示的X轴、Y轴及Z轴来说明各部分的配置及构成。X轴、Y轴及Z轴相互正交，分别表示X方向、Y方向及Z方向。另外，有时将Z方向设为上方，并将其相反方向设为下方而进行说明。
[第1实施方式]
图1是表示第1实施方式的半导体装置1的示意性剖视图。半导体装置1包含部件BP、积层体STC1及积层体STC2。积层体STC1及STC2分别包含多个半导体芯片10。
部件BP例如是安装衬底，且具有第1面BP1及第2面BP2。第2面BP2是与第1面BP1为相反侧的表面。部件BP包含在沿第1面BP1的X方向或Y方向上延伸的至少一条配线11。另外，部件BP也可为包含隔着层间绝缘膜而设置的多个配线层的所谓内插器(interposer)。
在部件BP的第2面BP2，设置包含多个焊球23的BGA(Ball Grid Array，球栅阵列)。焊球23分别电连接在设置于第1面BP1的配线11。另外，在将半导体装置1安装在未图示的电路衬底上的情况下，焊球23将配线11与外部电路(未图示)电连接。
积层体STC1及STC2在第1面BP1上，例如在X方向上排列而配置。积层体STC1及STC2分别包含在Z方向上积层的多个半导体芯片10。半导体芯片10包含半导体层13及半导体层15。半导体层13及半导体层15分别具有设置着功能元件的元件面、及与元件面为相反侧的背面。半导体层13与半导体层15以半导体层15的元件面15A面向半导体层13的元件面13A的方式贴合(参照图2)。
半导体装置1还具备分别电连接在积层体STC1及STC2的逻辑芯片30。
像图1所示那样，半导体芯片10经由连接凸块17而积层在配线板20之上。逻辑芯片30配置在配线板20的背面侧。配线板20具有：上表面，具有连接在半导体芯片10的配线(未图示)；及背面，配置着逻辑芯片30及倒装芯片凸块(以下称为FC(Flip Chip，倒装芯片)凸块27)。
逻辑芯片30例如经由以贯通配线板20的方式设置的通孔触点而电连接在积层体STC1或STC2。FC凸块27连接在设置于部件BP的第1面BP1的配线11。FC凸块27例如经由设置在配线板20之上表面的配线(未图示)而将配线11与逻辑芯片30之间电连接。另外，另一FC凸块27经由设置在配线板20之上表面的另一配线(未图示)而将配线11与积层体STC1或STC2之间电连接。
积层体STC1、STC2及逻辑芯片30例如使用密封树脂40而气密密封在部件BP之上。
在本实施方式中，通过将两个积层体STC1及STC2配置在部件BP上，能够使积层体STC1及STC2的良品率提高，从而提高半导体装置1的制造良率。
例如，在半导体装置1为半导体存储装置的情况下，半导体芯片10分别是存储器芯片，积层体STC1及STC2分别作为积层多个存储器芯片而成的存储体(memory stack)发挥功能。半导体装置1具有使积层体STC1的存储容量与积层体STC2的存储容量合起来的合计存储容量。而且，在半导体装置1中，与利用一个存储体实现相同的存储容量的情况相比，能够使存储器芯片的尺寸减半。
存储器芯片的良品率较大程度地取决于其芯片尺寸。例如，形成在硅晶片上的多个存储器芯片中，其内部包含构造缺陷的存储器芯片成为不良品，不包含构造缺陷的存储器芯片成为良品。硅晶片上的构造缺陷例如并非均匀地分布，而是具有取决于某些因素的分布。因此，通过减小芯片尺寸，能够使存储器芯片的良品率进一步提高。结果，存储体的良品率通过减小存储器芯片的尺寸而得以显著地改善。
图2是表示半导体芯片10的积层构造的示意性剖视图。像图2所示那样，半导体芯片10具有使半导体层13与半导体层15贴合而成的构造。半导体层13及15例如通过对半导体衬底进行研削或研磨而进行薄层化从而形成。
半导体层13具有元件面13A及背面13B，半导体层15具有元件面15A及背面15B。在元件面13A及15A之上，例如分别设置包含三维配置的存储单元的存储单元阵列MCA。另外，在半导体层13中，设置从背面13B到达存储单元阵列MCA的通孔触点35，在半导体层15中，设置从背面15B到达存储单元阵列MCA的通孔触点37。通孔触点35及37分别连接在存储单元阵列MCA的接触垫(未图示)。
半导体层13及15以元件面13A与元件面15A面对面的方式贴合。半导体层13及15经由设置在存储单元阵列MCA的表面的接触垫39而电连接。
此外，多个半导体芯片10在Z方向上积层。在Z方向上相邻的半导体芯片10经由将一通孔触点35与另一通孔触点37连通的连接凸块17而连接。
例如，在半导体芯片10中，设置在元件面13A之上的存储单元阵列MCA、与设置在元件面15A之上的存储单元阵列MCA之间的间隔WA比在Z方向上相邻的半导体芯片10的背面13B与背面15B之间的间隔WB窄。在以元件面13A上的存储单元阵列MCA与元件面15A上的存储单元阵列MCA相接的方式贴合的情况下，间隔WA变为零。
图3是表示第1实施方式的半导体装置1的构成的示意图。半导体装置1例如是半导体存储装置，包含作为存储体而发挥功能的积层体STC1及STC2。
例如，电源电压Vdd经由共通的配线而被供给到积层体STC1及STC2。另一方面，积层体STC1及STC2分别经由不同的配线及逻辑芯片30而连接在外部电路(未图示)。
积层体STC1经由连接导体BCP1而连接在逻辑芯片30，且经由配线ICL1而连接在外部电路。连接导体BCP1例如包含位于积层体STC1的最下层的半导体芯片10的通孔触点35(参照图2)。另外，配线ICL1例如包含形成在配线板20的表面的配线(未图示)、及设置在部件BP的第1面BP1的配线11。
积层体STC2经由连接导体BCP2而连接在另一逻辑芯片30，且经由配线ICL2而连接在外部电路。连接导体BCP2例如包含位于积层体STC2的最下层的半导体芯片10的通孔触点35(参照图2)。另外，配线ICL2例如包含形成在配线板20的表面的另一配线(未图示)、及另一配线11。
也就是说，积层体STC1及STC2分别经由独立的路径而连接在外部电路。这种构成在如下情况下有效，即，在外部电路与逻辑芯片30之间收发数据及命令的信号频带比能够使积层体STC1及STC2作为一体的存储体而动作的信号频带窄。
图4(a)及(b)是表示经由逻辑芯片30的半导体芯片10与外部电路的连接方法的示意图。图4(a)是表示半导体芯片10与外部电路之间的连接路径的示意图。图4(b)是表示在半导体芯片10与外部电路之间收发的信号的示意图。
像图4(a)所示那样，逻辑芯片30与外部电路之间利用配线ICL而连接，逻辑芯片30与各半导体芯片10之间利用连接导体BCP而连接。配线ICL是图3所示的配线ICL1及ICL2中的任一个。
半导体芯片10相对于逻辑芯片30并联连接。在该例中，逻辑芯片30与多个半导体芯片10之间经由多个连接导体BCP而连接。各连接导体BCP将一个半导体芯片连接到逻辑芯片30。
连接导体BCP是在积层体STC1或STC2的内部在Z方向上延伸的导体。连接导体BCP例如以包含连接凸块17、通孔触点35、37及接触垫39中之至少一个的方式构成(参照图2)。另外，各半导体芯片10与逻辑芯片30也可经由连接导体BCP及设置在配线板20之上的配线(未图示)而电连接(参照图1)。
在该情况下，逻辑芯片30将从外部电路发送而来的命令及数据分配到各半导体芯片10的接口电路，对从各半导体芯片10接收到的数据进行整合并输出到外部电路。
像图4(b)所示那样，在逻辑芯片30与外部电路之间收发的信号的频率fc1比在逻辑芯片30与各半导体芯片之间收发的信号的频率fc2高。逻辑芯片30例如包含缓冲存储器，对输入输出信号的频率进行转换。
图5是表示半导体芯片10与外部电路之间的另一连接方法的示意图。在该例中，逻辑芯片30经由一个连接导体BCP而连接在多个半导体芯片10。
例如，逻辑芯片30相对于积层在配线板20之上的多个半导体芯片10，经由一个连接导体BCP而进行数据的收发。另外，也可在逻辑芯片30与多个半导体芯片10之间，配置多个与两个以上的半导体芯片10相连的连接导体BCP。
此外，图2所示的半导体芯片10的积层构造、及图4(a)、图4(b)、图5所示的各半导体芯片10与逻辑芯片30之间的连接形态也被应用在以下的实施方式中。
[第2实施方式]
图6(a)及(b)是表示第2实施方式的半导体装置2及3的示意性剖视图。图7是表示第2实施方式的半导体装置2、3的构成的示意图。图8是表示半导体芯片的积层体STC1、STC2与逻辑芯片30的位置关系的示意性俯视图。
半导体装置2及3包含积层体STC1、积层体STC2、逻辑芯片30及配线板50。积层体STC1及STC2配置在配线板50之上表面，且分别包含多个半导体芯片10。逻辑芯片30配置在配线板50的背面。积层体STC1及STC2例如也可经由FC凸块(参照图1)而配置在配线板50之上。
配线板50例如包含树脂层41、至少一条配线43及接触垫45(参照图9)。至少一条配线43设置在树脂层41的上表面，接触垫45设置在树脂层41的背面。至少一条配线43与接触垫45例如经由贯穿树脂层41的通孔触点47而电连接。
像图6(a)所示那样，在配线板50的背面配置着焊球23及逻辑芯片30。焊球23及逻辑芯片30经由接触垫及通孔触点而连接在设置于配线板50的上表面的配线。逻辑芯片30以在Z方向上观察时与积层体STC1及STC2这两者重叠的方式配置(参照图8)。
在配线板50之上表面，设置着图7所示的配线ICL3、ICL4及ICL5。例如，外部电路经由焊球23而连接在配线ICL3。此外，配线ICL3连接在逻辑芯片30。也就是说，逻辑芯片30经由配线ICL3而与外部电路进行信号的收发。
另外，积层体STC1经由配线ICL4而与逻辑芯片30进行信号的收发。积层体STC2经由配线ICL5而与逻辑芯片30进行信号的收发。配线ICL4及ICL5分别连接在积层体STC1及STC2的连接导体BCP。
像图6(b)所示那样，积层体STC1及STC2的连接导体BCP也可配置在逻辑芯片30之上方。例如，像图8所示那样，逻辑芯片30以在Z方向上观察时与积层体STC1及STC2这两者重叠的方式配置。而且，连接导体BCP在逻辑芯片30之上方在Z方向上延伸。
通过像这样在逻辑芯片30的上方配置连接导体BCP，能够缩短配线ICL4及ICL5，从而能够加快各半导体芯片10与逻辑芯片30之间的信号的传输速度。
图9是表示第2实施方式的另一半导体装置4的示意性剖视图。半导体装置4包含积层体STC1、积层体STC2、逻辑芯片30、配线板50及存储器芯片70。积层体STC1及STC2配置在配线板50之上表面，逻辑芯片30及存储器芯片70配置在配线板50的背面。
像图9所示那样，配线板50包含树脂层41、配线43及接触垫45。配线43设置在树脂层41的上表面，接触垫45设置在树脂层41的背面。配线43与接触垫45例如经由贯穿树脂层41的通孔触点47而电连接。配线板50的Z方向的厚度Ws例如比半导体芯片10的Z方向的厚度Wc薄。
逻辑芯片30以在Z方向上观察时与积层体STC1及STC2这两者重叠的方式配置(参照图8)。另外，积层体STC1及STC2的连接导体BCP配置在逻辑芯片30之上方。此外，连接导体BCP经由贯穿配线板50的通孔触点47而连接在逻辑芯片30。
存储器芯片70经由设置在配线板50的上表面的配线43而连接在逻辑芯片30。存储器芯片70作为逻辑芯片30的缓冲存储器而发挥功能。
此外，配线板50并非限定于所述示例，例如也可为积层着多个配线层的所谓内插器。
已对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意图限定发明的范围。这些新颖的实施方式能以其它各种方式实施，可在不脱离发明的主旨的范围内，进行各种省略、替换及变更。这些实施方式或其变化包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1、2、3、4 半导体装置
10 半导体芯片
11、43 配线
13、15 半导体层
13A、15A 元件面
13B、15B 背面
17 连接凸块
23 焊球
27 FC凸块
20、50 配线板
30 逻辑芯片
35、37、47 通孔触点
39 接触垫
40 密封树脂
41 树脂层
70 存储器芯片
BCP 连接导体
BP 部件
BP1 第1面
BP2 第2面
ICL 配线
MCA 存储单元阵列
STC1、STC2 积层体

Claims (18)

1.一种半导体装置，其特征在于具备：
部件，包含第1面、与所述第1面为相反侧的第2面、及在沿所述第1面的第1方向上延伸的至少一条配线；
两个以上的积层体，是在所述第1面上在所述第1方向上排列而配置的两个以上的积层体，且分别包含在与所述第1面垂直的第2方向上积层的多个半导体芯片；
两个以上的逻辑芯片，分别电连接在所述积层体；及
在所述部件的所述第1面之上的树脂部件，将所述两个以上的积层体及所述两个以上的逻辑芯片密封在所述部件之上，且所述树脂部件与所述部件的所述第1面物理接触；且
所述多个半导体芯片分别包含第1半导体层及第2半导体层，
所述第1半导体层及第2半导体层具有设置着功能元件的元件面、及与所述元件面为相反侧的背面，且以所述第2半导体层的元件面面向所述第1半导体层的元件面的方式贴合。
2.根据权利要求1所述的半导体装置，其特征在于，
所述部件包含将所述逻辑芯片的一个与所述积层体的一个电连接的配线。
3.根据权利要求1所述的半导体装置，其特征在于，
所述积层体包含电连接在所述逻辑芯片的连接导体，
所述连接导体将所述多个半导体芯片分别与所述逻辑芯片电连接。
4.根据权利要求1所述的半导体装置，其特征在于，
所述积层体包含电连接在所述逻辑芯片的连接导体，
所述连接导体由所述多个半导体芯片所共有，且电连接在所述逻辑芯片。
5.根据权利要求1所述的半导体装置，其特征在于，
还具备配线板，所述配线板配置在所述部件的第1面上，
所述多个半导体芯片积层在所述配线板上，
所述逻辑芯片中的一个配置在所述部件与所述配线板之间。
6.根据权利要求5所述的半导体装置，其特征在于，
还具备焊接凸块，所述焊接凸块将所述配线板与所述部件连接，
设置在所述配线板上的积层体经由所述配线板及所述焊接凸块而电连接在所述部件的所述配线。
7.根据权利要求1所述的半导体装置，其特征在于，
还具备焊接凸块，所述焊接凸块设置在所述部件的第2面上，
所述焊接凸块与所述逻辑芯片中的一个经由所述配线而电连接。
8.根据权利要求1所述的半导体装置，其特征在于，
设置在所述第1半导体层的元件面上的第1构造体、与设置在所述第2半导体层的元件面上的第2构造体之间的第1间隔比多个所述半导体芯片中的在所述第2方向上相邻的半导体芯片间的第2间隔窄。
9.根据权利要求8所述的半导体装置，其特征在于，
所述积层体还包含设置在所述相邻的半导体芯片间的连接凸块，
所述第1构造体及所述第2构造体分别包含接触垫，
所述第1半导体层与所述第2半导体层经由所述接触垫而贴合。
10.一种半导体装置，其特征在于具备：
部件，包含第1面、与所述第1面为相反侧的第2面、及在沿所述第1面的第1方向上延伸的至少一条配线；
两个以上的积层体，在所述第1面上，在所述第1方向上排列而配置，且包含在与所述第1面垂直的第2方向上积层的多个半导体芯片；及
逻辑芯片，设置在所述部件的第2面上，且电连接在所述两个以上的积层体；
所述多个半导体芯片分别包含第1半导体层及第2半导体层，
所述第1半导体层及第2半导体层分别具有设置着功能元件的元件面、及与所述元件面为相反侧的背面，且以所述第2半导体层的元件面面向所述第1半导体层的元件面的方式贴合，
所述逻辑芯片设置于如下位置，即，在所述第2方向上观察时与所述两个以上的积层体中的相邻地配置的两个积层体重叠的位置。
11.根据权利要求10所述的半导体装置，其特征在于，
所述两个积层体分别包含在所述第2方向上延伸且电连接在所述逻辑芯片的连接导体，
所述连接导体设置于在所述第2方向上观察时与所述逻辑芯片重叠的位置。
12.根据权利要求11所述的半导体装置，其特征在于，
所述连接导体仅设置于在所述第2方向上观察时与所述逻辑芯片重叠的位置，且所述连接导体设置在所述两个积层体中，但不设置在所述两个积层体的中心部分。
13.根据权利要求11或12所述的半导体装置，其特征在于，
所述部件包含设置在所述连接导体与所述逻辑芯片之间的通孔触点，
所述连接导体经由所述通孔触点而连接在所述逻辑芯片。
14.根据权利要求10所述的半导体装置，其特征在于，
所述部件具有比所述半导体芯片的所述第2方向的厚度薄的所述第2方向的厚度。
15.根据权利要求10所述的半导体装置，其特征在于还具备存储器芯片，所述存储器芯片设置在所述部件的第2面上且电连接在所述逻辑芯片。
16.根据权利要求10所述的半导体装置，其特征在于还具备树脂部件，所述树脂部件设置在所述部件的第2面上且覆盖所述逻辑芯片。
17.根据权利要求10所述的半导体装置，其特征在于还具备焊接凸块，所述焊接凸块设置在所述部件的第2面上，且所述第2方向的厚度比所述逻辑芯片的所述第2方向的厚度厚。
18.根据权利要求17所述的半导体装置，其特征在于，
所述部件包含连接在所述配线的通孔触点，
所述焊接凸块经由所述通孔触点而连接在所述配线。
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